DE60029826D1 - Mehrratentransportsystem sowie chipsatz - Google Patents
Mehrratentransportsystem sowie chipsatzInfo
- Publication number
- DE60029826D1 DE60029826D1 DE60029826T DE60029826T DE60029826D1 DE 60029826 D1 DE60029826 D1 DE 60029826D1 DE 60029826 T DE60029826 T DE 60029826T DE 60029826 T DE60029826 T DE 60029826T DE 60029826 D1 DE60029826 D1 DE 60029826D1
- Authority
- DE
- Germany
- Prior art keywords
- data
- signal
- clock signal
- clock
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- Computer Hardware Design (AREA)
- Communication Control (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Static Random-Access Memory (AREA)
- Radar Systems Or Details Thereof (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US468606 | 1990-01-23 | ||
US09/468,606 US6631144B1 (en) | 1999-12-21 | 1999-12-21 | Multi-rate transponder system and chip set |
PCT/DK2000/000723 WO2001047173A2 (en) | 1999-12-21 | 2000-12-21 | A multi-rate transponder system and chip set |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60029826D1 true DE60029826D1 (de) | 2006-09-14 |
DE60029826T2 DE60029826T2 (de) | 2007-03-01 |
Family
ID=23860489
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60029826T Expired - Lifetime DE60029826T2 (de) | 1999-12-21 | 2000-12-21 | Mehrratentransportsystem sowie chipsatz |
Country Status (8)
Country | Link |
---|---|
US (1) | US6631144B1 (de) |
EP (1) | EP1243087B1 (de) |
CN (1) | CN1227833C (de) |
AT (1) | ATE335318T1 (de) |
AU (1) | AU2152201A (de) |
CA (1) | CA2395538C (de) |
DE (1) | DE60029826T2 (de) |
WO (1) | WO2001047173A2 (de) |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7227918B2 (en) * | 2000-03-14 | 2007-06-05 | Altera Corporation | Clock data recovery circuitry associated with programmable logic device circuitry |
US7333570B2 (en) | 2000-03-14 | 2008-02-19 | Altera Corporation | Clock data recovery circuitry associated with programmable logic device circuitry |
US7050463B1 (en) * | 2000-10-31 | 2006-05-23 | Texas Instruments Incorporated | Automatic bit-rate detection scheme for use on SONET transceiver |
JP4426739B2 (ja) * | 2001-06-26 | 2010-03-03 | 日本オプネクスト株式会社 | 光モジュールおよびその製造方法 |
US7142623B2 (en) * | 2002-05-31 | 2006-11-28 | International Business Machines Corporation | On-chip system and method for measuring jitter tolerance of a clock and data recovery circuit |
US8155236B1 (en) | 2002-06-21 | 2012-04-10 | Netlogic Microsystems, Inc. | Methods and apparatus for clock and data recovery using transmission lines |
US7437079B1 (en) | 2002-06-25 | 2008-10-14 | Finisar Corporation | Automatic selection of data rate for optoelectronic devices |
US7664401B2 (en) | 2002-06-25 | 2010-02-16 | Finisar Corporation | Apparatus, system and methods for modifying operating characteristics of optoelectronic devices |
US7809275B2 (en) | 2002-06-25 | 2010-10-05 | Finisar Corporation | XFP transceiver with 8.5G CDR bypass |
US7486894B2 (en) * | 2002-06-25 | 2009-02-03 | Finisar Corporation | Transceiver module and integrated circuit with dual eye openers |
US7561855B2 (en) | 2002-06-25 | 2009-07-14 | Finisar Corporation | Transceiver module and integrated circuit with clock and data recovery clock diplexing |
US7477847B2 (en) | 2002-09-13 | 2009-01-13 | Finisar Corporation | Optical and electrical channel feedback in optical transceiver module |
JP4136601B2 (ja) * | 2002-10-30 | 2008-08-20 | 三菱電機株式会社 | トランシーバモジュール |
US7474612B1 (en) * | 2003-03-20 | 2009-01-06 | Pmc- Sierra, Inc. | Multi-function bypass port and port bypass circuit |
US7751726B1 (en) * | 2003-06-24 | 2010-07-06 | Cisco Technology, Inc. | Automatic selection of the performance monitoring based on client type |
US7542483B1 (en) * | 2003-06-25 | 2009-06-02 | Cisco Technology, Inc. | Recoverable reference clock architecture for SONET/SDH and ethernet mixed bidirectional applications |
US7352835B1 (en) * | 2003-09-22 | 2008-04-01 | Altera Corporation | Clock data recovery circuitry with dynamic support for changing data rates and a dynamically adjustable PPM detector |
US7480358B2 (en) * | 2004-02-25 | 2009-01-20 | Infineon Technologies Ag | CDR-based clock synthesis |
US7397825B2 (en) * | 2004-03-10 | 2008-07-08 | Scientific-Atlanta, Inc. | Transport stream dejitterer |
KR100603616B1 (ko) * | 2004-12-16 | 2006-07-24 | 한국전자통신연구원 | 광전송 시스템에서 소스 동기 클럭을 이용한 클럭 동기 장치 |
KR100687723B1 (ko) * | 2004-12-17 | 2007-02-27 | 한국전자통신연구원 | 광 트랜시버의 동작 테스트 장치 |
US7532697B1 (en) * | 2005-01-27 | 2009-05-12 | Net Logic Microsystems, Inc. | Methods and apparatus for clock and data recovery using a single source |
US20060215296A1 (en) * | 2005-03-24 | 2006-09-28 | Gennum Corporation | Bidirectional referenceless communication circuit |
CN100407699C (zh) * | 2005-04-01 | 2008-07-30 | 华为技术有限公司 | 信号拆分合并的方法及装置 |
US7304498B2 (en) * | 2005-07-20 | 2007-12-04 | Altera Corporation | Clock circuitry for programmable logic devices |
US7432750B1 (en) | 2005-12-07 | 2008-10-07 | Netlogic Microsystems, Inc. | Methods and apparatus for frequency synthesis with feedback interpolation |
US7738448B2 (en) * | 2005-12-29 | 2010-06-15 | Telefonaktiebolaget Lm Ericsson (Publ) | Method for generating and sending signaling messages |
US7729415B1 (en) * | 2006-02-14 | 2010-06-01 | Xilinx, Inc. | High-speed interface for a programmable device |
US20070253474A1 (en) * | 2006-04-27 | 2007-11-01 | Finisar Corporation | Generating eye-diagrams and network protocol analysis of a data signal |
CN101098205A (zh) * | 2006-06-27 | 2008-01-02 | 中兴通讯股份有限公司 | 一种实现任意速率业务接入信号的恢复装置及控制方法 |
CN101232340B (zh) | 2007-01-23 | 2012-10-03 | 华为技术有限公司 | 通信***、方法、发送装置以及接收装置 |
US7881608B2 (en) * | 2007-05-10 | 2011-02-01 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd | Methods and apparatuses for measuring jitter in a transceiver module |
US7924184B1 (en) * | 2007-09-24 | 2011-04-12 | Altera Corporation | High-speed serial interface circuitry for programmable integrated circuit devices |
CN101729065B (zh) * | 2008-10-14 | 2012-05-23 | 联咏科技股份有限公司 | 频率合成器及其频率预除电路与其频率合成方法 |
EP2262139A1 (de) * | 2009-06-12 | 2010-12-15 | Alcatel Lucent | Variables Bitratengerät |
US8423814B2 (en) * | 2010-03-19 | 2013-04-16 | Netlogic Microsystems, Inc. | Programmable drive strength in memory signaling |
US8638896B2 (en) * | 2010-03-19 | 2014-01-28 | Netlogic Microsystems, Inc. | Repeate architecture with single clock multiplier unit |
US8520744B2 (en) * | 2010-03-19 | 2013-08-27 | Netlogic Microsystems, Inc. | Multi-value logic signaling in multi-functional circuits |
US8494377B1 (en) | 2010-06-30 | 2013-07-23 | Netlogic Microsystems, Inc. | Systems, circuits and methods for conditioning signals for transmission on a physical medium |
US8537949B1 (en) | 2010-06-30 | 2013-09-17 | Netlogic Microsystems, Inc. | Systems, circuits and methods for filtering signals to compensate for channel effects |
US8817855B2 (en) * | 2012-10-04 | 2014-08-26 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method and apparatus for aligning and integrating serial data streams |
US9001275B2 (en) * | 2012-11-19 | 2015-04-07 | Andrew Joo Kim | Method and system for improving audio fidelity in an HDMI system |
KR20140112241A (ko) * | 2013-03-13 | 2014-09-23 | 삼성전자주식회사 | 올-디지털 위상 동기 루프와 이의 동작 방법 |
US9609400B2 (en) * | 2013-08-22 | 2017-03-28 | Nec Corporation | Reconfigurable and variable-rate shared multi-transponder architecture for flexible ethernet-based optical networks |
US9792247B2 (en) * | 2014-07-18 | 2017-10-17 | Qualcomm Incorporated | Systems and methods for chip to chip communication |
US9509490B1 (en) * | 2015-09-21 | 2016-11-29 | Apple Inc. | Reference clock sharing |
KR102580172B1 (ko) | 2019-05-05 | 2023-09-18 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 정밀한 듀티 사이클 제어를 구현하는 더블 데이터 레이트 회로 및 데이터 생성 방법 |
CN111273233B (zh) * | 2020-03-04 | 2022-05-03 | 北京环境特性研究所 | 一种电子角反射器异步脉冲检测方法及装置 |
CN112688701B (zh) * | 2020-12-22 | 2022-05-31 | 北京奕斯伟计算技术有限公司 | 接收机电路以及接收机电路控制方法 |
CN114362803B (zh) * | 2021-12-15 | 2024-03-15 | 长光卫星技术股份有限公司 | 一种基于fpga的连续可变速率卫星通信转发器*** |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3411881A1 (de) | 1984-03-30 | 1985-10-10 | Siemens AG, 1000 Berlin und 8000 München | Verfahren und schaltungsanordnung zum uebertragen von mit einer ersten bitrate auftretenden datensignalbits in einem bitstrom mit einer gegenueber der ersten bitrate hoeheren zweiten bitrate |
JPH02246442A (ja) * | 1989-03-17 | 1990-10-02 | Fujitsu Ltd | 光中継器の位相補償方式 |
JPH0774673A (ja) * | 1993-09-03 | 1995-03-17 | Chikusanyo Denshi Gijutsu Kenkyu Kumiai | 無線式データキャリア装置 |
US5566180A (en) * | 1994-12-21 | 1996-10-15 | Hewlett-Packard Company | Method for recognizing events and synchronizing clocks |
US5696800A (en) * | 1995-03-22 | 1997-12-09 | Intel Corporation | Dual tracking differential manchester decoder and clock recovery circuit |
GB9514956D0 (en) | 1995-07-21 | 1995-09-20 | British Telecomm | Transmission of digital signals |
-
1999
- 1999-12-21 US US09/468,606 patent/US6631144B1/en not_active Expired - Fee Related
-
2000
- 2000-12-21 CN CNB008190658A patent/CN1227833C/zh not_active Expired - Fee Related
- 2000-12-21 AU AU21522/01A patent/AU2152201A/en not_active Abandoned
- 2000-12-21 WO PCT/DK2000/000723 patent/WO2001047173A2/en active IP Right Grant
- 2000-12-21 DE DE60029826T patent/DE60029826T2/de not_active Expired - Lifetime
- 2000-12-21 AT AT00984926T patent/ATE335318T1/de not_active IP Right Cessation
- 2000-12-21 CA CA002395538A patent/CA2395538C/en not_active Expired - Fee Related
- 2000-12-21 EP EP00984926A patent/EP1243087B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1243087A2 (de) | 2002-09-25 |
WO2001047173A3 (en) | 2001-11-15 |
WO2001047173A2 (en) | 2001-06-28 |
US6631144B1 (en) | 2003-10-07 |
EP1243087B1 (de) | 2006-08-02 |
CA2395538C (en) | 2007-09-18 |
CN1227833C (zh) | 2005-11-16 |
DE60029826T2 (de) | 2007-03-01 |
AU2152201A (en) | 2001-07-03 |
ATE335318T1 (de) | 2006-08-15 |
CN1435016A (zh) | 2003-08-06 |
CA2395538A1 (en) | 2001-06-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: HEYER, V., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 806 |