DE60004799D1 - Verzögerungsstabilisierendes system für eine integrierte schaltung - Google Patents
Verzögerungsstabilisierendes system für eine integrierte schaltungInfo
- Publication number
- DE60004799D1 DE60004799D1 DE60004799T DE60004799T DE60004799D1 DE 60004799 D1 DE60004799 D1 DE 60004799D1 DE 60004799 T DE60004799 T DE 60004799T DE 60004799 T DE60004799 T DE 60004799T DE 60004799 D1 DE60004799 D1 DE 60004799D1
- Authority
- DE
- Germany
- Prior art keywords
- delay
- integrated circuit
- stabilizing system
- stabilizing
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00078—Fixed delay
- H03K2005/00097—Avoiding variations of delay using feedback, e.g. controlled by a PLL
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Logic Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/272,803 US6157231A (en) | 1999-03-19 | 1999-03-19 | Delay stabilization system for an integrated circuit |
US272803 | 1999-03-19 | ||
PCT/US2000/006351 WO2000057552A1 (en) | 1999-03-19 | 2000-03-08 | Delay stabilization system for an integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60004799D1 true DE60004799D1 (de) | 2003-10-02 |
DE60004799T2 DE60004799T2 (de) | 2004-06-03 |
Family
ID=23041364
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60004799T Expired - Fee Related DE60004799T2 (de) | 1999-03-19 | 2000-03-08 | Verzögerungsstabilisierendes system für eine integrierte schaltung |
Country Status (7)
Country | Link |
---|---|
US (1) | US6157231A (de) |
EP (1) | EP1163723B1 (de) |
JP (1) | JP2002540668A (de) |
KR (1) | KR20010112319A (de) |
DE (1) | DE60004799T2 (de) |
TW (1) | TW449975B (de) |
WO (1) | WO2000057552A1 (de) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6335955B1 (en) * | 1998-12-29 | 2002-01-01 | Intel Corporation | Connection, system and method of phase delayed synchronization in high speed digital systems using delay elements |
US6560716B1 (en) * | 1999-11-10 | 2003-05-06 | Lsi Logic Corporation | System for measuring delay of digital signal using clock generator and delay unit wherein a set of digital elements of clock generator identical to a set of digital elements of delay unit |
US6647027B1 (en) | 1999-11-10 | 2003-11-11 | Lsi Logic Corporation | Method and apparatus for multi-channel data delay equalization |
US7197659B2 (en) * | 2001-09-28 | 2007-03-27 | Intel Corporation | Global I/O timing adjustment using calibrated delay elements |
US7154978B2 (en) * | 2001-11-02 | 2006-12-26 | Motorola, Inc. | Cascaded delay locked loop circuit |
US6795959B1 (en) * | 2002-03-21 | 2004-09-21 | Lattice Semiconductor Corporation | Integrated delay discriminator for use with a field-programmable gate array and a method of determining a time delay thereof |
US7082546B2 (en) * | 2002-08-12 | 2006-07-25 | Broadcom Corporation | Low-speed DLL employing a digital phase interpolator based upon a high-speed clock |
US6870415B2 (en) * | 2002-09-12 | 2005-03-22 | Broadcom Corporation | Delay generator with controlled delay circuit |
US6974252B2 (en) * | 2003-03-11 | 2005-12-13 | Intel Corporation | Failsafe mechanism for preventing an integrated circuit from overheating |
US6891774B1 (en) | 2003-09-03 | 2005-05-10 | T-Ram, Inc. | Delay line and output clock generator using same |
US7154259B2 (en) * | 2003-10-23 | 2006-12-26 | Formfactor, Inc. | Isolation buffers with controlled equal time delays |
US6927605B2 (en) * | 2003-11-07 | 2005-08-09 | Hewlett-Packard Development Company, L.P. | System and method for dynamically varying a clock signal |
US7453258B2 (en) * | 2004-09-09 | 2008-11-18 | Formfactor, Inc. | Method and apparatus for remotely buffering test channels |
US7262624B2 (en) * | 2004-12-21 | 2007-08-28 | Formfactor, Inc. | Bi-directional buffer for interfacing test system channel |
JP4603903B2 (ja) * | 2005-02-17 | 2010-12-22 | 株式会社アドバンテスト | 負荷変動補償回路、電子デバイス、試験装置、及びタイミング発生回路 |
US7370245B1 (en) * | 2005-02-25 | 2008-05-06 | Xilinx, Inc. | Cross-correlation of delay line characteristics |
JP4358131B2 (ja) * | 2005-02-28 | 2009-11-04 | セイコーインスツル株式会社 | イメージセンサ |
US7368950B2 (en) * | 2005-11-16 | 2008-05-06 | Montage Technology Group Limited | High speed transceiver with low power consumption |
US7577039B2 (en) * | 2005-11-16 | 2009-08-18 | Montage Technology Group, Ltd. | Memory interface to bridge memory buses |
US7558124B2 (en) * | 2005-11-16 | 2009-07-07 | Montage Technology Group, Ltd | Memory interface to bridge memory buses |
EP1967860A1 (de) * | 2007-03-08 | 2008-09-10 | Matsushita Electric Industrial Co., Ltd. | Ringoszillator |
US20090207901A1 (en) * | 2008-02-19 | 2009-08-20 | Meng-Ta Yang | Delay circuit and method capable of performing online calibration |
JP5267055B2 (ja) * | 2008-10-31 | 2013-08-21 | 富士通株式会社 | 電源電圧出力回路 |
TWI401697B (zh) * | 2009-01-14 | 2013-07-11 | Novatek Microelectronics Corp | 動態調整電路系統之時脈之方法與電路系統 |
US8260708B2 (en) * | 2009-04-17 | 2012-09-04 | Empire Technology Development Llc | Usage metering based upon hardware aging |
US8258880B2 (en) * | 2010-02-26 | 2012-09-04 | Infineon Technologies Ag | Ring oscillator for providing constant oscillation frequency |
CN102959415B (zh) | 2010-07-30 | 2015-01-07 | 英派尔科技开发有限公司 | 基于老化的部件使用度量 |
US8324974B1 (en) | 2010-12-17 | 2012-12-04 | Western Digital Technologies, Inc. | Regulating power consumption of digital circuitry using a multi-layer ring oscillator |
US8390367B1 (en) * | 2011-02-15 | 2013-03-05 | Western Digital Technologies, Inc. | Ensuring minimum gate speed during startup of gate speed regulator |
KR20130042373A (ko) * | 2011-10-18 | 2013-04-26 | 삼성전자주식회사 | 반도체 메모리의 전압 조절 장치 |
CN104995841B (zh) | 2013-01-06 | 2018-02-09 | 英派尔科技开发有限公司 | 基于老化的泄漏能量减小方法和*** |
EP3510738B1 (de) * | 2016-09-08 | 2021-08-25 | Lattice Semiconductor Corporation | Taktrückgewinnung und datenwiederherstellung für programmierbare logische vorrichtungen |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62159006U (de) * | 1986-03-31 | 1987-10-08 | ||
JPS6369315A (ja) * | 1986-09-11 | 1988-03-29 | Sony Corp | Cmos回路を用いた可変遅延装置 |
JPS6369314A (ja) * | 1986-09-11 | 1988-03-29 | Sony Corp | Cmos回路を用いた可変遅延装置 |
JPH02100514A (ja) * | 1988-10-07 | 1990-04-12 | Ricoh Co Ltd | ディレイライン |
JPH02296410A (ja) * | 1989-05-11 | 1990-12-07 | Mitsubishi Electric Corp | 遅延回路 |
JPH04213213A (ja) * | 1990-12-10 | 1992-08-04 | Fujitsu Ltd | ディジタル集積回路装置 |
US5072197A (en) * | 1991-01-03 | 1991-12-10 | Hewlett-Packard Company | Ring oscillator circuit having improved frequency stability with respect to temperature, supply voltage, and semiconductor process variations |
JPH0575343A (ja) * | 1991-09-17 | 1993-03-26 | Mitsubishi Electric Corp | クロツク信号出力回路 |
US5345119A (en) * | 1992-09-16 | 1994-09-06 | At&T Bell Laboratories | Continuous-time filter tuning with a delay-locked-loop in mass storage systems or the like |
US5561692A (en) * | 1993-12-09 | 1996-10-01 | Northern Telecom Limited | Clock phase shifting method and apparatus |
US5712883A (en) * | 1996-01-03 | 1998-01-27 | Credence Systems Corporation | Clock signal distribution system |
JPH09326689A (ja) * | 1996-06-03 | 1997-12-16 | Hitachi Ltd | クロック発生回路 |
JP3694998B2 (ja) * | 1996-08-05 | 2005-09-14 | ソニー株式会社 | 電圧発生回路 |
JPH10276068A (ja) * | 1997-03-28 | 1998-10-13 | Sony Corp | リングオシレータ |
US5994938A (en) * | 1998-01-30 | 1999-11-30 | Credence Systems Corporation | Self-calibrating programmable phase shifter |
-
1999
- 1999-03-19 US US09/272,803 patent/US6157231A/en not_active Expired - Fee Related
-
2000
- 2000-03-08 JP JP2000607331A patent/JP2002540668A/ja active Pending
- 2000-03-08 KR KR1020017011615A patent/KR20010112319A/ko not_active Application Discontinuation
- 2000-03-08 EP EP00914921A patent/EP1163723B1/de not_active Expired - Lifetime
- 2000-03-08 WO PCT/US2000/006351 patent/WO2000057552A1/en not_active Application Discontinuation
- 2000-03-08 DE DE60004799T patent/DE60004799T2/de not_active Expired - Fee Related
- 2000-03-15 TW TW089104698A patent/TW449975B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1163723A1 (de) | 2001-12-19 |
KR20010112319A (ko) | 2001-12-20 |
EP1163723A4 (de) | 2002-06-19 |
EP1163723B1 (de) | 2003-08-27 |
TW449975B (en) | 2001-08-11 |
JP2002540668A (ja) | 2002-11-26 |
DE60004799T2 (de) | 2004-06-03 |
WO2000057552A1 (en) | 2000-09-28 |
US6157231A (en) | 2000-12-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |