DE3888937D1 - Verfahren zum Herstellen von integrierten Schaltungen mit FET. - Google Patents
Verfahren zum Herstellen von integrierten Schaltungen mit FET.Info
- Publication number
- DE3888937D1 DE3888937D1 DE88311215T DE3888937T DE3888937D1 DE 3888937 D1 DE3888937 D1 DE 3888937D1 DE 88311215 T DE88311215 T DE 88311215T DE 3888937 T DE3888937 T DE 3888937T DE 3888937 D1 DE3888937 D1 DE 3888937D1
- Authority
- DE
- Germany
- Prior art keywords
- fet
- integrated circuits
- manufacturing integrated
- manufacturing
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/128,834 US4844776A (en) | 1987-12-04 | 1987-12-04 | Method for making folded extended window field effect transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3888937D1 true DE3888937D1 (de) | 1994-05-11 |
DE3888937T2 DE3888937T2 (de) | 1994-07-21 |
Family
ID=22437208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3888937T Expired - Fee Related DE3888937T2 (de) | 1987-12-04 | 1988-11-25 | Verfahren zum Herstellen von integrierten Schaltungen mit FET. |
Country Status (8)
Country | Link |
---|---|
US (1) | US4844776A (de) |
EP (1) | EP0319215B1 (de) |
JP (1) | JP2780986B2 (de) |
KR (1) | KR960001602B1 (de) |
CA (1) | CA1284235C (de) |
DE (1) | DE3888937T2 (de) |
ES (1) | ES2050712T3 (de) |
HK (1) | HK43495A (de) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2780179B2 (ja) * | 1988-10-14 | 1998-07-30 | セイコーエプソン株式会社 | 半導体装置及び半導体装置の製造方法 |
US5079180A (en) * | 1988-12-22 | 1992-01-07 | Texas Instruments Incorporated | Method of fabricating a raised source/drain transistor |
US4954214A (en) * | 1989-01-05 | 1990-09-04 | Northern Telecom Limited | Method for making interconnect structures for VLSI devices |
EP0422824A1 (de) * | 1989-10-12 | 1991-04-17 | AT&T Corp. | Feldeffekttransistor mit Fenster aus Polysilizium |
US5036378A (en) * | 1989-11-01 | 1991-07-30 | At&T Bell Laboratories | Memory device |
FR2655194B1 (fr) * | 1989-11-28 | 1992-04-10 | Sgs Thomson Microelectronics | Procede de fabrication de circuits integres constituant des memoires eprom. |
DE4038177A1 (de) * | 1989-12-18 | 1991-06-20 | Telefunken Electronic Gmbh | Halbleiteranordnung und verfahren zu ihrer herstellung |
JPH03230531A (ja) * | 1990-02-06 | 1991-10-14 | Matsushita Electron Corp | 半導体装置の製造方法 |
US5879997A (en) * | 1991-05-30 | 1999-03-09 | Lucent Technologies Inc. | Method for forming self aligned polysilicon contact |
US5219793A (en) * | 1991-06-03 | 1993-06-15 | Motorola Inc. | Method for forming pitch independent contacts and a semiconductor device having the same |
US5880022A (en) * | 1991-12-30 | 1999-03-09 | Lucent Technologies Inc. | Self-aligned contact window |
KR950011982B1 (ko) * | 1992-11-06 | 1995-10-13 | 현대전자산업주식회사 | 전도물질 패드를 갖는 반도체 접속장치 및 그 제조방법 |
JPH06333944A (ja) * | 1993-05-25 | 1994-12-02 | Nippondenso Co Ltd | 半導体装置 |
US5731218A (en) * | 1993-11-02 | 1998-03-24 | Siemens Aktiengesellschaft | Method for producing a contact hole to a doped region |
DE4337355C2 (de) * | 1993-11-02 | 1997-08-21 | Siemens Ag | Verfahren zur Herstellung eines Kontaktlochs zu einem dotierten Bereich |
US5395787A (en) * | 1993-12-01 | 1995-03-07 | At&T Corp. | Method of manufacturing shallow junction field effect transistor |
US5407859A (en) * | 1993-12-01 | 1995-04-18 | At&T Corp. | Field effect transistor with landing pad |
US5420058A (en) * | 1993-12-01 | 1995-05-30 | At&T Corp. | Method of making field effect transistor with a sealed diffusion junction |
JP3238820B2 (ja) * | 1994-02-18 | 2001-12-17 | 富士通株式会社 | 半導体装置 |
US5702979A (en) * | 1994-05-31 | 1997-12-30 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
US5945738A (en) * | 1994-05-31 | 1999-08-31 | Stmicroelectronics, Inc. | Dual landing pad structure in an integrated circuit |
US5956615A (en) * | 1994-05-31 | 1999-09-21 | Stmicroelectronics, Inc. | Method of forming a metal contact to landing pad structure in an integrated circuit |
US5633196A (en) * | 1994-05-31 | 1997-05-27 | Sgs-Thomson Microelectronics, Inc. | Method of forming a barrier and landing pad structure in an integrated circuit |
US5705427A (en) * | 1994-12-22 | 1998-01-06 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
JP4156044B2 (ja) * | 1994-12-22 | 2008-09-24 | エスティーマイクロエレクトロニクス,インコーポレイテッド | 集積回路におけるランディングパッド構成体の製造方法 |
JP2790167B2 (ja) * | 1995-01-09 | 1998-08-27 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US5686761A (en) * | 1995-06-06 | 1997-11-11 | Advanced Micro Devices, Inc. | Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology |
US5719071A (en) * | 1995-12-22 | 1998-02-17 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad sturcture in an integrated circuit |
US6001726A (en) * | 1997-03-24 | 1999-12-14 | Motorola, Inc. | Method for using a conductive tungsten nitride etch stop layer to form conductive interconnects and tungsten nitride contact structure |
US6001697A (en) * | 1998-03-24 | 1999-12-14 | Mosel Vitelic Inc. | Process for manufacturing semiconductor devices having raised doped regions |
JP3939314B2 (ja) | 2004-06-10 | 2007-07-04 | 三星電子株式会社 | 空気調和装置及びその均油運転方法 |
DE102005063092B3 (de) * | 2005-12-30 | 2007-07-19 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement mit einer Kontaktstruktur mit erhöhter Ätzselektivität |
DE102006004412B3 (de) * | 2006-01-31 | 2007-08-30 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Erhöhen der Ätzselektivität in einer Kontaktstruktur in Halbleiterbauelementen |
JP2008058628A (ja) * | 2006-08-31 | 2008-03-13 | Ricoh Co Ltd | 光走査装置および光走査装置を備えた画像形成装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4384301A (en) * | 1979-11-07 | 1983-05-17 | Texas Instruments Incorporated | High performance submicron metal-oxide-semiconductor field effect transistor device structure |
US4324038A (en) * | 1980-11-24 | 1982-04-13 | Bell Telephone Laboratories, Incorporated | Method of fabricating MOS field effect transistors |
JPS5830147A (ja) * | 1981-08-18 | 1983-02-22 | Toshiba Corp | 半導体装置 |
US4453306A (en) * | 1983-05-27 | 1984-06-12 | At&T Bell Laboratories | Fabrication of FETs |
US4478679A (en) * | 1983-11-30 | 1984-10-23 | Storage Technology Partners | Self-aligning process for placing a barrier metal over the source and drain regions of MOS semiconductors |
JPH0612822B2 (ja) * | 1984-07-27 | 1994-02-16 | 株式会社日立製作所 | 半導体装置 |
CA1235824A (en) * | 1985-06-28 | 1988-04-26 | Vu Q. Ho | Vlsi mosfet circuits using refractory metal and/or refractory metal silicide |
JPS62169480A (ja) * | 1986-01-22 | 1987-07-25 | Hitachi Ltd | 半導体装置とその製造方法 |
JPH0773127B2 (ja) * | 1986-01-31 | 1995-08-02 | 株式会社東芝 | 半導体装置の製造方法 |
JPS62224075A (ja) * | 1986-03-26 | 1987-10-02 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JPS62224077A (ja) * | 1986-03-26 | 1987-10-02 | Hitachi Micro Comput Eng Ltd | 半導体集積回路装置 |
-
1987
- 1987-12-04 US US07/128,834 patent/US4844776A/en not_active Expired - Lifetime
-
1988
- 1988-11-25 DE DE3888937T patent/DE3888937T2/de not_active Expired - Fee Related
- 1988-11-25 ES ES88311215T patent/ES2050712T3/es not_active Expired - Lifetime
- 1988-11-25 EP EP88311215A patent/EP0319215B1/de not_active Expired - Lifetime
- 1988-11-29 CA CA000584407A patent/CA1284235C/en not_active Expired - Fee Related
- 1988-12-01 KR KR1019880015974A patent/KR960001602B1/ko not_active IP Right Cessation
- 1988-12-03 JP JP63306788A patent/JP2780986B2/ja not_active Expired - Lifetime
-
1995
- 1995-03-23 HK HK43495A patent/HK43495A/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0319215A2 (de) | 1989-06-07 |
HK43495A (en) | 1995-03-31 |
JP2780986B2 (ja) | 1998-07-30 |
KR960001602B1 (ko) | 1996-02-02 |
EP0319215A3 (en) | 1990-01-03 |
ES2050712T3 (es) | 1994-06-01 |
KR890011110A (ko) | 1989-08-12 |
DE3888937T2 (de) | 1994-07-21 |
US4844776A (en) | 1989-07-04 |
CA1284235C (en) | 1991-05-14 |
JPH022139A (ja) | 1990-01-08 |
EP0319215B1 (de) | 1994-04-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN |
|
8339 | Ceased/non-payment of the annual fee |