DE3881855D1 - Signalverzoegerungsschaltung. - Google Patents

Signalverzoegerungsschaltung.

Info

Publication number
DE3881855D1
DE3881855D1 DE8888119927T DE3881855T DE3881855D1 DE 3881855 D1 DE3881855 D1 DE 3881855D1 DE 8888119927 T DE8888119927 T DE 8888119927T DE 3881855 T DE3881855 T DE 3881855T DE 3881855 D1 DE3881855 D1 DE 3881855D1
Authority
DE
Germany
Prior art keywords
delay circuit
signal delay
signal
circuit
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888119927T
Other languages
English (en)
Other versions
DE3881855T2 (de
Inventor
Albert Manhee Chu
William Robert Griffin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE3881855D1 publication Critical patent/DE3881855D1/de
Application granted granted Critical
Publication of DE3881855T2 publication Critical patent/DE3881855T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • H03K2005/00215—Layout of the delay element using FET's where the conduction path of multiple FET's is in parallel or in series, all having the same gate control

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Pulse Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Networks Using Active Elements (AREA)
DE88119927T 1987-12-30 1988-11-30 Signalverzögerungsschaltung. Expired - Fee Related DE3881855T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/139,551 US4812688A (en) 1987-12-30 1987-12-30 Transistor delay circuits

Publications (2)

Publication Number Publication Date
DE3881855D1 true DE3881855D1 (de) 1993-07-22
DE3881855T2 DE3881855T2 (de) 1993-12-23

Family

ID=22487223

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88119927T Expired - Fee Related DE3881855T2 (de) 1987-12-30 1988-11-30 Signalverzögerungsschaltung.

Country Status (4)

Country Link
US (1) US4812688A (de)
EP (1) EP0322577B1 (de)
JP (1) JPH0654864B2 (de)
DE (1) DE3881855T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4926074A (en) * 1987-10-30 1990-05-15 North American Philips Corporation Semiconductor switch with parallel lateral double diffused MOS transistor and lateral insulated gate transistor
US4897563A (en) * 1988-08-01 1990-01-30 Itt Corporation N-way MMIC redundant switch
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
KR101903975B1 (ko) 2008-07-16 2018-10-04 텔라 이노베이션스, 인코포레이티드 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US11683029B1 (en) * 2022-01-18 2023-06-20 Nxp B.V. Charge injection protection devices and methods for input/output interfaces

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3986041A (en) * 1974-12-20 1976-10-12 International Business Machines Corporation CMOS digital circuits with resistive shunt feedback amplifier
JPS5648715A (en) * 1979-09-28 1981-05-02 Nec Corp Delay signal generating circuit
JPS5772429A (en) * 1980-10-22 1982-05-06 Toshiba Corp Semiconductor integrated circuit device
JPS57133712A (en) * 1981-02-12 1982-08-18 Fujitsu Ltd Constituting method of delay circuit in master slice ic
JPS5894232A (ja) * 1981-11-30 1983-06-04 Toshiba Corp 半導体アナログスイッチ回路
JPS58111429A (ja) * 1981-12-24 1983-07-02 Nec Corp 遅延回路
US4430587A (en) * 1982-01-13 1984-02-07 Rockwell International Corporation MOS Fixed delay circuit
JPS58184822A (ja) * 1982-03-31 1983-10-28 Fujitsu Ltd 入力回路
US4473761A (en) * 1982-04-23 1984-09-25 Motorola, Inc. Solid state transmission gate
US4476401A (en) * 1983-01-31 1984-10-09 Motorola, Inc. Write strobe generator for clock synchronized memory
US4508983A (en) * 1983-02-10 1985-04-02 Motorola, Inc. MOS Analog switch driven by complementary, minimally skewed clock signals
JPS60102017A (ja) * 1983-11-09 1985-06-06 Fujitsu Ltd 遅延回路
US4700089A (en) * 1984-08-23 1987-10-13 Fujitsu Limited Delay circuit for gate-array LSI
US4694205A (en) * 1985-06-03 1987-09-15 Advanced Micro Devices, Inc. Midpoint sense amplification scheme for a CMOS DRAM

Also Published As

Publication number Publication date
JPH01206722A (ja) 1989-08-18
EP0322577A2 (de) 1989-07-05
JPH0654864B2 (ja) 1994-07-20
DE3881855T2 (de) 1993-12-23
US4812688A (en) 1989-03-14
EP0322577A3 (en) 1989-11-02
EP0322577B1 (de) 1993-06-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee