DE3880003D1 - Halbleiteranordnung mit einer leiterschicht unter dem kontaktfleck. - Google Patents

Halbleiteranordnung mit einer leiterschicht unter dem kontaktfleck.

Info

Publication number
DE3880003D1
DE3880003D1 DE8888107501T DE3880003T DE3880003D1 DE 3880003 D1 DE3880003 D1 DE 3880003D1 DE 8888107501 T DE8888107501 T DE 8888107501T DE 3880003 T DE3880003 T DE 3880003T DE 3880003 D1 DE3880003 D1 DE 3880003D1
Authority
DE
Germany
Prior art keywords
layer
contact point
semiconductor arrangement
under
layer under
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888107501T
Other languages
English (en)
Other versions
DE3880003T2 (de
Inventor
Hiroshi Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3880003D1 publication Critical patent/DE3880003D1/de
Publication of DE3880003T2 publication Critical patent/DE3880003T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Bipolar Transistors (AREA)
  • Local Oxidation Of Silicon (AREA)
DE8888107501T 1987-05-15 1988-05-10 Halbleiteranordnung mit einer leiterschicht unter dem kontaktfleck. Expired - Fee Related DE3880003T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62116727A JPS63283040A (ja) 1987-05-15 1987-05-15 半導体装置

Publications (2)

Publication Number Publication Date
DE3880003D1 true DE3880003D1 (de) 1993-05-13
DE3880003T2 DE3880003T2 (de) 1993-09-16

Family

ID=14694302

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888107501T Expired - Fee Related DE3880003T2 (de) 1987-05-15 1988-05-10 Halbleiteranordnung mit einer leiterschicht unter dem kontaktfleck.

Country Status (4)

Country Link
US (1) US4984061A (de)
EP (1) EP0291014B1 (de)
JP (1) JPS63283040A (de)
DE (1) DE3880003T2 (de)

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JP2593965B2 (ja) * 1991-01-29 1997-03-26 三菱電機株式会社 半導体装置
ES2059215T3 (es) * 1991-02-25 1994-11-01 Ake Gustafson Procedimiento de fijacion de un bobinado a un circuito electronico.
US5281855A (en) * 1991-06-05 1994-01-25 Trovan Limited Integrated circuit device including means for facilitating connection of antenna lead wires to an integrated circuit die
US5223851A (en) * 1991-06-05 1993-06-29 Trovan Limited Apparatus for facilitating interconnection of antenna lead wires to an integrated circuit and encapsulating the assembly to form an improved miniature transponder device
US5149674A (en) * 1991-06-17 1992-09-22 Motorola, Inc. Method for making a planar multi-layer metal bonding pad
FR2687009B1 (fr) * 1992-01-31 1994-04-29 Sgs Thomson Microelectronics Composant de protection pour circuit automobile.
US5309025A (en) * 1992-07-27 1994-05-03 Sgs-Thomson Microelectronics, Inc. Semiconductor bond pad structure and method
SE500523C2 (sv) * 1992-10-09 1994-07-11 Elsa Elektroniska Systems And Halvledarkomponent med minst en första och en andra komponentelektrod innefattande ett flertal på en halvledarbricka integrerade halvledarelement, som vart och ett innefattar minst en första och en andra elementelektrod på samma sida av halvledarbrickan, varid de första elementelektroderna är förbundna med den första komponentelektroden och de andra elementelektroderna är förbundna med den andra komponentelektroden.
JP2807396B2 (ja) * 1993-05-25 1998-10-08 ローム株式会社 半導体装置
EP0637840A1 (de) * 1993-08-05 1995-02-08 AT&T Corp. Integrierte Schaltung mit aktiven Elementen unter den Anschlussflächen
EP0646959B1 (de) * 1993-09-30 2001-08-16 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Verfahren zur Metallisierung und Verbindung bei der Herstellung von Leistungshalbleiterbauelementen
US5523604A (en) * 1994-05-13 1996-06-04 International Rectifier Corporation Amorphous silicon layer for top surface of semiconductor device
EP0693782B1 (de) * 1994-07-13 2000-11-15 United Microelectronics Corporation Verfahren zur Reduzierung des Antenneneffekts während der Fabrikation
US5665996A (en) * 1994-12-30 1997-09-09 Siliconix Incorporated Vertical power mosfet having thick metal layer to reduce distributed resistance
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US5650355A (en) * 1995-03-30 1997-07-22 Texas Instruments Incorporated Process of making and process of trimming a fuse in a top level metal and in a step
US5965903A (en) * 1995-10-30 1999-10-12 Lucent Technologies Inc. Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein
JP3510039B2 (ja) * 1996-03-15 2004-03-22 株式会社デンソー 半導体装置およびその製造方法
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US5986343A (en) * 1998-05-04 1999-11-16 Lucent Technologies Inc. Bond pad design for integrated circuits
US5942800A (en) * 1998-06-22 1999-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Stress buffered bond pad and method of making
US6037668A (en) 1998-11-13 2000-03-14 Motorola, Inc. Integrated circuit having a support structure
TW445616B (en) * 1998-12-04 2001-07-11 Koninkl Philips Electronics Nv An integrated circuit device
US6936531B2 (en) * 1998-12-21 2005-08-30 Megic Corporation Process of fabricating a chip structure
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JPS63283040A (ja) 1988-11-18
JPH0546973B2 (de) 1993-07-15
EP0291014A3 (en) 1989-07-12
US4984061A (en) 1991-01-08
EP0291014A2 (de) 1988-11-17
DE3880003T2 (de) 1993-09-16
EP0291014B1 (de) 1993-04-07

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