DE3861834D1 - Verfahren zur herstellung elektrischer isolationszonen fuer eine cmos-integrierte schaltung. - Google Patents
Verfahren zur herstellung elektrischer isolationszonen fuer eine cmos-integrierte schaltung.Info
- Publication number
- DE3861834D1 DE3861834D1 DE8888901280T DE3861834T DE3861834D1 DE 3861834 D1 DE3861834 D1 DE 3861834D1 DE 8888901280 T DE8888901280 T DE 8888901280T DE 3861834 T DE3861834 T DE 3861834T DE 3861834 D1 DE3861834 D1 DE 3861834D1
- Authority
- DE
- Germany
- Prior art keywords
- cmos
- integrated circuit
- electrical insulation
- producing electrical
- insulation zones
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010292 electrical insulation Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/105—Masks, metal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8700860A FR2610140B1 (fr) | 1987-01-26 | 1987-01-26 | Circuit integre cmos et procede de fabrication de ses zones d'isolation electrique |
PCT/FR1988/000042 WO1988005603A1 (fr) | 1987-01-26 | 1988-01-26 | Procede de fabrication des zones d'isolation electrique d'un circuit integre cmos |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3861834D1 true DE3861834D1 (de) | 1991-04-04 |
Family
ID=9347260
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8888901280T Expired - Lifetime DE3861834D1 (de) | 1987-01-26 | 1988-01-26 | Verfahren zur herstellung elektrischer isolationszonen fuer eine cmos-integrierte schaltung. |
Country Status (6)
Country | Link |
---|---|
US (1) | US4889828A (de) |
EP (1) | EP0300011B1 (de) |
JP (1) | JPH01501987A (de) |
DE (1) | DE3861834D1 (de) |
FR (1) | FR2610140B1 (de) |
WO (1) | WO1988005603A1 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5164331A (en) * | 1991-10-03 | 1992-11-17 | Hewlett-Packard Company | Method of forming and etching titanium-tungsten interconnects |
US5219783A (en) * | 1992-03-20 | 1993-06-15 | Texas Instruments Incorporated | Method of making semiconductor well structure |
DE69331618T2 (de) * | 1992-10-23 | 2002-10-17 | Koninklijke Philips Electronics N.V., Eindhoven | Verfahren zur Herstellung einer Halbleiteranordnung, wobei ein seitlich abgegrenzter Halbleiterbereich selbst-justiert in einem Halbleiterkörper erzeugt wird |
US5895255A (en) * | 1994-11-30 | 1999-04-20 | Kabushiki Kaisha Toshiba | Shallow trench isolation formation with deep trench cap |
JP2001230315A (ja) | 2000-02-17 | 2001-08-24 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
DE10103524A1 (de) * | 2001-01-26 | 2002-08-22 | Infineon Technologies Ag | Verfahren und Halbleiteranordnung zur Ätzung einer Schicht eines Halbleitersubstrats mittels einer siliziumhaltigen Ätzmaske |
ITRM20040445A1 (it) * | 2004-09-17 | 2004-12-17 | St Microelectronics Srl | Processo per scavare trincee in un dispositivo ottico integrato. |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2529714A1 (fr) * | 1982-07-01 | 1984-01-06 | Commissariat Energie Atomique | Procede de realisation de l'oxyde de champ d'un circuit integre |
CA1204525A (en) * | 1982-11-29 | 1986-05-13 | Tetsu Fukano | Method for forming an isolation region for electrically isolating elements |
NL8302541A (nl) * | 1983-07-15 | 1985-02-01 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting, en halfgeleiderinrichting vervaardigd volgens de werkwijze. |
JPS6054453A (ja) * | 1983-09-05 | 1985-03-28 | Oki Electric Ind Co Ltd | 半導体集積回路装置の製造方法 |
JPS60244037A (ja) * | 1984-05-17 | 1985-12-03 | Toshiba Corp | 半導体装置及びその製造方法 |
JPS60244043A (ja) * | 1984-05-17 | 1985-12-03 | Toshiba Corp | 相補型半導体装置の製造方法 |
US4595452A (en) * | 1985-03-11 | 1986-06-17 | Oerlikon-Buhrle U.S.A. Inc. | Method and apparatus for plasma etching |
US4676869A (en) * | 1986-09-04 | 1987-06-30 | American Telephone And Telegraph Company At&T Bell Laboratories | Integrated circuits having stepped dielectric regions |
-
1987
- 1987-01-26 FR FR8700860A patent/FR2610140B1/fr not_active Expired - Lifetime
-
1988
- 1988-01-26 JP JP62506281A patent/JPH01501987A/ja active Pending
- 1988-01-26 EP EP88901280A patent/EP0300011B1/de not_active Expired - Lifetime
- 1988-01-26 US US07/249,183 patent/US4889828A/en not_active Expired - Fee Related
- 1988-01-26 DE DE8888901280T patent/DE3861834D1/de not_active Expired - Lifetime
- 1988-01-26 WO PCT/FR1988/000042 patent/WO1988005603A1/fr active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
US4889828A (en) | 1989-12-26 |
JPH01501987A (ja) | 1989-07-06 |
WO1988005603A1 (fr) | 1988-07-28 |
EP0300011A1 (de) | 1989-01-25 |
FR2610140B1 (fr) | 1990-04-20 |
EP0300011B1 (de) | 1991-02-27 |
FR2610140A1 (fr) | 1988-07-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |