DE3850943D1 - Löschbaren programmierbarer Speicher. - Google Patents

Löschbaren programmierbarer Speicher.

Info

Publication number
DE3850943D1
DE3850943D1 DE3850943T DE3850943T DE3850943D1 DE 3850943 D1 DE3850943 D1 DE 3850943D1 DE 3850943 T DE3850943 T DE 3850943T DE 3850943 T DE3850943 T DE 3850943T DE 3850943 D1 DE3850943 D1 DE 3850943D1
Authority
DE
Germany
Prior art keywords
erasable programmable
programmable memory
memory
erasable
programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3850943T
Other languages
English (en)
Other versions
DE3850943T2 (de
Inventor
James L Paterson
David D Wilmoth
Bert R Riemenschneider
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE3850943D1 publication Critical patent/DE3850943D1/de
Publication of DE3850943T2 publication Critical patent/DE3850943T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE3850943T 1987-12-09 1988-12-07 Löschbaren programmierbarer Speicher. Expired - Fee Related DE3850943T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/130,774 US4924437A (en) 1987-12-09 1987-12-09 Erasable programmable memory including buried diffusion source/drain lines and erase lines

Publications (2)

Publication Number Publication Date
DE3850943D1 true DE3850943D1 (de) 1994-09-08
DE3850943T2 DE3850943T2 (de) 1994-12-01

Family

ID=22446267

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3850943T Expired - Fee Related DE3850943T2 (de) 1987-12-09 1988-12-07 Löschbaren programmierbarer Speicher.

Country Status (5)

Country Link
US (1) US4924437A (de)
EP (1) EP0320231B1 (de)
JP (1) JP2833627B2 (de)
KR (1) KR920010850B1 (de)
DE (1) DE3850943T2 (de)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047814A (en) * 1988-02-05 1991-09-10 Emanuel Hazani E2 PROM cell including isolated control diffusion
US5303185A (en) * 1988-02-05 1994-04-12 Emanuel Hazani EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells
US5040036A (en) * 1988-02-05 1991-08-13 Emanuel Hazani Trench-isolated self-aligned split-gate EEPROM transistor and memory array
US5162247A (en) * 1988-02-05 1992-11-10 Emanuel Hazani Process for trench-isolated self-aligned split-gate EEPROM transistor and memory array
US5219774A (en) * 1988-05-17 1993-06-15 Xicor, Inc. Deposited tunneling oxide
US5047981A (en) * 1988-07-15 1991-09-10 Texas Instruments Incorporated Bit and block erasing of an electrically erasable and programmable read-only memory array
US5168335A (en) * 1988-07-15 1992-12-01 Texas Instruments Incorporated Electrically programmable, electrically erasable memory array cell with field plate
US5155055A (en) * 1988-07-15 1992-10-13 Texas Instruments Incorporated Method of making an electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel
US5089433A (en) * 1988-08-08 1992-02-18 National Semiconductor Corporation Bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture
US5262846A (en) * 1988-11-14 1993-11-16 Texas Instruments Incorporated Contact-free floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates
JP2515009B2 (ja) * 1989-01-13 1996-07-10 株式会社東芝 不揮発性半導体メモリの製造方法
US5844842A (en) * 1989-02-06 1998-12-01 Hitachi, Ltd. Nonvolatile semiconductor memory device
IT1229131B (it) * 1989-03-09 1991-07-22 Sgs Thomson Microelectronics Matrice di memoria eprom con struttura a tovaglia e procedimento per la sua fabbricazione.
US5111430A (en) * 1989-06-22 1992-05-05 Nippon Telegraph And Telephone Corporation Non-volatile memory with hot carriers transmitted to floating gate through control gate
US5051795A (en) * 1989-11-21 1991-09-24 Texas Instruments Incorporated EEPROM with trench-isolated bitlines
US5173436A (en) * 1989-11-21 1992-12-22 Texas Instruments Incorporated Method of manufacturing an EEPROM with trench-isolated bitlines
US5215934A (en) * 1989-12-21 1993-06-01 Tzeng Jyh Cherng J Process for reducing program disturbance in eeprom arrays
US5010028A (en) * 1989-12-29 1991-04-23 Texas Instruments Incorporated Method of making hot electron programmable, tunnel electron erasable contactless EEPROM
US5060195A (en) * 1989-12-29 1991-10-22 Texas Instruments Incorporated Hot electron programmable, tunnel electron erasable contactless EEPROM
US5313432A (en) * 1990-05-23 1994-05-17 Texas Instruments Incorporated Segmented, multiple-decoder memory array and method for programming a memory array
EP0459164B1 (de) * 1990-06-01 1996-09-04 Texas Instruments Incorporated Auslöschbare programmierbare Speicheranordnung
US5057446A (en) * 1990-08-06 1991-10-15 Texas Instruments Incorporated Method of making an EEPROM with improved capacitive coupling between control gate and floating gate
JPH04123471A (ja) 1990-09-14 1992-04-23 Oki Electric Ind Co Ltd 半導体記憶装置のデータ書込みおよび消去方法
US5147816A (en) * 1990-09-28 1992-09-15 Texas Instruments Incorporated Method of making nonvolatile memory array having cells with two tunelling windows
US5045491A (en) * 1990-09-28 1991-09-03 Texas Instruments Incorporated Method of making a nonvolatile memory array having cells with separate program and erase regions
US5216270A (en) * 1991-02-28 1993-06-01 Texas Instruments Incorporated Non-volatile memory cell with tunnel window structure and method
US5273926A (en) * 1991-06-27 1993-12-28 Texas Instruments Incorporated Method of making flash EEPROM or merged FAMOS cell without alignment sensitivity
US5225700A (en) * 1991-06-28 1993-07-06 Texas Instruments Incorporated Circuit and method for forming a non-volatile memory cell
US5430859A (en) * 1991-07-26 1995-07-04 Sundisk Corporation Solid state memory system including plural memory chips and a serialized bus
US5138576A (en) * 1991-11-06 1992-08-11 Altera Corporation Method and apparatus for erasing an array of electrically erasable EPROM cells
US5218568A (en) * 1991-12-17 1993-06-08 Texas Instruments Incorporated Electrically-erasable, electrically-programmable read-only memory cell, an array of such cells and methods for making and using the same
US5225362A (en) * 1992-06-01 1993-07-06 National Semiconductor Corporation Method of manufacturing a full feature high density EEPROM cell with poly tunnel spacer
FR2693308B1 (fr) * 1992-07-03 1994-08-05 Commissariat Energie Atomique Memoire eeprom a triples grilles et son procede de fabrication.
US5592415A (en) * 1992-07-06 1997-01-07 Hitachi, Ltd. Non-volatile semiconductor memory
US5357463A (en) * 1992-11-17 1994-10-18 Micron Semiconductor, Inc. Method for reverse programming of a flash EEPROM
DE4333978A1 (de) * 1993-10-05 1995-04-13 Gold Star Electronics Nichtflüchtiger Halbleiterspeicher und Verfahren zu dessen Herstellung
US5474947A (en) * 1993-12-27 1995-12-12 Motorola Inc. Nonvolatile memory process
KR0150050B1 (ko) * 1994-09-27 1998-10-01 김주용 플래쉬 이이피롬 셀 형성방법
US5716874A (en) * 1996-02-20 1998-02-10 United Microelectronics Corporation Method of fabricating EPROM memory by individually forming gate oxide and coupling insulator
KR100232200B1 (ko) * 1997-05-26 1999-12-01 김영환 비휘발성 메모리 소자 및 제조 방법
US20040021170A1 (en) * 1999-03-24 2004-02-05 Caywood John M. Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell
US6384451B1 (en) 1999-03-24 2002-05-07 John Caywood Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell
US6534816B1 (en) 1999-03-24 2003-03-18 John M. Caywood Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell
DE19946883A1 (de) * 1999-09-30 2001-04-12 Micronas Gmbh Verfahren zur Herstellung eines integrierten CMOS-Halbleiterspeichers
JP2006054283A (ja) * 2004-08-11 2006-02-23 Nec Electronics Corp 不揮発性半導体記憶装置，及びその製造方法
US7502256B2 (en) * 2004-11-30 2009-03-10 Siliconsystems, Inc. Systems and methods for reducing unauthorized data recovery from solid-state storage devices

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2743422A1 (de) * 1977-09-27 1979-03-29 Siemens Ag Wortweise loeschbarer, nicht fluechtiger speicher in floating-gate-technik
US4258466A (en) * 1978-11-02 1981-03-31 Texas Instruments Incorporated High density electrically programmable ROM
DE2916884C3 (de) * 1979-04-26 1981-12-10 Deutsche Itt Industries Gmbh, 7800 Freiburg Programmierbare Halbleiterspeicherzelle
US4561004A (en) * 1979-10-26 1985-12-24 Texas Instruments High density, electrically erasable, floating gate memory cell
JPS5743470A (en) * 1980-08-29 1982-03-11 Fujitsu Ltd Semiconductor device
DE3136517C2 (de) * 1980-09-26 1985-02-07 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Nichtflüchtige Halbleiter-Speichervorrichtung
US4531203A (en) * 1980-12-20 1985-07-23 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device and method for manufacturing the same
JPS58203697A (ja) * 1982-05-20 1983-11-28 Toshiba Corp 半導体記憶装置
JPS6045067A (ja) * 1983-08-23 1985-03-11 Toshiba Corp 不揮発性半導体メモリ装置
US4750024A (en) * 1986-02-18 1988-06-07 Texas Instruments Incorporated Offset floating gate EPROM memory cell

Also Published As

Publication number Publication date
DE3850943T2 (de) 1994-12-01
KR890011088A (ko) 1989-08-12
JP2833627B2 (ja) 1998-12-09
EP0320231B1 (de) 1994-08-03
US4924437A (en) 1990-05-08
EP0320231A3 (de) 1992-03-18
JPH022178A (ja) 1990-01-08
KR920010850B1 (ko) 1992-12-19
EP0320231A2 (de) 1989-06-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee