DE3751892D1 - Halbleiteranordnung mit zwei Verbindungshalbleitern und Verfahren zu ihrer Herstellung - Google Patents

Halbleiteranordnung mit zwei Verbindungshalbleitern und Verfahren zu ihrer Herstellung

Info

Publication number
DE3751892D1
DE3751892D1 DE3751892T DE3751892T DE3751892D1 DE 3751892 D1 DE3751892 D1 DE 3751892D1 DE 3751892 T DE3751892 T DE 3751892T DE 3751892 T DE3751892 T DE 3751892T DE 3751892 D1 DE3751892 D1 DE 3751892D1
Authority
DE
Germany
Prior art keywords
layer
production
compound semiconductors
semiconductor
semiconductor arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3751892T
Other languages
English (en)
Other versions
DE3751892T2 (de
Inventor
Takao Kuroda
Takao Miyazaki
Akiyoshi Watanabe
Hiroyoshi Matsumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE3751892D1 publication Critical patent/DE3751892D1/de
Application granted granted Critical
Publication of DE3751892T2 publication Critical patent/DE3751892T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02392—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02461—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02549—Antimonides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H01L29/365—Planar doping, e.g. atomic-plane doping, delta-doping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/432—Heterojunction gate for field effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)
DE3751892T 1986-06-02 1987-06-01 Halbleiteranordnung mit zwei Verbindungshalbleitern und Verfahren zu ihrer Herstellung Expired - Fee Related DE3751892T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61125736A JPH0783028B2 (ja) 1986-06-02 1986-06-02 半導体装置及び製造方法

Publications (2)

Publication Number Publication Date
DE3751892D1 true DE3751892D1 (de) 1996-10-10
DE3751892T2 DE3751892T2 (de) 1997-04-03

Family

ID=14917516

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3751892T Expired - Fee Related DE3751892T2 (de) 1986-06-02 1987-06-01 Halbleiteranordnung mit zwei Verbindungshalbleitern und Verfahren zu ihrer Herstellung

Country Status (4)

Country Link
US (1) US4814838A (de)
EP (1) EP0249371B1 (de)
JP (1) JPH0783028B2 (de)
DE (1) DE3751892T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2620268A1 (fr) * 1987-09-03 1989-03-10 Centre Nat Rech Scient Procede de dopage d'une couche semi-conductrice et transistor obtenu par ce procede
JP2770340B2 (ja) * 1988-09-06 1998-07-02 ソニー株式会社 半導体装置、絶縁ゲート型電界効果トランジスタ及びショットキーゲート型電界効果トランジスタ
US6083220A (en) 1990-03-13 2000-07-04 The Regents Of The University Of California Endovascular electrolytically detachable wire and tip for the formation of thrombus in arteries, veins, aneurysms, vascular malformations and arteriovenous fistulas
USRE42625E1 (en) 1990-03-13 2011-08-16 The Regents Of The University Of California Endovascular electrolytically detachable wire and tip for the formation of thrombus in arteries, veins, aneurysms, vascular malformations and arteriovenous fistulas
USRE42756E1 (en) 1990-03-13 2011-09-27 The Regents Of The University Of California Endovascular electrolytically detachable wire and tip for the formation of thrombus in arteries, veins, aneurysms, vascular malformations and arteriovenous fistulas
JP2817995B2 (ja) * 1990-03-15 1998-10-30 富士通株式会社 ▲ｉｉｉ▼―▲ｖ▼族化合物半導体ヘテロ構造基板および▲ｉｉｉ▼―▲ｖ▼族化合物ヘテロ構造半導体装置
JP2549206B2 (ja) * 1990-12-27 1996-10-30 住友電気工業株式会社 電界効果トランジスタ
JPH0521468A (ja) * 1991-07-17 1993-01-29 Sumitomo Electric Ind Ltd 電界効果トランジスタの製造方法
JP3224437B2 (ja) * 1992-11-30 2001-10-29 富士通株式会社 Ｉｉｉ−ｖ族化合物半導体装置
JP3376078B2 (ja) * 1994-03-18 2003-02-10 富士通株式会社 高電子移動度トランジスタ
US6043143A (en) * 1998-05-04 2000-03-28 Motorola, Inc. Ohmic contact and method of manufacture
DE10025264A1 (de) * 2000-05-22 2001-11-29 Max Planck Gesellschaft Feldeffekt-Transistor auf der Basis von eingebetteten Clusterstrukturen und Verfahren zu seiner Herstellung
US9692209B2 (en) 2011-06-10 2017-06-27 Massachusetts Institute Of Technology High-concentration active doping in semiconductors and semiconductor devices produced by such doping

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3953876A (en) * 1973-06-07 1976-04-27 Dow Corning Corporation Silicon solar cell array
US4062038A (en) * 1976-01-28 1977-12-06 International Business Machines Corporation Radiation responsive device
US4632712A (en) * 1983-09-12 1986-12-30 Massachusetts Institute Of Technology Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth

Also Published As

Publication number Publication date
EP0249371A3 (en) 1988-10-05
DE3751892T2 (de) 1997-04-03
JPS62283675A (ja) 1987-12-09
EP0249371B1 (de) 1996-09-04
EP0249371A2 (de) 1987-12-16
JPH0783028B2 (ja) 1995-09-06
US4814838A (en) 1989-03-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee