JPS5591860A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS5591860A JPS5591860A JP16581078A JP16581078A JPS5591860A JP S5591860 A JPS5591860 A JP S5591860A JP 16581078 A JP16581078 A JP 16581078A JP 16581078 A JP16581078 A JP 16581078A JP S5591860 A JPS5591860 A JP S5591860A
- Authority
- JP
- Japan
- Prior art keywords
- conduction type
- layer
- polycrystalline layer
- semiconductor substrate
- single crystals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
Landscapes
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To increase the degree of integration and simplify the processing work, by reducing the overlap capacitance of a gate, a source and a drain and using the self- alignment method. CONSTITUTION:Reverse conduction type buried-in layer 22 and insulating layer 23 are formed on one conduction type semiconductor substrate 21, and further, single crystals 24S, 25S and polycrystalline layer 24P' are grown on a semiconductor substrate 21. Opposite conduction type impurity regions 27' and 28' are formed on single crystal layers 24S, 25S and polycrystalline layer 24P'. Source electrode 27 is formed over single crystals 24S and 25S and polycrystalline layer 24P', and further, drain electrode 28 and gate oxide film 30 are formed.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53165810A JPS6053473B2 (en) | 1978-12-30 | 1978-12-30 | semiconductor storage device |
DE7979301928T DE2967388D1 (en) | 1978-09-20 | 1979-09-18 | Semiconductor memory device and process for fabricating the device |
CA000335866A CA1144646A (en) | 1978-09-20 | 1979-09-18 | Dynamic ram having buried capacitor and planar gate |
EP79301928A EP0009910B1 (en) | 1978-09-20 | 1979-09-18 | Semiconductor memory device and process for fabricating the device |
US06/076,993 US4329704A (en) | 1978-09-20 | 1979-09-19 | MOS Random access memory with buried storage capacitor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53165810A JPS6053473B2 (en) | 1978-12-30 | 1978-12-30 | semiconductor storage device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5591860A true JPS5591860A (en) | 1980-07-11 |
JPS6053473B2 JPS6053473B2 (en) | 1985-11-26 |
Family
ID=15819417
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53165810A Expired JPS6053473B2 (en) | 1978-09-20 | 1978-12-30 | semiconductor storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6053473B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5003361A (en) * | 1987-08-31 | 1991-03-26 | At&T Bell Laboratories | Active dynamic memory cell |
-
1978
- 1978-12-30 JP JP53165810A patent/JPS6053473B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5003361A (en) * | 1987-08-31 | 1991-03-26 | At&T Bell Laboratories | Active dynamic memory cell |
Also Published As
Publication number | Publication date |
---|---|
JPS6053473B2 (en) | 1985-11-26 |
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