DE3672031D1 - Halbleiteranordnung mit einer hohen durchbruchspannung. - Google Patents

Halbleiteranordnung mit einer hohen durchbruchspannung.

Info

Publication number
DE3672031D1
DE3672031D1 DE8686113342T DE3672031T DE3672031D1 DE 3672031 D1 DE3672031 D1 DE 3672031D1 DE 8686113342 T DE8686113342 T DE 8686113342T DE 3672031 T DE3672031 T DE 3672031T DE 3672031 D1 DE3672031 D1 DE 3672031D1
Authority
DE
Germany
Prior art keywords
semiconductor arrangement
breakthrough voltage
high breakthrough
voltage
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686113342T
Other languages
English (en)
Inventor
Yoshiro Pat Division Baba
Kazuo Pat Division Tsuru
Tatsuo Pat Division Akiyama
Yutaka Pat Division Koshino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3672031D1 publication Critical patent/DE3672031D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Bipolar Transistors (AREA)
DE8686113342T 1985-09-30 1986-09-29 Halbleiteranordnung mit einer hohen durchbruchspannung. Expired - Lifetime DE3672031D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60216586A JPS6276673A (ja) 1985-09-30 1985-09-30 高耐圧半導体装置

Publications (1)

Publication Number Publication Date
DE3672031D1 true DE3672031D1 (de) 1990-07-19

Family

ID=16690738

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686113342T Expired - Lifetime DE3672031D1 (de) 1985-09-30 1986-09-29 Halbleiteranordnung mit einer hohen durchbruchspannung.

Country Status (4)

Country Link
US (1) US5031021A (de)
EP (1) EP0217326B1 (de)
JP (1) JPS6276673A (de)
DE (1) DE3672031D1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USH665H (en) * 1987-10-19 1989-08-01 Bell Telephone Laboratories, Incorporated Resistive field shields for high voltage devices
FR2650122B1 (fr) * 1989-07-21 1991-11-08 Motorola Semiconducteurs Dispositif semi-conducteur a haute tension et son procede de fabrication
DE58909785D1 (de) * 1989-11-28 1997-04-10 Siemens Ag Halbleiterscheibe mit dotiertem Ritzrahmen
DE69233742D1 (de) * 1991-01-31 2008-09-18 Toshiba Kk Halbleiterbauelement mit hoher Durchbruchspannung
US5650359A (en) * 1991-05-06 1997-07-22 Texas Instruments Incorporated Composite dielectric passivation of high density circuits
DE4231829A1 (de) * 1992-09-23 1994-03-24 Telefunken Microelectron Planares Halbleiterbauteil
US5543335A (en) * 1993-05-05 1996-08-06 Ixys Corporation Advanced power device process for low drop
US6107674A (en) * 1993-05-05 2000-08-22 Ixys Corporation Isolated multi-chip devices
US6147393A (en) * 1993-05-05 2000-11-14 Ixys Corporation Isolated multi-chip devices
US5637908A (en) * 1994-09-28 1997-06-10 Harris Corporation Structure and technique for tailoring effective resistivity of a SIPOS layer by patterning and control of dopant introduction
JP3958404B2 (ja) * 1997-06-06 2007-08-15 三菱電機株式会社 横型高耐圧素子を有する半導体装置
JP5195186B2 (ja) * 2008-09-05 2013-05-08 三菱電機株式会社 半導体装置の製造方法
CN103035732B (zh) * 2012-12-17 2015-10-28 华南理工大学 一种vdmos晶体管及其制备方法
JP6079456B2 (ja) * 2013-06-07 2017-02-15 三菱電機株式会社 半導体装置の検査方法
WO2015097581A1 (en) * 2013-12-23 2015-07-02 Hkg Technologies Limited Power semiconductor devices having semi-insulating field plate
EP2908344A1 (de) * 2014-02-12 2015-08-19 Nxp B.V. Halbleitervorrichtung mit Heteroübergang

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS523277B2 (de) * 1973-05-19 1977-01-27
JPS532552B2 (de) * 1974-03-30 1978-01-28
JPS6022497B2 (ja) * 1974-10-26 1985-06-03 ソニー株式会社 半導体装置
JPS6041458B2 (ja) * 1975-04-21 1985-09-17 ソニー株式会社 半導体装置の製造方法
DE2628902C3 (de) * 1976-06-28 1979-01-18 Akzo Gmbh, 5600 Wuppertal Flammwidrige und selbstverlöschende Polymermassen
GB2047461A (en) * 1979-04-19 1980-11-26 Philips Electronic Associated Semiconductor device
US4344985A (en) * 1981-03-27 1982-08-17 Rca Corporation Method of passivating a semiconductor device with a multi-layer passivant system by thermally growing a layer of oxide on an oxygen doped polycrystalline silicon layer
US4420765A (en) * 1981-05-29 1983-12-13 Rca Corporation Multi-layer passivant system
JPS59105362A (ja) * 1982-12-08 1984-06-18 Matsushita Electronics Corp 半導体装置

Also Published As

Publication number Publication date
JPH0350414B2 (de) 1991-08-01
EP0217326A2 (de) 1987-04-08
EP0217326A3 (en) 1987-12-02
EP0217326B1 (de) 1990-06-13
JPS6276673A (ja) 1987-04-08
US5031021A (en) 1991-07-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee