DE3485063D1 - Logisches gate und testverfahren. - Google Patents

Logisches gate und testverfahren.

Info

Publication number
DE3485063D1
DE3485063D1 DE8585900324T DE3485063T DE3485063D1 DE 3485063 D1 DE3485063 D1 DE 3485063D1 DE 8585900324 T DE8585900324 T DE 8585900324T DE 3485063 T DE3485063 T DE 3485063T DE 3485063 D1 DE3485063 D1 DE 3485063D1
Authority
DE
Germany
Prior art keywords
variable input
gate
input gates
gates
testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585900324T
Other languages
English (en)
Inventor
W Moore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aerojet Rocketdyne Inc
Original Assignee
Aerojet General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aerojet General Corp filed Critical Aerojet General Corp
Application granted granted Critical
Publication of DE3485063D1 publication Critical patent/DE3485063D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE8585900324T 1984-12-11 1984-12-11 Logisches gate und testverfahren. Expired - Fee Related DE3485063D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1984/001926 WO1986003592A1 (en) 1984-12-11 1984-12-11 Amenable logic gate and method of testing

Publications (1)

Publication Number Publication Date
DE3485063D1 true DE3485063D1 (de) 1991-10-17

Family

ID=22182338

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585900324T Expired - Fee Related DE3485063D1 (de) 1984-12-11 1984-12-11 Logisches gate und testverfahren.

Country Status (4)

Country Link
EP (1) EP0204697B1 (de)
JP (1) JPS62501519A (de)
DE (1) DE3485063D1 (de)
WO (1) WO1986003592A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3726570A1 (de) * 1987-08-10 1989-02-23 Siemens Ag Verfahren und schaltungsanordnung fuer halbleiterbausteine mit in hochintegrierter schaltkreistechnik zusammengefassten logischen verknuepfungsschaltungen

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3783254A (en) * 1972-10-16 1974-01-01 Ibm Level sensitive logic system
US3958110A (en) * 1974-12-18 1976-05-18 Ibm Corporation Logic array with testing circuitry
US4225957A (en) * 1978-10-16 1980-09-30 International Business Machines Corporation Testing macros embedded in LSI chips
DE3015992A1 (de) * 1980-04-25 1981-11-05 Ibm Deutschland Gmbh, 7000 Stuttgart Programmierbare logische anordnung
US4435805A (en) * 1981-06-04 1984-03-06 International Business Machines Corporation Testing of logic arrays
US4542508A (en) * 1983-11-21 1985-09-17 Aerojet-General Corporation Amenable logic gate and method of testing

Also Published As

Publication number Publication date
JPS62501519A (ja) 1987-06-18
EP0204697A1 (de) 1986-12-17
WO1986003592A1 (en) 1986-06-19
EP0204697A4 (de) 1988-04-26
EP0204697B1 (de) 1991-09-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee