DE3484134D1 - Lineares rueckfuehrungsschieberegister. - Google Patents

Lineares rueckfuehrungsschieberegister.

Info

Publication number
DE3484134D1
DE3484134D1 DE8484114661T DE3484134T DE3484134D1 DE 3484134 D1 DE3484134 D1 DE 3484134D1 DE 8484114661 T DE8484114661 T DE 8484114661T DE 3484134 T DE3484134 T DE 3484134T DE 3484134 D1 DE3484134 D1 DE 3484134D1
Authority
DE
Germany
Prior art keywords
vlsi
shift register
linear feedback
test
vlsi circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484114661T
Other languages
English (en)
Inventor
Mon Yen Tsai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3484134D1 publication Critical patent/DE3484134D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/31813—Test pattern generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58—Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/581—Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58—Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/583—Serial finite field implementation, i.e. serial implementation of finite field arithmetic, generating one new bit or trit per step, e.g. using an LFSR or several independent LFSRs; also includes PRNGs with parallel operation between LFSR and outputs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE8484114661T 1983-12-30 1984-12-04 Lineares rueckfuehrungsschieberegister. Expired - Fee Related DE3484134D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/567,217 US4680539A (en) 1983-12-30 1983-12-30 General linear shift register

Publications (1)

Publication Number Publication Date
DE3484134D1 true DE3484134D1 (de) 1991-03-28

Family

ID=24266230

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484114661T Expired - Fee Related DE3484134D1 (de) 1983-12-30 1984-12-04 Lineares rueckfuehrungsschieberegister.

Country Status (4)

Country Link
US (1) US4680539A (de)
EP (1) EP0148403B1 (de)
JP (1) JPS60147660A (de)
DE (1) DE3484134D1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0196171B1 (de) * 1985-03-23 1991-11-06 International Computers Limited Integrierte digitale Schaltungen
GB8518860D0 (en) * 1985-07-25 1985-08-29 Int Computers Ltd Digital integrated circuits
JPS63182585A (ja) * 1987-01-26 1988-07-27 Toshiba Corp テスト容易化機能を備えた論理回路
GB2210171B (en) * 1987-09-28 1991-06-26 Plessey Co Plc Test circuit
GB8728444D0 (en) * 1987-12-04 1988-01-13 Plessey Co Plc Analogue circuit element & chain for testing analogue circuit
US5184067A (en) * 1988-07-12 1993-02-02 Kabushiki Kaisha Toshiba Signature compression circuit
JPH0776782B2 (ja) * 1988-07-12 1995-08-16 株式会社東芝 シグネチャ圧縮回路
EP0358376B1 (de) * 1988-09-07 1995-02-22 Texas Instruments Incorporated Integrierte Prüfschaltung
US6304987B1 (en) * 1995-06-07 2001-10-16 Texas Instruments Incorporated Integrated test circuit
US5483518A (en) 1992-06-17 1996-01-09 Texas Instruments Incorporated Addressable shadow port and protocol for serial bus networks
JP3005250B2 (ja) 1989-06-30 2000-01-31 テキサス インスツルメンツ インコーポレイテツド バスモニター集積回路
US6675333B1 (en) 1990-03-30 2004-01-06 Texas Instruments Incorporated Integrated circuit with serial I/O controller
JP2841882B2 (ja) * 1991-02-04 1998-12-24 日本電気株式会社 疑似乱数パタン発生器
US5642362A (en) * 1994-07-20 1997-06-24 International Business Machines Corporation Scan-based delay tests having enhanced test vector pattern generation
US5506520A (en) * 1995-01-11 1996-04-09 International Business Machines Corporation Energy conserving clock pulse generating circuits
US5623545A (en) * 1995-08-31 1997-04-22 National Semiconductor Corporation Automatic data generation for self-test of cryptographic hash algorithms in personal security devices
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US6260165B1 (en) 1996-10-18 2001-07-10 Texas Instruments Incorporated Accelerating scan test by re-using response data as stimulus data
US6097889A (en) * 1997-06-23 2000-08-01 Motorola, Inc. Signal processing apparatus with stages in a signal path operating as LFSR of alternable type and method for processing signals
US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US7058862B2 (en) 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US8176394B2 (en) * 2008-04-11 2012-05-08 Mediatek Inc. Linear feedback shift register structure and method
US10708043B2 (en) 2013-03-07 2020-07-07 David Mayer Hutchinson One pad communications

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1252036A (de) * 1968-08-20 1971-11-03
US3815025A (en) * 1971-10-18 1974-06-04 Ibm Large-scale integrated circuit testing structure
US3790885A (en) * 1972-03-27 1974-02-05 Ibm Serial test patterns for mosfet testing
US4233524A (en) * 1978-07-24 1980-11-11 National Semiconductor Corporation Multi-function logic circuit
US4225957A (en) * 1978-10-16 1980-09-30 International Business Machines Corporation Testing macros embedded in LSI chips
US4244048A (en) * 1978-12-29 1981-01-06 International Business Machines Corporation Chip and wafer configuration and testing method for large-scale-integrated circuits
DE2902375C2 (de) * 1979-01-23 1984-05-17 Siemens AG, 1000 Berlin und 8000 München Logikbaustein für integrierte Digitalschaltungen
US4328435A (en) * 1979-12-28 1982-05-04 International Business Machines Corporation Dynamically switchable logic block for JK/EOR functions
DE3029883A1 (de) * 1980-08-07 1982-03-11 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke
US4513418A (en) * 1982-11-08 1985-04-23 International Business Machines Corporation Simultaneous self-testing system

Also Published As

Publication number Publication date
EP0148403A2 (de) 1985-07-17
JPS60147660A (ja) 1985-08-03
US4680539A (en) 1987-07-14
EP0148403A3 (en) 1988-06-22
EP0148403B1 (de) 1991-02-20
JPH0481147B2 (de) 1992-12-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee