DE3464442D1 - Process for producing of a thin film transistor with self-aligned gate - Google Patents
Process for producing of a thin film transistor with self-aligned gateInfo
- Publication number
- DE3464442D1 DE3464442D1 DE8484402027T DE3464442T DE3464442D1 DE 3464442 D1 DE3464442 D1 DE 3464442D1 DE 8484402027 T DE8484402027 T DE 8484402027T DE 3464442 T DE3464442 T DE 3464442T DE 3464442 D1 DE3464442 D1 DE 3464442D1
- Authority
- DE
- Germany
- Prior art keywords
- self
- producing
- thin film
- film transistor
- aligned gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010409 thin film Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/091—Laser beam processing of fets
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/949—Energy beam treating radiation resist on semiconductor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8316203A FR2553579B1 (fr) | 1983-10-12 | 1983-10-12 | Procede de fabrication d'un transistor en film mince a grille auto-alignee |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3464442D1 true DE3464442D1 (en) | 1987-07-30 |
Family
ID=9293041
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8484402027T Expired DE3464442D1 (en) | 1983-10-12 | 1984-10-09 | Process for producing of a thin film transistor with self-aligned gate |
Country Status (5)
Country | Link |
---|---|
US (1) | US4587720A (de) |
EP (1) | EP0139585B1 (de) |
JP (1) | JPS6097675A (de) |
DE (1) | DE3464442D1 (de) |
FR (1) | FR2553579B1 (de) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6784033B1 (en) * | 1984-02-15 | 2004-08-31 | Semiconductor Energy Laboratory Co., Ltd. | Method for the manufacture of an insulated gate field effect semiconductor device |
JPH0752776B2 (ja) * | 1985-01-24 | 1995-06-05 | シャープ株式会社 | 薄膜トランジスタおよびその製造法 |
FR2590409B1 (fr) * | 1985-11-15 | 1987-12-11 | Commissariat Energie Atomique | Procede de fabrication d'un transistor en couches minces a grille auto-alignee par rapport au drain et a la source de celui-ci et transistor obtenu par le procede |
FR2590406B1 (fr) * | 1985-11-15 | 1988-10-28 | Commissariat Energie Atomique | Procede de fabrication d'un transistor en couches minces a grille auto-alignee par rapport au drain et a la source de celui-ci |
JPS62140467A (ja) * | 1985-12-13 | 1987-06-24 | Sharp Corp | 薄膜トランジスタの製造方法 |
FR2593327B1 (fr) * | 1986-01-23 | 1988-10-28 | Commissariat Energie Atomique | Procede de fabrication d'un transistor en couches minces utilisant deux ou trois niveaux de masquage |
JPS62291067A (ja) * | 1986-06-10 | 1987-12-17 | Nec Corp | 薄膜トランジスタの製造方法 |
EP0251563A3 (de) * | 1986-06-17 | 1991-01-09 | Tokyo Electric Co. Ltd. | Photoelektrischer Wandler |
US4678542A (en) * | 1986-07-25 | 1987-07-07 | Energy Conversion Devices, Inc. | Self-alignment process for thin film diode array fabrication |
US4862234A (en) | 1986-11-29 | 1989-08-29 | Sharp Kabushiki Kaisha | Thin-film transistor |
US4918504A (en) * | 1987-07-31 | 1990-04-17 | Nippon Telegraph And Telephone Corporation | Active matrix cell |
JPH01173650A (ja) * | 1987-12-26 | 1989-07-10 | Seikosha Co Ltd | 非晶質シリコン薄膜トランジスタの製造方法 |
US5173753A (en) * | 1989-08-10 | 1992-12-22 | Industrial Technology Research Institute | Inverted coplanar amorphous silicon thin film transistor which provides small contact capacitance and resistance |
US5010027A (en) * | 1990-03-21 | 1991-04-23 | General Electric Company | Method for fabricating a self-aligned thin-film transistor utilizing planarization and back-side photoresist exposure |
KR940008227B1 (ko) * | 1991-08-27 | 1994-09-08 | 주식회사 금성사 | 박막 트랜지스터 제조방법 |
US5597747A (en) * | 1995-12-15 | 1997-01-28 | Industrial Technology Research Institute | Method of making inverted thin film transistor using backsick exposure and negative photoresist |
GB9606083D0 (en) * | 1996-03-22 | 1996-05-22 | Philips Electronics Nv | Electronic device manufacture |
JP2005235860A (ja) * | 2004-02-17 | 2005-09-02 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
US7527994B2 (en) * | 2004-09-01 | 2009-05-05 | Honeywell International Inc. | Amorphous silicon thin-film transistors and methods of making the same |
KR101769612B1 (ko) * | 2010-12-10 | 2017-08-21 | 삼성디스플레이 주식회사 | 기판 평탄화 방법 |
US10679847B2 (en) | 2018-03-01 | 2020-06-09 | International Business Machines Corporation | Self-aligned spacerless thin film transistor |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56165371A (en) * | 1980-05-26 | 1981-12-18 | Shunpei Yamazaki | Semiconductor device |
US4380864A (en) * | 1981-07-27 | 1983-04-26 | The United States Of America As Represented By The Secretary Of The Air Force | Method for providing in-situ non-destructive monitoring of semiconductors during laser annealing process |
US4404731A (en) * | 1981-10-01 | 1983-09-20 | Xerox Corporation | Method of forming a thin film transistor |
JPS58170067A (ja) * | 1982-03-31 | 1983-10-06 | Fujitsu Ltd | 薄膜トランジスタの製造方法 |
US4456490A (en) * | 1983-03-09 | 1984-06-26 | Westinghouse Electric Corp. | Laser annealing of MIS devices by back surface laser treatment |
-
1983
- 1983-10-12 FR FR8316203A patent/FR2553579B1/fr not_active Expired
-
1984
- 1984-10-09 EP EP84402027A patent/EP0139585B1/de not_active Expired
- 1984-10-09 DE DE8484402027T patent/DE3464442D1/de not_active Expired
- 1984-10-10 US US06/659,316 patent/US4587720A/en not_active Expired - Fee Related
- 1984-10-12 JP JP59212797A patent/JPS6097675A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
FR2553579A1 (fr) | 1985-04-19 |
JPS6097675A (ja) | 1985-05-31 |
EP0139585B1 (de) | 1987-06-24 |
FR2553579B1 (fr) | 1985-12-27 |
JPH0523057B2 (de) | 1993-03-31 |
EP0139585A1 (de) | 1985-05-02 |
US4587720A (en) | 1986-05-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |