DE3381632D1 - Speicherschaltung mit mitteln zum nachweis der speisespannung. - Google Patents
Speicherschaltung mit mitteln zum nachweis der speisespannung.Info
- Publication number
- DE3381632D1 DE3381632D1 DE8383108582T DE3381632T DE3381632D1 DE 3381632 D1 DE3381632 D1 DE 3381632D1 DE 8383108582 T DE8383108582 T DE 8383108582T DE 3381632 T DE3381632 T DE 3381632T DE 3381632 D1 DE3381632 D1 DE 3381632D1
- Authority
- DE
- Germany
- Prior art keywords
- detecting
- supply voltage
- memory circuit
- memory
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
- G01R19/16557—Logic probes, i.e. circuits indicating logic state (high, low, O)
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
- G05F1/571—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overvoltage detector
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Power Engineering (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57150844A JPS5940393A (ja) | 1982-08-31 | 1982-08-31 | メモリ回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3381632D1 true DE3381632D1 (de) | 1990-07-12 |
Family
ID=15505609
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8383108582T Expired - Lifetime DE3381632D1 (de) | 1982-08-31 | 1983-08-31 | Speicherschaltung mit mitteln zum nachweis der speisespannung. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4631707A (de) |
EP (1) | EP0102618B1 (de) |
JP (1) | JPS5940393A (de) |
DE (1) | DE3381632D1 (de) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS613390A (ja) * | 1984-06-15 | 1986-01-09 | Hitachi Ltd | 記憶装置 |
GB8611794D0 (en) * | 1986-05-14 | 1986-06-25 | Gen Electric Co Plc | Microprocessor back-up system |
US5001670A (en) * | 1987-02-06 | 1991-03-19 | Tektronix, Inc. | Nonvolatile memory protection |
FR2613491B1 (fr) * | 1987-04-03 | 1989-07-21 | Thomson Csf | Dispositif de detection du niveau haut d'une tension en technologie mos |
JPS6444618A (en) * | 1987-08-13 | 1989-02-17 | Toshiba Corp | Reset signal generating circuit |
US4800532A (en) * | 1987-11-25 | 1989-01-24 | Siemens Aktiengesellschaft | Circuit arrangement with a processor and at least two read-write memories |
US5046052A (en) * | 1988-06-01 | 1991-09-03 | Sony Corporation | Internal low voltage transformation circuit of static random access memory |
JP2614514B2 (ja) * | 1989-05-19 | 1997-05-28 | 三菱電機株式会社 | ダイナミック・ランダム・アクセス・メモリ |
DE69120483T2 (de) * | 1990-08-17 | 1996-11-14 | Sgs Thomson Microelectronics | Halbleiter-Speicher mit unterdrücktem Testmodus-Eingang während des Strom-Einschaltens |
US5124951A (en) * | 1990-09-26 | 1992-06-23 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with sequenced latched row line repeaters |
US5121358A (en) * | 1990-09-26 | 1992-06-09 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with power-on reset controlled latched row line repeaters |
US5424986A (en) * | 1991-12-19 | 1995-06-13 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with power-on reset control of disabled rows |
US5420798A (en) * | 1993-09-30 | 1995-05-30 | Macronix International Co., Ltd. | Supply voltage detection circuit |
WO1997000518A1 (fr) * | 1995-06-14 | 1997-01-03 | Hitachi, Ltd. | Memoire a semiconducteurs, unite de memoire et carte de memoire |
US5884084A (en) * | 1996-10-31 | 1999-03-16 | Intel Corporation | Circuit and method for using early reset to prevent CMOS corruption with advanced power supplies |
US5940345A (en) * | 1997-12-12 | 1999-08-17 | Cypress Semiconductor Corp. | Combinational logic feedback circuit to ensure correct power-on-reset of a four-bit synchronous shift register |
JP4549711B2 (ja) * | 2004-03-29 | 2010-09-22 | ルネサスエレクトロニクス株式会社 | 半導体回路装置 |
KR101707266B1 (ko) * | 2013-08-29 | 2017-02-15 | 엘에스산전 주식회사 | Plc에서의 os의 업데이트 장치 및 방법 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5713072B2 (de) * | 1975-02-10 | 1982-03-15 | ||
JPS53120548A (en) * | 1977-03-30 | 1978-10-21 | Toshiba Corp | Battery life display system |
US4104734A (en) * | 1977-06-30 | 1978-08-01 | Fairchild Camera And Instrument Corporation | Low voltage data retention bias circuitry for volatile memories |
CH657712A5 (de) * | 1978-03-08 | 1986-09-15 | Hitachi Ltd | Referenzspannungserzeuger. |
US4288865A (en) * | 1980-02-06 | 1981-09-08 | Mostek Corporation | Low-power battery backup circuit for semiconductor memory |
JPS56122132U (de) * | 1980-02-18 | 1981-09-17 |
-
1982
- 1982-08-31 JP JP57150844A patent/JPS5940393A/ja active Granted
-
1983
- 1983-08-31 DE DE8383108582T patent/DE3381632D1/de not_active Expired - Lifetime
- 1983-08-31 EP EP83108582A patent/EP0102618B1/de not_active Expired - Lifetime
- 1983-08-31 US US06/528,006 patent/US4631707A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS5940393A (ja) | 1984-03-06 |
JPH0241838B2 (de) | 1990-09-19 |
EP0102618B1 (de) | 1990-06-06 |
US4631707A (en) | 1986-12-23 |
EP0102618A2 (de) | 1984-03-14 |
EP0102618A3 (en) | 1987-07-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |