DE3377958D1 - Method of manufacturing a semiconductor device including burying an insulating film - Google Patents
Method of manufacturing a semiconductor device including burying an insulating filmInfo
- Publication number
- DE3377958D1 DE3377958D1 DE8383303080T DE3377958T DE3377958D1 DE 3377958 D1 DE3377958 D1 DE 3377958D1 DE 8383303080 T DE8383303080 T DE 8383303080T DE 3377958 T DE3377958 T DE 3377958T DE 3377958 D1 DE3377958 D1 DE 3377958D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- semiconductor device
- insulating film
- device including
- including burying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
- Local Oxidation Of Silicon (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57092917A JPS58210634A (ja) | 1982-05-31 | 1982-05-31 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3377958D1 true DE3377958D1 (en) | 1988-10-13 |
Family
ID=14067831
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8383303080T Expired DE3377958D1 (en) | 1982-05-31 | 1983-05-27 | Method of manufacturing a semiconductor device including burying an insulating film |
Country Status (4)
Country | Link |
---|---|
US (1) | US4505025A (de) |
EP (1) | EP0098687B1 (de) |
JP (1) | JPS58210634A (de) |
DE (1) | DE3377958D1 (de) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6054450A (ja) * | 1983-09-05 | 1985-03-28 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
US4615746A (en) * | 1983-09-29 | 1986-10-07 | Kenji Kawakita | Method of forming isolated island regions in a semiconductor substrate by selective etching and oxidation and devices formed therefrom |
US4662986A (en) * | 1985-06-27 | 1987-05-05 | Signetics Corporation | Planarization method and technique for isolating semiconductor islands |
US4665007A (en) * | 1985-08-19 | 1987-05-12 | International Business Machines Corporation | Planarization process for organic filling of deep trenches |
JPS62169442A (ja) * | 1986-01-22 | 1987-07-25 | Nec Corp | 素子分離領域の形成方法 |
JPS6377122A (ja) * | 1986-09-19 | 1988-04-07 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH01125935A (ja) * | 1987-11-11 | 1989-05-18 | Seiko Instr & Electron Ltd | 半導体装置の製造方法 |
JPH0824141B2 (ja) * | 1988-04-15 | 1996-03-06 | 松下電器産業株式会社 | 半導体装置の製造方法 |
ATE137358T1 (de) * | 1988-11-10 | 1996-05-15 | Applied Materials Inc | Planarisationsmethode für ic-struktur |
US5112776A (en) * | 1988-11-10 | 1992-05-12 | Applied Materials, Inc. | Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing |
US4962063A (en) * | 1988-11-10 | 1990-10-09 | Applied Materials, Inc. | Multistep planarized chemical vapor deposition process with the use of low melting inorganic material for flowing while depositing |
EP0423907B1 (de) * | 1988-11-10 | 1996-04-24 | Applied Materials, Inc. | Planarisationsmethode für IC-Struktur |
US5244841A (en) * | 1988-11-10 | 1993-09-14 | Applied Materials, Inc. | Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing |
US5256592A (en) * | 1989-10-20 | 1993-10-26 | Oki Electric Industry Co., Ltd. | Method for fabricating a semiconductor integrated circuit device |
KR0140979B1 (ko) * | 1989-10-20 | 1998-07-15 | 고스기 노부미쓰 | 반도체 집적회로 장치의 제조방법 |
JPH0774146A (ja) * | 1990-02-09 | 1995-03-17 | Applied Materials Inc | 低融点無機材料を使用する集積回路構造の改良された平坦化方法 |
US5077234A (en) * | 1990-06-29 | 1991-12-31 | Digital Equipment Corporation | Planarization process utilizing three resist layers |
US5175122A (en) * | 1991-06-28 | 1992-12-29 | Digital Equipment Corporation | Planarization process for trench isolation in integrated circuit manufacture |
US5300813A (en) | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
KR0121297B1 (en) * | 1992-04-16 | 1997-11-15 | Fujitsu Ltd | Semiconductor device and process of producing the same |
JP2820187B2 (ja) * | 1992-04-16 | 1998-11-05 | 三星電子 株式会社 | 半導体装置の製造方法 |
US5532191A (en) * | 1993-03-26 | 1996-07-02 | Kawasaki Steel Corporation | Method of chemical mechanical polishing planarization of an insulating film using an etching stop |
US5635428A (en) * | 1994-10-25 | 1997-06-03 | Texas Instruments Incorporated | Global planarization using a polyimide block |
KR0157875B1 (ko) * | 1994-11-03 | 1999-02-01 | 문정환 | 반도체 장치의 제조방법 |
KR100334525B1 (ko) * | 1995-12-29 | 2002-11-04 | 주식회사 하이닉스반도체 | 반도체 소자의 평탄화 방법 |
US8649123B1 (en) | 2008-11-26 | 2014-02-11 | Western Digital (Fremont), Llc | Method to eliminate reactive ion etching (RIE) loading effects for damascene perpendicular magnetic recording (PMR) fabrication |
US8257597B1 (en) | 2010-03-03 | 2012-09-04 | Western Digital (Fremont), Llc | Double rie damascene process for nose length control |
US9312273B2 (en) | 2013-12-02 | 2016-04-12 | International Business Machines Corporation | Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition |
US9496282B2 (en) * | 2013-12-02 | 2016-11-15 | International Business Machines Corporation | Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition |
US10879108B2 (en) * | 2016-11-15 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Topographic planarization method for lithography process |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5226182A (en) * | 1975-08-25 | 1977-02-26 | Hitachi Ltd | Manufacturing method of semi-conductor unit |
JPS5918858B2 (ja) * | 1976-09-22 | 1984-05-01 | 株式会社日立製作所 | ホトレジスト被膜の埋込方法 |
GB2060252B (en) * | 1979-09-17 | 1984-02-22 | Nippon Telegraph & Telephone | Mutually isolated complementary semiconductor elements |
JPS5664453A (en) * | 1979-10-31 | 1981-06-01 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
US4333227A (en) * | 1979-11-29 | 1982-06-08 | International Business Machines Corporation | Process for fabricating a self-aligned micrometer bipolar transistor device |
US4338138A (en) * | 1980-03-03 | 1982-07-06 | International Business Machines Corporation | Process for fabricating a bipolar transistor |
US4378630A (en) * | 1980-05-05 | 1983-04-05 | International Business Machines Corporation | Process for fabricating a high performance PNP and NPN structure |
JPS56160050A (en) * | 1980-05-14 | 1981-12-09 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
US4394196A (en) * | 1980-07-16 | 1983-07-19 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of etching, refilling and etching dielectric grooves for isolating micron size device regions |
DE3170644D1 (en) * | 1980-11-29 | 1985-06-27 | Toshiba Kk | Method of filling a groove in a semiconductor substrate |
US4394237A (en) * | 1981-07-17 | 1983-07-19 | Bell Telephone Laboratories, Incorporated | Spectroscopic monitoring of gas-solid processes |
-
1982
- 1982-05-31 JP JP57092917A patent/JPS58210634A/ja active Pending
-
1983
- 1983-05-23 US US06/497,407 patent/US4505025A/en not_active Expired - Lifetime
- 1983-05-27 EP EP83303080A patent/EP0098687B1/de not_active Expired
- 1983-05-27 DE DE8383303080T patent/DE3377958D1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0098687A2 (de) | 1984-01-18 |
US4505025A (en) | 1985-03-19 |
EP0098687A3 (en) | 1985-09-18 |
EP0098687B1 (de) | 1988-09-07 |
JPS58210634A (ja) | 1983-12-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |