DE2861528D1 - Method for making self-aligned integrated semiconductor devices - Google Patents

Method for making self-aligned integrated semiconductor devices

Info

Publication number
DE2861528D1
DE2861528D1 DE7878100092T DE2861528T DE2861528D1 DE 2861528 D1 DE2861528 D1 DE 2861528D1 DE 7878100092 T DE7878100092 T DE 7878100092T DE 2861528 T DE2861528 T DE 2861528T DE 2861528 D1 DE2861528 D1 DE 2861528D1
Authority
DE
Germany
Prior art keywords
semiconductor devices
integrated semiconductor
making self
aligned integrated
aligned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE7878100092T
Other languages
English (en)
Inventor
Augustine Wei-Chun Chang
Arun Kumar Gaind
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE2861528D1 publication Critical patent/DE2861528D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Weting (AREA)
DE7878100092T 1977-07-12 1978-06-06 Method for making self-aligned integrated semiconductor devices Expired DE2861528D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/814,801 US4135954A (en) 1977-07-12 1977-07-12 Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers

Publications (1)

Publication Number Publication Date
DE2861528D1 true DE2861528D1 (en) 1982-02-25

Family

ID=25216035

Family Applications (1)

Application Number Title Priority Date Filing Date
DE7878100092T Expired DE2861528D1 (en) 1977-07-12 1978-06-06 Method for making self-aligned integrated semiconductor devices

Country Status (4)

Country Link
US (1) US4135954A (de)
EP (1) EP0000327B1 (de)
JP (1) JPS5419668A (de)
DE (1) DE2861528D1 (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2358748A1 (fr) * 1976-07-15 1978-02-10 Radiotechnique Compelec Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procede
US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
US4199380A (en) * 1978-11-13 1980-04-22 Motorola, Inc. Integrated circuit method
US4289574A (en) * 1979-04-30 1981-09-15 Fairchild Camera & Instrument Corp. Process for patterning metal connections on a semiconductor structure by using an aluminum oxide etch resistant layer
US4243435A (en) * 1979-06-22 1981-01-06 International Business Machines Corporation Bipolar transistor fabrication process with an ion implanted emitter
US4333794A (en) * 1981-04-07 1982-06-08 International Business Machines Corporation Omission of thick Si3 N4 layers in ISA schemes
US4385947A (en) * 1981-07-29 1983-05-31 Harris Corporation Method for fabricating CMOS in P substrate with single guard ring using local oxidation
US4454646A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4454647A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
JPS5864044A (ja) * 1981-10-14 1983-04-16 Toshiba Corp 半導体装置の製造方法
US4550489A (en) * 1981-11-23 1985-11-05 International Business Machines Corporation Heterojunction semiconductor
US4460910A (en) * 1981-11-23 1984-07-17 International Business Machines Corporation Heterojunction semiconductor
US4443932A (en) * 1982-01-18 1984-04-24 Motorla, Inc. Self-aligned oxide isolated process and device
US4435898A (en) 1982-03-22 1984-03-13 International Business Machines Corporation Method for making a base etched transistor integrated circuit
JPS59124620A (ja) * 1982-12-30 1984-07-18 Nippon Mektron Ltd 自動メツキ装置
FR2568723B1 (fr) * 1984-08-03 1987-06-05 Commissariat Energie Atomique Circuit integre notamment de type mos et son procede de fabrication
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
US4583282A (en) * 1984-09-14 1986-04-22 Motorola, Inc. Process for self-aligned buried layer, field guard, and isolation
US4571816A (en) * 1984-12-11 1986-02-25 Rca Corporation Method of making a capacitor with standard self-aligned gate process
US4721682A (en) * 1985-09-25 1988-01-26 Monolithic Memories, Inc. Isolation and substrate connection for a bipolar integrated circuit
US4740827A (en) * 1985-09-30 1988-04-26 Kabushiki Kaisha Toshiba CMOS semiconductor device
US4696097A (en) * 1985-10-08 1987-09-29 Motorola, Inc. Poly-sidewall contact semiconductor device method
US4669177A (en) * 1985-10-28 1987-06-02 Texas Instruments Incorporated Process for making a lateral bipolar transistor in a standard CSAG process
US4936928A (en) * 1985-11-27 1990-06-26 Raytheon Company Semiconductor device
EP0257328B1 (de) * 1986-08-11 1991-10-23 Siemens Aktiengesellschaft Verfahren zur Stabilisierung von pn-Übergängen
US4738624A (en) * 1987-04-13 1988-04-19 International Business Machines Corporation Bipolar transistor structure with self-aligned device and isolation and fabrication process therefor
JPH084109B2 (ja) * 1987-08-18 1996-01-17 富士通株式会社 半導体装置およびその製造方法
JPH0678128B2 (ja) * 1987-11-13 1994-10-05 株式会社山田メッキ工業所 被処理物搬送装置
WO1989005519A1 (en) * 1987-12-02 1989-06-15 Advanced Micro Devices, Inc. Self-aligned interconnects for semiconductor devices
US5880036A (en) * 1992-06-15 1999-03-09 Micron Technology, Inc. Method for enhancing oxide to nitride selectivity through the use of independent heat control
US5651855A (en) * 1992-07-28 1997-07-29 Micron Technology, Inc. Method of making self aligned contacts to silicon substrates during the manufacture of integrated circuits
KR0161112B1 (ko) * 1995-01-11 1999-02-01 문정환 반도체 소자 격리방법
JPH10173052A (ja) * 1996-12-13 1998-06-26 Fujitsu Ltd 半導体装置及びその製造方法
US6124206A (en) * 1997-12-29 2000-09-26 Siemens Aktiengesellschaft Reduced pad erosion
DE10308870B4 (de) * 2003-02-28 2006-07-27 Austriamicrosystems Ag Bipolartransistor mit verbessertem Basis-Emitter-Übergang und Verfahren zur Herstellung
US20170183587A1 (en) * 2014-06-20 2017-06-29 Dow Global Technologies Llc Polyhydric alcohol compositions for gas dehydration
US11177132B2 (en) 2019-07-03 2021-11-16 International Business Machines Corporation Self aligned block masks for implantation control
TW202145344A (zh) * 2020-04-08 2021-12-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 用於選擇性蝕刻氧化矽膜之設備及方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3479237A (en) * 1966-04-08 1969-11-18 Bell Telephone Labor Inc Etch masks on semiconductor surfaces
US3560278A (en) * 1968-11-29 1971-02-02 Motorola Inc Alignment process for fabricating semiconductor devices
NL173110C (nl) * 1971-03-17 1983-12-01 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht.
US3860466A (en) * 1971-10-22 1975-01-14 Texas Instruments Inc Nitride composed masking for integrated circuits
DE2157633C3 (de) * 1971-11-20 1980-01-24 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zum Herstellen von Zonen einer monolithisch integrierten Festkörperschaltung
JPS5538823B2 (de) * 1971-12-22 1980-10-07
US3771218A (en) * 1972-07-13 1973-11-13 Ibm Process for fabricating passivated transistors
CA998778A (en) * 1972-07-13 1976-10-19 Martin M. Skowron Semiconductor manufacturing process
US3883372A (en) * 1973-07-11 1975-05-13 Westinghouse Electric Corp Method of making a planar graded channel MOS transistor
US3900352A (en) * 1973-11-01 1975-08-19 Ibm Isolated fixed and variable threshold field effect transistor fabrication technique
GB1492447A (en) * 1974-07-25 1977-11-16 Siemens Ag Semiconductor devices
US3948694A (en) * 1975-04-30 1976-04-06 Motorola, Inc. Self-aligned method for integrated circuit manufacture
US4021270A (en) * 1976-06-28 1977-05-03 Motorola, Inc. Double master mask process for integrated circuit manufacture
FR2358748A1 (fr) * 1976-07-15 1978-02-10 Radiotechnique Compelec Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procede
US4044452A (en) * 1976-10-06 1977-08-30 International Business Machines Corporation Process for making field effect and bipolar transistors on the same semiconductor chip

Also Published As

Publication number Publication date
US4135954A (en) 1979-01-23
EP0000327A1 (de) 1979-01-24
EP0000327B1 (de) 1982-01-13
JPS5419668A (en) 1979-02-14

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee