DE19916636A1 - Semiconductor chip with ferromagnetic screen - Google Patents

Semiconductor chip with ferromagnetic screen

Info

Publication number
DE19916636A1
DE19916636A1 DE19916636A DE19916636A DE19916636A1 DE 19916636 A1 DE19916636 A1 DE 19916636A1 DE 19916636 A DE19916636 A DE 19916636A DE 19916636 A DE19916636 A DE 19916636A DE 19916636 A1 DE19916636 A1 DE 19916636A1
Authority
DE
Germany
Prior art keywords
layer
circuit
semiconductor chip
ferromagnetic
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19916636A
Other languages
German (de)
Inventor
Peter Hofreiter
Holger Sedlak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19916636A priority Critical patent/DE19916636A1/en
Publication of DE19916636A1 publication Critical patent/DE19916636A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The semiconductor chip has a circuit (2) developed in the semiconductor substrate (1), and includes a conductive screening layer (4) for protecting the circuit, at least on one side, against electric fields. A further, ferromagnetic, layer (5) is provided for protecting the circuit, at least on one side, against magnetic fields, and is preferably arranged over the surface of the semiconductor substrate supporting the circuit layer. The ferromagnetic layer (5,5a) almost completely surrounds the semiconductor chip.

Description

Die Erfindung betrifft einen Halbleiterchip mit einer in ei­ nem Halbleitersubstrat realisierten Schaltung und einer die Schaltung zumindest einseitig vor elektrischen Feldern ab­ schirmenden leitenden Abdeckung.The invention relates to a semiconductor chip with an egg nem semiconductor substrate realized circuit and a die Switch off at least on one side from electrical fields shielding conductive cover.

Ein solcher Halbleiterchip ist aus der EP 0 169 941 B1 be­ kannt. Die dortige leitende Abdeckung dient zwar in erster Linie dazu, einen Schutz vor optischer beziehungsweise elek­ tronenoptischer Analyse der Schaltungsmuster im Halbleiter­ substrat zu bieten, da die leitende Abdeckung elektrisch mit der Schaltung in Verbindung ist und ein Entfernen dieser Ab­ deckung einfach detektiert werden kann und geeignete Schutz­ maßnahmen eingeleitet werden können. Allerdings bildet diese bekannte leitende Abdeckung auch einen Schutz vor der stören­ den Einstrahlung elektrischer Felder und darüber hinaus einen Schutz vor der Abstrahlung elektrischer Felder, die abgehört werden könnten und eine Analyse der in der Schaltung ablau­ fenden Vorgänge ermöglichen würden.Such a semiconductor chip is known from EP 0 169 941 B1 knows. The conductive cover there serves first Line to protect against optical or elec Tron-optical analysis of the circuit pattern in the semiconductor to offer substrate, because the conductive cover electrically with the circuit is connected and removing this Ab cover can be easily detected and appropriate protection measures can be initiated. However, this forms known conductive cover also provide protection from the disturb the radiation of electrical fields and beyond Protection against the radiation of electrical fields that are intercepted could be and an analysis of the in the circuit ablau would enable processes to take place.

Allerdings kann diese leitende Abdeckung von magnetischen Feldern ungehindert durchdrungen werden und somit nach wie vor informationstragende Strahlung nach außerhalb des Chips gelangen.However, this conductive cover can be magnetic Fields are penetrated unhindered and thus still before information-carrying radiation outside the chip reach.

Die Aufgabe der Erfindung ist es daher, einen Halbleiterchip anzugeben, bei dem auch die Abstrahlung magnetischer Felder verringert oder verhindert ist.The object of the invention is therefore a semiconductor chip specify where the radiation of magnetic fields is reduced or prevented.

Die Aufgabe wird durch einen Halbleiterchip gemäß Anspruch 1 gelöst. Vorteilhafte Weiterbildungen der Erfindung sind in den Unteransprüchen angegeben. The object is achieved by a semiconductor chip according to claim 1 solved. Advantageous developments of the invention are in specified in the subclaims.  

Durch die erfindungsgemäße zusätzliche ferromagnetische Schicht wird das magnetische Feld stark gedämpft und dadurch wirksam abgeschirmt.Due to the additional ferromagnetic Layer, the magnetic field is strongly damped and thereby effectively shielded.

Die abschirmende ferromagnetische Abdeckung kann nur auf der die Schaltung aufweisenden Oberfläche des Halbleitersubstrats aber auch auf beiden Oberflächen angeordnet sein oder gar den Halbleiterchip vollständig umhüllen, abgesehen von Öffnungen für die elektrische Kontaktierung.The shielding ferromagnetic cover can only be used on the the circuit having the surface of the semiconductor substrate but can also be arranged on both surfaces or even the Fully encapsulate the semiconductor chip, apart from openings for electrical contacting.

Die Erfindung wird nachfolgend anhand eines Ausführungsbei­ spiels mit Hilfe einer Figur näher erläutert. Dabei zeigt dieThe invention is illustrated below with the aid of an embodiment game explained with the help of a figure. The shows

Figur ein Halbleitersubstrat mit darauf angeordneter fer­ romagnetischer Schicht.Figure a semiconductor substrate with fer arranged thereon romagnetic layer.

Die Figur zeigt ein Halbleitersubstrat 1 mit einer in einer Oberfläche ausgebildeten Schicht 2 mit darin realisierten elektrischen Schaltkreisen. Im dargestellten Beispiel ist oberhalb der Schaltkreisschicht 2 eine leitende Schicht 4 an­ geordnet, die von der Schaltkreisschicht 2 durch eine nicht leitende Schicht 3 isoliert sein muß, um keine Kurzschlüsse hervorzurufen. Oberhalb der leitenden Schicht 4 ist eine Schicht 5 aus ferromagnetischem Material angeordnet. Diese ferromagnetische Schicht 5 könnte auch unterhalb der leiten­ den Schicht 4 angeordnet werden. Für den Fall, daß das ferro­ magnetische Material nicht leitend ist, könnte in diesem Fall auf die isolierende Schicht 3 verzichtet werden.The figure shows a semiconductor substrate 1 with a layer 2 formed in a surface with electrical circuits implemented therein. In the example shown, a conductive layer 4 is arranged above the circuit layer 2 , which must be insulated from the circuit layer 2 by a non-conductive layer 3 in order not to cause short circuits. A layer 5 made of ferromagnetic material is arranged above the conductive layer 4 . This ferromagnetic layer 5 could also be arranged below the conductive layer 4 . In the event that the ferromagnetic material is not conductive, the insulating layer 3 could be dispensed with in this case.

Prinzipiell könnte auch nur eine Schicht, die sowohl leitende als auch ferromagnetische Eigenschaften aufweist verwendet werden.In principle, just one layer could be both conductive as well as having ferromagnetic properties become.

Eine nur auf der die Schaltungsschicht aufweisenden Oberflä­ che des Halbleitersubstrats 2 angeordnete ferromagnetische Schicht 5 wird in den meisten Fällen für eine wirksame Ab­ schirmung ausreichen. Für eine noch wirksamere Abschirmung kann jedoch auch, wie dies strichliert dargestellt ist, der gesamte Halbleiterchip von der ferromagnetischen Schicht 5, 5a umhüllt sein.A ferromagnetic layer 5 arranged only on the surface of the semiconductor substrate 2 which has the circuit layer will in most cases be sufficient for effective shielding. For an even more effective shielding, however, the entire semiconductor chip can also be encased by the ferromagnetic layer 5 , 5 a, as shown in broken lines.

Claims (3)

1. Halbleiterchip mit einer in einem Halbleitersubstrat (1) realisierten Schaltung (2) und einer die Schaltung (2) zumin­ dest einseitig vor elektrischen Feldern abschirmenden leiten­ den Schicht (4), gekennzeichnet durch eine weitere die Schaltung (2) zumindest einseitig vor magne­ tischen Feldern abschirmenden ferromagnetischen Schicht (5).1. A semiconductor chip with a circuit ( 2 ) realized in a semiconductor substrate ( 1 ) and a circuit ( 2 ) shielding the circuit ( 2 ) at least on one side from electrical fields, the layer ( 4 ), characterized by a further circuit ( 2 ) at least on one side table fields shielding ferromagnetic layer ( 5 ). 2. Halbleiterchip nach Anspruch 1, dadurch gekennzeichnet, daß die ferromagnetische Schicht (5) über der die Schaltungs­ schicht (2) aufweisenden Oberfläche des Halbleitersubstrats (1) angeordnet ist.2. Semiconductor chip according to claim 1, characterized in that the ferromagnetic layer ( 5 ) over the circuit layer ( 2 ) having the surface of the semiconductor substrate ( 1 ) is arranged. 3. Halbleiterchip nach Anspruch 2, dadurch gekennzeichnet, daß die ferromagnetische Schicht (5, 5a) den Halbleiterchip nahezu vollständig umhüllt.3. A semiconductor chip according to claim 2, characterized in that the ferromagnetic layer ( 5 , 5 a) envelops the semiconductor chip almost completely.
DE19916636A 1999-04-13 1999-04-13 Semiconductor chip with ferromagnetic screen Ceased DE19916636A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19916636A DE19916636A1 (en) 1999-04-13 1999-04-13 Semiconductor chip with ferromagnetic screen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19916636A DE19916636A1 (en) 1999-04-13 1999-04-13 Semiconductor chip with ferromagnetic screen

Publications (1)

Publication Number Publication Date
DE19916636A1 true DE19916636A1 (en) 2000-06-29

Family

ID=7904387

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19916636A Ceased DE19916636A1 (en) 1999-04-13 1999-04-13 Semiconductor chip with ferromagnetic screen

Country Status (1)

Country Link
DE (1) DE19916636A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004040503A1 (en) * 2004-08-20 2006-02-23 Infineon Technologies Ag Semiconductor element such as a conductive bridging RAM has chip in housing with screening layer on chip and housing for electric and or magnetic shielding
CN110459530A (en) * 2019-07-26 2019-11-15 南通通富微电子有限公司 Encapsulating structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0667643A1 (en) * 1994-01-20 1995-08-16 Tokin Corporation Electromagnetic interference suppressing body having low electromagnetic transparency and reflection, and electronic device having the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0667643A1 (en) * 1994-01-20 1995-08-16 Tokin Corporation Electromagnetic interference suppressing body having low electromagnetic transparency and reflection, and electronic device having the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004040503A1 (en) * 2004-08-20 2006-02-23 Infineon Technologies Ag Semiconductor element such as a conductive bridging RAM has chip in housing with screening layer on chip and housing for electric and or magnetic shielding
CN110459530A (en) * 2019-07-26 2019-11-15 南通通富微电子有限公司 Encapsulating structure
CN110459530B (en) * 2019-07-26 2021-07-02 南通通富微电子有限公司 Packaging structure

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Date Code Title Description
OAV Publication of unexamined application with consent of applicant
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection