CN87107369A - 集成双板晶体管的集电极接触 - Google Patents
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Abstract
本发明提出了附属在集电极区(1)侧面上的集电极接触(6),及制造该接触的方法,在此过程中,产生沟槽(3),它侧向地限制了集电极区(1),沟槽(3)的深度的尺寸至少等于集电极区(1)的厚度。集电极接触(6)包括含有集电极区(1)导电类型掺杂剂的多晶硅,并覆盖了从相邻的集电极接触(6)扩散的高掺杂的接触区(7′)。
Description
本发明涉及到在集成双极晶体管中接触点节省空间的应用。众所周知,在德国技术杂志(German technical Journal“Elektronik”,10(1984年5月18日)第68和69页上所描述的,接触点被施加到横向延伸的区域。
进而,从DE-A26 21 165中知道接触到围绕基区的U形沟槽的底表面的集电极区。
本发明从已知的前面提到的DE-A2621165的集成双极晶体管型的集电极接触开始,其一种导电类型的集电极区是在另一种导电类型的硅的片状半导体衬底的主表面上,用完全围绕集电极区的U形沟槽的方法,与单块集成固体电路中其余的半导体器绝缘的。
本发明的目的是提供一个集电极区节省空间的接触的方法。本发明的主导思想是基于主要在纵向延伸中实现集电极接触。
根据本发明,此上述目的的获得是在于集电极区的集电极接触设置在沟槽的侧壁上并包括具有集电极区的导电类型的掺杂剂的一层多晶硅,在于集电极接触复盖了集电极区导电类型的高掺杂接触区,在于沟槽的底表面复盖一层二氧化硅,在于沟槽的深度至少等于集电极区的厚度。
根据本发明,权利要求2提出的集电极接触的进一步的实施,是直接在二氧化硅层的下面提供掺杂的多晶硅的导体引线,它设置在围绕上述导体引线的二氧化硅的又一层,与二氧化硅层共同存在于沟槽的底表面。这样,无需任何在空间的进一步投资即可获得设置在半导体体内深处的导体网络,它或可作为集成电路单个元件的屏蔽不然就为元件电源的屏蔽。
下面本发明将参照一个具体实例进行说明,该实施例与欧洲专利申请EP-A0071665中公开的通常的方法密切相关,并与通常方法相容。根据此惯用方法,发射极区用氧化掩蔽层复盖,采用确定的不同加速电压下的二次离子注入工艺,借助注入掩膜确定了基极区后便形成了带有基极接触区的基极区。
本发明将参照附图1-9作详细说明,其中:
图1到图7示出了集成双极晶体管的斜面剖示图,不是实际的尺寸,用以说明根据本发明方法的连续进行的处理步骤;
图8示出了从图7中可看到的在S-S′线上的截面剖示略图,
图9用于说明根据本发明方法的又一实施例。
此后描述的实施例是指集成的NPN双极晶体管,它具有有利的高频或开关特性。当然在采用根据本发明的方法中,适当地选择一不同的导电类型时,集电极接触也可附着到集成的PNP双极晶体管上。
根据本发明的较佳实施例,是从轻掺杂P型导电半导体衬底2开始的,在其主表面上产生最好用离子注入生成的轻n型导电的硅单晶层。如图1所示,集电极区1用限制它的沟槽3的各向异性的腐蚀,预定要延伸穿过单晶硅层。沟槽3的深度必须至少等于集电极区1的厚度,这样才能确保要制造的双极晶体管与其余的集成固体电路的元件有安全可靠的电绝缘。
各向异性腐蚀工艺只能从气相进行,对半导体材料以及二氧化硅和氮化硅的腐蚀是已知的,因此在此不拟详述。
在制备了集电极区1之后,如图2所示,半导体衬底2暴露的表面部分或主表面部分,包括沟槽3的表面部分用热生长的二氧化物层4复盖。后者包括二氧化物层的侧壁层7。在热生长的二氧化物层4上淀积氮化硅层4′。之后进行各向异性的氮化物腐蚀,因此通过这样的直接的腐蚀氮化硅层,未掩蔽的沟槽的主表面和底表面上的氮化物层部分就被去除了。
从掩蔽层层序4,4′部分,结果使得将集电极电极接触区保持在主表面上成为可能,并使发射极区不受热生成的绝缘层的影响。这样当适当地选定层4,4′的厚度时,根据本发明的方法与前面提到的EP-A 0071665已知的方法是一致的,其中公开了与基极区接触区一起(包括后者的基极区)发射极区的自调整制造。
与此相关,如图3所示,看一下EP-A0071665中公开的方法,发射区41和没有包括在图3的切口中的集电极接触区,它们是通过光刻抗蚀剂的掩蔽层M1防止腐蚀而得到保护的。然后在与主表面垂直的择优方向进行各向异性的氮化物腐蚀,当然,在沟槽的侧壁以及掩蔽层M1下保留了氮化物层。此后进行通常的二氧化物腐蚀,在此过程中,在沟槽3侧壁上的氮化物层以及掩蔽层M1被掩蔽,结果,沟槽3的底表面以及围绕发射极区41和集电极接触区的半导体材料被暴露。这样获得了如图3所示的截面图的布局。
为了制造在发射极区下累进的(graduated)或阶梯式的基极区,(它仍然要产生的)如在已提到的EP-A 0071665中描述的那样,半导体衬底2的导电类型离子-P型导电离子注入到半导体表面的暴露部分。沟槽3的底在足够高的温度下允许活化,然后,这些离子形成了如图4所示的沟道-阻碍区9。
根据本发明并参照上边提到的EP-A 0071665中公开的方法进一步运用本法,在本发明最佳应用中,衬底导电类型的离子以任意选择的次序,一次以初始加速电压注入,穿透氧化物层4和氮化物层4′,而一次以另一加速压注入,以掩蔽在发射极区和收集极接触区上的层序4,4′。由此将产生如图4截面图所示的布局,包括激活基极区5和基极接触区5′。然而在进行P型杂质掺杂注入之前,必须小心地将掩蔽层M1去除。
在此之后进行热氧化,在此过程中,在沟槽3的底表面上形成了绝缘层8,在主表面上形成了绝缘层81,81延伸到围绕发射极区41的集电极接触区。这样便获得了图5的部分截面图中示出的布局,设集电极接触区是位于截面的表面之后。
下面层序4,4′的部分,由于仍然保留在侧壁表面的发射极区41上,在进行正常的氧化物腐蚀之前采用通常的氮化物腐蚀去除,如图6所示。考虑到层序4,4′的氧化物层4比二氧化硅层81和8薄,可在气相中进行通常的各向异性腐工艺,它在达到时停止,这样,在沟槽3底上的绝缘层8和在发射极区41及集电极接触区以外的绝缘层81基本上被保留住。
用于除去沟槽3侧壁上和发射极区41上的相对薄的层序4,4′,的氮化物腐蚀和氧化物腐蚀工艺之后,在布局的主表面上沉积一层掺杂的多晶硅,此层含有集电极区的导电类型掺杂剂,这样有可能制备集电极接触和/或双极晶体管的发射极区,它是通过腐蚀掩蔽层,最好用光致抗蚀剂在多晶硅层上掩蔽,示例如图7。由图8可看到采用了腐蚀掩膜M2,在主表面上确定了用于集电极6和发射极电极10的接触区6′,它重叠了绝缘层81的边缘部分,和在发射极区41外侧的部分。在下面的高温工艺过程中,从n掺杂的多晶硅层的其余部分向各种区进行扩散,即从发射极电极10的发射极区11,在图7的斜面剖示中没有示出的集电极接触区,从作为主表面上的边界和带或条形设计的集电极接触区7′构成集电极区1的边框的接触部分6′,从邻接集电极区1的部分6侧表面。该集电极接触区7′分别与外边的基极区部分5′以及P型导电半导体衬底2形成了一个PN(P-n)结。
由集电极区1的侧壁接触导致了空间非常节省和极低的欧姆接触。只在主表面上需要一个用于导线引线的接触表面C,它可被限制为和发射极接触表面E和基极接触表面B一样小的尺寸。
如参照图9所说明的,发射极接触也可籍助于多晶硅的导体引线12,它被直接设置在沟槽3底表面上的二氧化硅层8的下面。
根据图2,在层序4,4′形成后可将掺杂多晶硅的导体引线12***到沟槽3,用热氧化的方法它在表面产生另一层二氧化硅8′,这样就产生了另一附加的导体引线面(level)使其可与底或框边连接,或用于连接集电极区的目的,否则用于使集电极区彼此间实现电屏蔽。
沟槽或在特定的沟槽3中可采用已知的一种平面扩散工艺来填充绝缘材料,这样在主表面上即形成一平的或平面的用于导体引线的布线表面。
Claims (4)
1、集成双极晶体管的集电极接触,其一种导电类型的集电极区是在另一导电类型的片状半导体硅衬底的一主表面上绝缘,与单块集成固体电路的其余器件相绝缘,这是通过完全围绕集电极区(1)的沟槽3完成的,其特征在于:
上述集电极区(1)的集电极接触(6)设置在上述沟槽(3)的侧壁上,并包含具有上述集电极区(1)的导电类型的掺杂剂的一层多晶硅,
上述集电极(6)复盖了上述集电极区(1)的导电类型的高掺杂的接触区(7′),
上述沟槽(3)的底表面复盖了一层二氧化硅(8),
上述沟槽(3)的深度至少等于上述集电极区(1)的厚度。
2、如权利要求(1)中的集电极接触,其特征在于:
在上述二氧化硅层(8)的下面直接设置一掺杂多晶硅的导体引线(12),依次,设置另一二氧化硅层(8′)与上述二氧化硅层(8)一起围绕上述导体引线(12),存在于上述沟槽(3)的底表面(图9)。
3、如权利要求(1)或(2)中所要求的一种制造集电极接触的方法,其特征为下述处理步骤:
(a)在另一导电类型的半导体衬底(2)的主表面上形成导电的单晶硅层,用各向异性腐蚀穿透上述硅层而形成沟槽(3),上述集电极区的边缘部分被暴露出;
(b)在半导体衬底(2)主表面的表面部分包括上述沟槽(3)的表面部分用热生长的氧化物层(4)复盖,它包括侧壁二氧化物层(7)和在其上淀积的氮化硅层(4′);
(c)下一步进行各向异性的氮化物的腐蚀工艺,通过该工艺去除了在上述沟槽(3)的侧表面和底表面上的氮化硅层(4′)的未掩蔽部分;
(d)然后进行氧化物腐蚀,用于暴露出氧化物层的非掩蔽部分,通过此工艺暴露出上述沟槽(3)的底表面和主表面的未掩蔽部分;
(e)之后,将衬底的导电类型离子注入到半导体表面的暴露的部分,在上述沟槽(3)的底表面上,当激活时,同时形成了沟道-阻碍区(9)和双极晶体管的基极区(5,5′);(图4)
(f)上述步骤之后,然后进行热氧化,这样在上述沟槽(3)的底表面且暴露的硅上形成了一绝缘层(8),其厚度超过侧壁二氧化物层(7)的厚度(图5);
(g)然后进行氮化物腐蚀,用腐蚀除去侧壁上较薄的二氧化物层(7),基本上保留了上述沟槽(3)底上的绝缘层(8)(图6);
(h)之后,淀积含有集电极区的导电类型的掺杂剂的多晶硅层;
(i)然后,经过各向异性腐蚀,除去了在上述沟槽(3)的底表面和上述主表面上未掩蔽的区域中掺杂的多晶硅,这样在其后的高温处理过程中形成了集电极接触,复盖了集电极区的导电型的相邻的接触区(7′)。
4、如权利要求3中所述的方法,其特征为下列工艺步骤:
b′)紧接处理步骤b),用掩蔽层(M1)将集电极区(41)掩蔽,这样以保护该区不被腐蚀;
c′)而后接处理步骤c)和d),上述沟槽(3)的底表面以及发射极区(41)的周围和集电极接触区(12)的周围(图3);
d′)去除掩蔽层(M1);
e′)之后,在处理步骤e)的过程中,以随意或任意样的次序,将衬底导电型的离子一次以初始加速电压注入,使得包括氧化物层(4)和氮化物层(4′)的层序被穿透,在另一时间,以第二次加速电压使得上述层序(4,4′)在上述发射极区(41)和上述集电极-接触区(12)生效;
f′)之后,进行热氧化步骤,这样,在上述沟槽(3)的底表面及发射极区(41)的外侧,以及上述集电极接触区(12)的外侧(图5)分别形成了绝缘层(8,81);
g′)进行处理步骤g),在此过程中,除了在上述沟槽(3)的底上的绝缘层(8)外,保留了在发射极区(41)及集电极接触区(12)(图6)的外边形成的绝缘层(81);
h′)下面在仍然存在的层序(4,4′)去除之后,接处理步骤h),淀积了上述多晶硅层;
i′)处理步骤i)是通过采用腐蚀掩膜(M2)进行的,在主表面上确定了集电极(6)的接触区(6′)和发射极电极((10)它重迭了在上述发射极区(41)之外形成的绝缘区(81),这样在下面的高温处理过程中的形成了脱离了与接触区(7′)相接的集电极接触(6,6′),和与发射极区(11)相接的发射极电极(10)。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP86117692A EP0271599B1 (de) | 1986-12-18 | 1986-12-18 | Kollektorkontakt eines integrierten Bipolartransistors |
EP86117692 | 1986-12-18 | ||
EP86117692.3 | 1986-12-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN87107369A true CN87107369A (zh) | 1988-06-29 |
CN1016125B CN1016125B (zh) | 1992-04-01 |
Family
ID=8195655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN87107369A Expired CN1016125B (zh) | 1986-12-18 | 1987-12-11 | 集成双极晶体管的集电极接触 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4992843A (zh) |
EP (1) | EP0271599B1 (zh) |
JP (1) | JP2585329B2 (zh) |
CN (1) | CN1016125B (zh) |
DE (1) | DE3681291D1 (zh) |
Cited By (1)
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CN100375293C (zh) * | 2001-11-20 | 2008-03-12 | 通用半导体公司 | 具有多晶硅源极接触结构的沟槽mosfet器件 |
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JP2890550B2 (ja) * | 1989-11-14 | 1999-05-17 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US5289024A (en) * | 1990-08-07 | 1994-02-22 | National Semiconductor Corporation | Bipolar transistor with diffusion compensation |
US5250837A (en) * | 1991-05-17 | 1993-10-05 | Delco Electronics Corporation | Method for dielectrically isolating integrated circuits using doped oxide sidewalls |
US5250461A (en) * | 1991-05-17 | 1993-10-05 | Delco Electronics Corporation | Method for dielectrically isolating integrated circuits using doped oxide sidewalls |
US5341023A (en) * | 1992-06-18 | 1994-08-23 | International Business Machines Corporation | Novel vertical-gate CMOS compatible lateral bipolar transistor |
JP2708027B2 (ja) * | 1995-10-05 | 1998-02-04 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US5856700A (en) * | 1996-05-08 | 1999-01-05 | Harris Corporation | Semiconductor device with doped semiconductor and dielectric trench sidewall layers |
US6853048B1 (en) * | 2000-08-11 | 2005-02-08 | Agere Systems Inc. | Bipolar transistor having an isolation structure located under the base, emitter and collector and a method of manufacture thereof |
US6864547B2 (en) | 2001-06-15 | 2005-03-08 | Agere Systems Inc. | Semiconductor device having a ghost source/drain region and a method of manufacture therefor |
US6958518B2 (en) * | 2001-06-15 | 2005-10-25 | Agere Systems Inc. | Semiconductor device having at least one source/drain region formed on an isolation region and a method of manufacture therefor |
US6809386B2 (en) * | 2002-08-29 | 2004-10-26 | Micron Technology, Inc. | Cascode I/O driver with improved ESD operation |
US7691734B2 (en) * | 2007-03-01 | 2010-04-06 | International Business Machines Corporation | Deep trench based far subcollector reachthrough |
US7692483B2 (en) * | 2007-10-10 | 2010-04-06 | Atmel Corporation | Apparatus and method for preventing snap back in integrated circuits |
US8085604B2 (en) * | 2008-12-12 | 2011-12-27 | Atmel Corporation | Snap-back tolerant integrated circuits |
EP3024020A1 (en) * | 2014-11-19 | 2016-05-25 | Nxp B.V. | Semiconductor device and method |
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FR547012A (fr) * | 1922-01-21 | 1922-11-29 | Signal Gmbh | Procédé et dispositif pour déterminer les distances par des ondes acoustiques réfléchies |
BE631066A (zh) * | 1962-04-16 | |||
CH547012A (de) * | 1967-11-14 | 1974-03-15 | Sony Corp | Dispositif semi-conducteur. |
GB1534896A (en) * | 1975-05-19 | 1978-12-06 | Itt | Direct metal contact to buried layer |
JPS5244186A (en) * | 1975-10-06 | 1977-04-06 | Hitachi Ltd | Semiconductor intergrated circuit device |
US4339767A (en) * | 1980-05-05 | 1982-07-13 | International Business Machines Corporation | High performance PNP and NPN transistor structure |
EP0071665B1 (de) * | 1981-08-08 | 1986-04-16 | Deutsche ITT Industries GmbH | Verfahren zum Herstellen einer monolithisch integrierten Festkörperschaltung mit mindestens einem bipolaren Planartransistor |
DE3586341T2 (de) * | 1984-02-03 | 1993-02-04 | Advanced Micro Devices Inc | Bipolartransistor mit in schlitzen gebildeten aktiven elementen. |
JPH0618198B2 (ja) * | 1984-02-15 | 1994-03-09 | 株式会社日立製作所 | 半導体装置 |
JPS60241230A (ja) * | 1984-05-16 | 1985-11-30 | Hitachi Micro Comput Eng Ltd | 半導体装置 |
JPS6146063A (ja) * | 1984-08-10 | 1986-03-06 | Hitachi Ltd | 半導体装置の製造方法 |
US4674173A (en) * | 1985-06-28 | 1987-06-23 | Texas Instruments Incorporated | Method for fabricating bipolar transistor |
US4711017A (en) * | 1986-03-03 | 1987-12-08 | Trw Inc. | Formation of buried diffusion devices |
-
1986
- 1986-12-18 EP EP86117692A patent/EP0271599B1/de not_active Expired - Lifetime
- 1986-12-18 DE DE8686117692T patent/DE3681291D1/de not_active Expired - Fee Related
-
1987
- 1987-12-11 CN CN87107369A patent/CN1016125B/zh not_active Expired
- 1987-12-17 JP JP62320051A patent/JP2585329B2/ja not_active Expired - Lifetime
-
1989
- 1989-11-03 US US07/433,406 patent/US4992843A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100375293C (zh) * | 2001-11-20 | 2008-03-12 | 通用半导体公司 | 具有多晶硅源极接触结构的沟槽mosfet器件 |
Also Published As
Publication number | Publication date |
---|---|
EP0271599A1 (de) | 1988-06-22 |
CN1016125B (zh) | 1992-04-01 |
DE3681291D1 (de) | 1991-10-10 |
JP2585329B2 (ja) | 1997-02-26 |
US4992843A (en) | 1991-02-12 |
EP0271599B1 (de) | 1991-09-04 |
JPS63164366A (ja) | 1988-07-07 |
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