CN2741188Y - Structure of reverse-fuse memory assembly - Google Patents
Structure of reverse-fuse memory assembly Download PDFInfo
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- CN2741188Y CN2741188Y CN 200420067254 CN200420067254U CN2741188Y CN 2741188 Y CN2741188 Y CN 2741188Y CN 200420067254 CN200420067254 CN 200420067254 CN 200420067254 U CN200420067254 U CN 200420067254U CN 2741188 Y CN2741188 Y CN 2741188Y
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Abstract
The utility model relates to a structure of reverse-fuse memory assembly which comprises a metal silicide layer, a first type conductive layer on the metal silicide layer, a reverse-fuse layer on the first type conductive layer and a second type conductive layer on the reverse-fuse layer. According to the structure of the utility model, the total resistance mass of the polycrystalline silicon and the silicide layer is lower, because the structure of reverse-fuse memory assembly reduces a polycrystalline silicon layer compared with the prior art. The drive current of the reverse-fuse memory assembly can be increased.
Description
Technical field
The utility model relates to a kind of semiconductor assembly structure to be improved, particularly about a kind of structure of improving anti-fuse-type memory assembly polysilicon and metal silicide processing procedure.
Background technology
Anti-fuse-type memory assembly is a kind of memory assembly of three-dimensional, and its memory cell is provided in a side of the positive pole of diode and the antifuse layer between the negative pole to do control.When antifuse layer was intact, its anodal and negative pole opened circuit each other, but when antifuse layer is destroyed, its anodal and negative pole formation diode, and its line design is that the material of positive pole and negative pole is orthogonal.The anti-fuse-type memory assembly of three-dimensional structure and traditional two-dimensional structure memory compare, and the memory that the long-pending floor space of the silicon of its required use is more traditional is little, also therefore, can increase the positive degree of memory, reduces the cost of unit are.Anti-in addition fuse-type memory assembly can provide preferable protection owing to have the characteristic of a burning (OTP) on confidentiality.
See also Figure 1A to Fig. 1 D, be the generalized section of the metal silicide processing procedure of existing anti-fuse-type memory assembly polysilicon.Shown in Figure 1A, the dielectric layer processing procedure was finished on the semiconductor-based end 100 between plain conductor and lead thereof, omitted for simple diagram, the polysilicon layer of deposition one doping P+ on dielectric layer between plain conductor and lead thereof is with as bottom polysilicon layer 110 herein.Deposit a undoped polysilicon or amorphous silicon layer as react polysilicon layer 111 in bottom polysilicon layer 110 on thereafter.Then, deposit a titanium coating 119 and follow-up titanium nitride layer 120 on undoped polysilicon or amorphous silicon layer 111.
Next, shown in Figure 1B, use a prompt tempering processing procedure, so that reaction polysilicon layer and titanium coating 119 and 120 reactions of part titanium nitride layer form a titanium-silicon compound layer 130.The titanium-silicon compound layer 130 of its formation has low electrical conductivity and good thermal stability, can reduce the resistance between lead.Afterwards, on titanium-silicon compound, deposit the polysilicon layer of one deck doping P+ as the first type conductive layer 135.
Follow-up, shown in Fig. 1 C, carry out a thermal oxidation processing procedure to form an antifuse layer 136 on the first type conductive layer 135.The antifuse layer 136 of its formation is the primary clustering as the anti-fuse-type memory cell of control.Thereafter, the antifuse layer 136 that forms before the definition, titanium-silicon compound layer 130, the first type conductive layer 135 and bottom polysilicon layer 110 are to form character line, it comprises little shadow, insert dielectric material and follow-up cmp processing procedure behind etching and the formation lead between lead, it is general existing skill, does not encyclopaedize at this.At last, shown in Fig. 1 D, the polysilicon layer that deposits a doping N is as the second type conductive layer 140, and defines the second type conductive layer 140 to form bit line.
See also shown in Figure 3, it is the stereogram of the metal silicide processing procedure of existing anti-fuse-type memory assembly polysilicon, bottom polysilicon layer 110 is formed at semiconductor-based the end 100, and bottom polysilicon layer 110, titanium-silicon compound layer 130, titanium nitride layer 120, the first type conductive layer 135 are arranged on it in regular turn.Bottom polysilicon layer 110, titanium-silicon compound layer 130 and the first type conductive layer 135 are as character line (WL).The second type conductive layer 140 is as accompanying an antifuse layer 136 in bit line (BL) and itself and the first type conductive layer 135.
This processing procedure needs polysilicon layer and follow-up undoped polysilicon or the amorphous silicon layer of deposition one P+ earlier when forming the titanium silicide.The titanium coating of heating deposition is so that titanium coating and the undoped polysilicon under it or amorphous silicon layer reaction form the titanium silicide layer.Again deposit the polysilicon layer of one deck doping P+ thereafter.Its step that forms the first type conductive layer is quite loaded down with trivial details, and the polysilicon deposition of multilayer must be constantly by the gross wafer take out by previous reactor and insert again in the reactor that reacts in advance, not only step is numerous and diverse, and need wait as long for and vacuumize, to reach the chamber pressure of standard, quite expend the processing procedure time.
Application No. has disclosed a kind of memory cell of low-leakage current for No. 09/560626, wherein between the diode of positive pole and negative pole, place an antifuse layer, when antifuse layer when being intact, its positive pole and negative pole open circuit each other, but when antifuse layer was destroyed, its positive pole and negative pole were connected at the antifuse layer of a zonule, also therefore formed diode, also because its very the fuse of zonule make its diode have very little scope zone, the also therefore relatively little leakage current of its tool.United States Patent (USP) discloses a kind of three-dimensional No. 6525953 in addition, programmable, nonvolatile memory cell, it is the column by a self-aligned, wherein comprises the positive pole and the negative pole assembly of diode, and between wherein antifuse layer, and column forms its memory cell according to this, its operation principles also is to be intact and whether to destroy according to antifuse layer, forms circuit, and the data of decision storage.
Therefore, for overcoming above-mentioned existing method, promptly, produced the utility model in positive pole that forms diode and the shortcoming that the negative pole assembly all is to use the polysilicon of doping.
The utility model content
In view of this, in order to address the above problem, a purpose of the present utility model is to provide a kind of structure of anti-fuse-type memory assembly of simplification, it can reduce the deposition step of polysilicon, to simplify the processing procedure that forms metal silicide, reduction processing procedure time, and attenuating manufacturing cost.
Another purpose of the present utility model is to provide a kind of structure of anti-fuse-type memory assembly, and it can reach the overall resistance matter that reduces polysilicon and silicide layer by reducing by a polysilicon layer, and increases the drive current of anti-fuse-type memory assembly by this.
The utility model proposes a kind of polysilicon and silicide structural of anti-fuse-type memory assembly, it comprises: a metal silicide layer, one first type conductive layer on this metal silicide layer, an antifuse layer on this first type conductive layer and one second type conductive layer on this antifuse layer.According to structure of the present utility model,,, can increase the drive current of anti-fuse-type memory assembly so the overall resistance matter of its polysilicon and silicide layer is lower because it reduces by a polysilicon layer than prior art.
Description of drawings
Figure 1A to Fig. 1 D is the generalized section of existing anti-fuse-type memory assembly polysilicon and metal silicide processing procedure;
Fig. 2 A to Fig. 2 D is anti-fuse-type memory assembly polysilicon and the metal silicide processing procedure generalized section of the utility model embodiment;
Fig. 3 is the stereogram of the metal silicide processing procedure of existing anti-fuse-type memory assembly polysilicon;
Fig. 4 is the stereogram of the metal silicide processing procedure of the anti-fuse-type memory assembly of the utility model polysilicon.
Symbol description:
Prior art:
100, the semiconductor-based end 110, bottom polysilicon layer 111, reaction polysilicon layer
119, titanium coating 120, titanium nitride layer 130, titanium-silicon compound layer
135, the first type conductive layer 136, antifuse layer 140, the second type conductive layer
The utility model technology:
200, semiconductor substrate 210, titanium nitride layer 212, titanium coating
220, reaction polysilicon layer 230, the first type conductive layer 240, titanium silicide layer
235, antifuse layer 250, the second type conductive layer
Embodiment
For technical problem of the present utility model, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
See also Fig. 2 A to Fig. 2 D, it is the processing procedure profile of the embodiment of the manufacture method of the anti-fuse-type memory assembly of the utility model simplification.In the narration of present embodiment, substrate comprises established assembly on the semiconductor crystal wafer, for example grid etc.
At first, shown in Fig. 2 A, semiconductor substrate 200 is provided, and dielectric layer has been formed on the semiconductor substrate 200 between plain conductor and lead thereof, its plain conductor can be copper metal or tungsten metal, and dielectric layer can be unadulterated silex glass between its lead, and tetraethoxysilane is silicon dioxide or other dielectric material in silicon source.Thereafter, deposition titanium nitride layer 210 and follow-up titanium coating 212, but titanium nitride applied chemistry vapour deposition process (CVD) or the mode of physical vaporous deposition (PVD) forms, titanium is Applied Physics vapour deposition process (PVD) deposition.The thickness of titanium nitride is the 25-250 dust, and it is as titanium-silicon compound and its bonding coat of plain conductor down, and the thickness of titanium is the 200-800 dust, its as after form the source of titanium-silicon compound.
Thereafter, deposit a undoped polysilicon layer or amorphous silicon layer as reacting polysilicon layer 220 on titanium coating 212, it uses a chemical vapour deposition technique (CVD), in reaction temperature at 450 ℃-800 ℃, reaction pressure is in the condition deposit of 0.1Torr-10Torr, thickness of its reaction polysilicon layer 220 is the 200-1500 dust, is as reacting to form follow-up titanium-silicon compound layer with its titanium coating 212 and part titanium nitride layer 210 down.Next, the deposition first type conductive layer 230 on the reaction polysilicon layer, it can be the polysilicon layer of doping P+, also be that applied chemistry vapour deposition process (CVD) forms, but this polysilicon layer is as conduction and form diode action, need the lower resistivity of tool, so by mixing to reduce the resistivity of itself, the impurity that is mixed is boron or other triad.And, can be after the chemical vapor deposition (CVD) reaction of its polysilicon, by a high-temperature diffusion method impurity become into, or after deposition, adopt the mode that ion is implanted, with impurity with the ion kenel, in the implanted polysilicon, or when the deposition reaction of polysilicon, (In-situ) carries out the infiltration of impurity simultaneously, and the first type conductive layer, 230 thickness of its formation are the 300-2000 dust.
Follow-up, shown in Fig. 2 B, with a hot processing procedure, it can be Fast Heating processing procedure or boiler tube processing procedure, in temperature is 400 ℃-1200 ℃, feed inert gas, so that titanium/titanium nitride layer 210 that forms before and reaction polysilicon layer 220 react to form titanium silicide layer 240, the titanium silicide layer 240 of its formation has low-resistance matter and heat-staple characteristic.
Thereafter, shown in Fig. 2 C, carry out a hot processing procedure, it can be Fast Heating processing procedure or boiler tube processing procedure, is 400 ℃-1200 ℃ in temperature, aerating oxygen, make the first type conductive layer surface produce silicon dioxide layer, its silicon dioxide layer thickness is the 5-200 dust, as the antifuse layer 235 of the anti-fuse-type memory assembly of control, so important suitable with inhomogeneity control of the quality of antifuse layer 235.
Then, the antifuse layer 235 that forms before the definition, the titanium-silicon compound layer 240 and the first type conductive layer 230 are to form character line, and it comprises that prior aries such as little shadow and etching do not encyclopaedize at this.In between lead, insert dielectric material after forming lead, it can be the formed silicon dioxide of chemical vapour deposition technique with a high-density electric slurry (HDP), it is dense that the electricity slurry that ion concentration in its electricity slurry is more general excites chemical vapour deposition technique, so can utilize the method for deposition/etching/deposition, have preferable ditch and fill out ability, can insert in the gap that forms behind the lead.Next, (CMP) removes unnecessary dielectric layer with chemical mechanical milling method, and makes its planarization.
Next, shown in Fig. 2 D, deposit the second type conductive layer 250 on antifuse layer 235, it can be the polysilicon layer of doping N+, be to use a chemical vapour deposition technique (CVD), at 450 ℃-800 ℃, reaction pressure is in the condition deposit of 0.1Torr-10Torr in reaction temperature, and its thickness is the 1000-6500 dust.The second type conductive layer forms diode action as conduction and with the first type conductive layer that forms before, so it also needs lower resistivity, and the impurity that it mixed is arsenic or other pentad.The method of its implantation, also be can by high-temperature diffusion method impurity become into, or in the mode that adopts ion to implant.Being noted that it is opposite with the first type conductive layer 230 that forms before that the kenel of the second type conductive layer 250 needs, and easily says it, can also be the P+ type at the polysilicon layer of this step deposition, and the polysilicon of deposition be the N+ type before.
Thereafter, define the second type conductive layer 250 to form bit line, it comprises light shield, develop, and etching.In between lead, insert dielectric material after forming lead, it also is the formed silicon dioxide of chemical vapour deposition technique with a high-density electric slurry (HDP), inserts in the gap that forms behind the lead, thereafter, (CMP) removes unnecessary dielectric layer with chemical mechanical milling method, and makes its planarization.
See also shown in Figure 4, it is the stereogram of the metal silicide processing procedure of the anti-fuse-type memory assembly of demonstration the utility model polysilicon, titanium silicide layer 240 is formed at semiconductor-based the end 200, itself and the first type conductive layer 230 as character line (WL) and the second type conductive layer 250 as bit line (BL).Wherein, there is titanium nitride layer 210 at 200 at the titanium silicide layer 240 and the semiconductor-based end as adhesive effect, and in the middle of the first type conductive layer 230 and the second type conductive layer 250 antifuse layer 235 arranged.
Therefore, the utility model reaches the overall resistance matter that reduces polysilicon and silicide layer by reducing by a polysilicon layer, and increases the drive current of anti-fuse-type memory assembly by this.In addition, because the anti-fuse-type memory assembly that the utility model provides reduces by a polysilicon layer than prior art, also can reach the purpose that reduces cost.
Though the utility model discloses as above with preferred embodiment; right its is not in order to limit the utility model; anyly have the knack of this skill person; in not breaking away from design of the present utility model and scope; when doing a little change and retouching, therefore protection range of the present utility model is as the criterion when looking claims person of defining.
Claims (12)
1. the structure of an anti-fuse-type memory assembly is characterized in that, comprising:
One metal silicide layer;
One first type conductive layer is on this metal silicide layer;
One antifuse layer is on this first type conductive layer; And
One second type conductive layer is on this antifuse layer.
2. the structure of anti-fuse-type memory assembly according to claim 1 is characterized in that, this first type conductive layer is that the P type and the second type conductive layer are the N types.
3. the structure of anti-fuse-type memory assembly according to claim 1 is characterized in that, this first type conductive layer is that the N type and the second type conductive layer are the P types.
4. the structure of anti-fuse-type memory assembly according to claim 1 is characterized in that, this metal silicide layer is a titanium-silicon compound, cobalt and silicon compound, or the nisiloy compound is formed.
5. the structure of anti-fuse-type memory assembly according to claim 1 is characterized in that, this antifuse layer is silicon dioxide or silicon nitride.
6. the structure of an anti-fuse-type memory assembly is characterized in that, comprising:
One first lead;
One bonding coat is positioned on this first lead;
One metal silicide layer is positioned on this bonding coat;
One first type conductive layer is positioned on this first lead;
One antifuse layer is positioned on this first type conductive layer; And
One second type conductive layer is positioned under one second lead, this first lead and second lead are orthogonal, and the antifuse layer in the middle of this first type conductive layer and this second type conductive layer is a square type zone, and only when this antifuse layer bursts apart the first type conductive layer and the second type conductive layer just can form diode.
7. the structure of anti-fuse-type memory assembly according to claim 6 is characterized in that, this first lead and second lead are that tungsten, aluminium or copper constitute.
8. the structure of anti-fuse-type memory assembly according to claim 6 is characterized in that, this metal silicide layer is a titanium-silicon compound, cobalt and silicon compound, or the nisiloy compound is formed.
9. the structure of anti-fuse-type memory assembly according to claim 6 is characterized in that, this first type conductive layer and the second type conductive layer are P type or N type.
10. the structure of anti-fuse-type memory assembly according to claim 6 is characterized in that, kenel is different each other with the second type conductive layer for this first type conductive layer.
11. the structure of anti-fuse-type memory assembly according to claim 6 is characterized in that, this antifuse layer is silicon dioxide or silicon nitride.
12. the structure of anti-fuse-type memory assembly according to claim 6 is characterized in that, this bonding coat is the nitride of titanium, the nitride of cobalt or the nitride of nickel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420067254 CN2741188Y (en) | 2003-07-22 | 2004-06-18 | Structure of reverse-fuse memory assembly |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN03146105 | 2003-07-22 | ||
| CN03146105.0 | 2003-07-22 | ||
| CN 200420067254 CN2741188Y (en) | 2003-07-22 | 2004-06-18 | Structure of reverse-fuse memory assembly |
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| CN2741188Y true CN2741188Y (en) | 2005-11-16 |
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| CN 200420067254 Expired - Lifetime CN2741188Y (en) | 2003-07-22 | 2004-06-18 | Structure of reverse-fuse memory assembly |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1320633C (en) * | 2003-07-22 | 2007-06-06 | 台湾积体电路制造股份有限公司 | Structure and producing method of back-fuse type memory assembly |
| CN102646681A (en) * | 2006-10-04 | 2012-08-22 | 株式会社半导体能源研究所 | Semiconductor device |
| CN101752002B (en) * | 2008-12-11 | 2013-09-18 | 旺宏电子股份有限公司 | Aluminum copper oxide based memory devices and methods for manufacture |
-
2004
- 2004-06-18 CN CN 200420067254 patent/CN2741188Y/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1320633C (en) * | 2003-07-22 | 2007-06-06 | 台湾积体电路制造股份有限公司 | Structure and producing method of back-fuse type memory assembly |
| CN102646681A (en) * | 2006-10-04 | 2012-08-22 | 株式会社半导体能源研究所 | Semiconductor device |
| CN102646681B (en) * | 2006-10-04 | 2015-08-05 | 株式会社半导体能源研究所 | Semiconductor device |
| CN101752002B (en) * | 2008-12-11 | 2013-09-18 | 旺宏电子股份有限公司 | Aluminum copper oxide based memory devices and methods for manufacture |
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| GR01 | Patent grant | ||
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| CX01 | Expiry of patent term |
Expiration termination date: 20140618 Granted publication date: 20051116 |