CN1650443A - Utilizing atomic layer deposition for programmable device - Google Patents

Utilizing atomic layer deposition for programmable device Download PDF

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Publication number
CN1650443A
CN1650443A CN02829486.6A CN02829486A CN1650443A CN 1650443 A CN1650443 A CN 1650443A CN 02829486 A CN02829486 A CN 02829486A CN 1650443 A CN1650443 A CN 1650443A
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electrode
ald
programmable material
nitride
dielectric
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T·A·劳里
C·H·丹尼森
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Ovonyx Inc
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Ovonyx Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/884—Switching materials based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes

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  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In an aspect, an apparatus is provided that sets and reprograms the state of programmable device. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programkmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.

Description

Use ald for programming device
The field
The programming device that comprises phase change memory device can be programmed by the state that changes phase-change material.
Background
Typical computer or the device (comprise physical storage) relevant with computer, so-called is main storage or random access storage device (RAM).Usually, RAM is the operable memory of computer program, and read-only memory (ROM) is to be used for for example storing the memory that starts computer and carry out the program of diagnosis.Typical memory application comprises dynamic RAM (DRAM), static random-access memory (SRAM), Erasable Programmable Read Only Memory EPROM (EPROM) and Electrically Erasable Read Only Memory (EEPROM).
Solid-state memory typically uses microelectronic circuit component for each bank bit (for example, every is 1-4 transistor) in memory application.Because need one or more electronic circuit component for each bank bit, these devices may consume a large amount of chips " area " (real estate) and come store bits of information, have limited the density of memory chip like this.Original " non-volatile " memory element of these devices such as EEPROM, typically uses to have the floating gate fet device of limited reprogramming ability and keep electric charge to store each bank bit on the grid of field-effect transistor.This class memory device is relatively slow for programming.
Phase change memory device uses phase-change material (i.e. the material that TURP changes between common amorphous state and common crystalline state) to be used for the application of electronic memory.One type memory element is by Troy at first, the Energy Conversion Devices of Michigan, the Inc exploitation, this memory element uses a kind of phase-change material, but this phase-change material can common amorphous configuration state and usually between the configuration state of crystalline state local order TURP change or crossing over complete amorphous state and fully between the crystalline state between the difference detected state of the local order of gamut TURP change.The typical material that is suitable for this application comprises the material that those use various chalkogenide elements.These electrical storage devices typically do not use FET device as memory storage element, still, but comprise the monomer of film chalcogenide material in electrical application.Finally, need very little chip area to come store bits of information, thereby intrinsic high density memory chips is provided.It is still really non-volatile that state changes material, reason is when being arranged on the crystalline state of representing resistance value, half hitch crystalline state, amorphous state, half amorphous state, this value remains unchanged up to the value that has been reprogrammed to representative the physical state of material (for example, crystalline state or amorphous state).Like this, phase-change storage material has been represented sizable improvement of nonvolatile storage.
For solid-state and total characteristic of phase change memory device be, especially the sizable power consumption when setting or reprogramming memory element.Power consumption is important factor, is very important in the mancarried device that depends on battery (for example, storage battery) power supply especially.The power consumption that reduces memory device is desirable.
Solid-state and another total characteristic phase change memory device be from/to the limited re-programmable cycle life of amorphous state and crystalline state.In addition, as time goes by, phase-change material can not be reliably from/to amorphous state and crystalline state reprogramming.The programmable cycle life that increases phase-change storage material is desirable.
Description of drawings
By reading following detailed description and with reference to the accompanying drawings, advantage of the present invention will become apparent.
Fig. 1 is the schematic diagram of an embodiment of memory element array;
Fig. 2 schematically illustrates the cross-sectional plan view of the part of Semiconductor substrate, and according to an embodiment who forms memory element on substrate, this Semiconductor substrate has the dielectric raceway groove of the z direction thickness of the qualification memory cell that forms therein;
Fig. 3 is described in the structure of introducing after the isolating device that dopant forms memory element, passing Fig. 2 of same cross sectional view;
Fig. 4 describes the structure of the Fig. 3 that forms raceway groove;
Fig. 5 describes the schematic top view of Fig. 4 structure;
Fig. 6 is described in the sectional view that forms contact Fig. 4 structure afterwards;
Fig. 7 is described in the structure that forms after mask material and the dielectric substance, passes Fig. 6 of same cross sectional view;
Fig. 8 is described in the structure that forms after the opening, passes the Fig. 7 in same cross section by the dielectric that exposes this contact;
Fig. 9 describes the structure of using ALD to create electrode individual layer (monolayer) on dielectric and contact, pass Fig. 8 of same cross sectional view is shown;
Figure 10 despise on dielectric and contact, be conformally formed electrode after, the structure of passing Fig. 9 of same cross sectional view;
The structure that Figure 11 is described in after the horizontal component that forms dielectric in the opening and remove electrode, passes Figure 10 of same cross sectional view;
After Figure 12 describes and uses ALD to be conformally formed on electrode to stop, the structure of passing Figure 11 of same cross sectional view;
Figure 13 be described in form and patterning (pattern) programmable material, stop with conductor after, the structure of passing Figure 12 of same cross sectional view;
The structure that Figure 14 is described in and forms dielectric on the conductor, form through hole and form after the holding wire on this dielectric, pass Figure 13 of same cross sectional view;
Figure 15 describes to form has the method for the memory device that is similar to structure shown in Figure 14; And
Figure 16 describes and comprises a system embodiment with the memory that is similar to structure shown in Figure 14.
Describe in detail
With reference to customized configuration exemplary embodiment is described.One skilled in the art will appreciate that within the scope of the appended claims and can make various modifications and variations.In addition, in order to make the present invention simpler and clearer, omitted detailed description for known elements, device, parts, circuit, processing step etc.
Described and used programmable material to determine the memory device of the storage element states of device, this memory device is reprogrammed to amorphous state and crystalline state.Described memory device and method be with respect to existing device, the power consumption that improved device reliability, improved programmable cycle life is provided and has reduced.In addition, in one embodiment, use conventional technology tool set and facility can make this equipment.
In one embodiment, ald (ALD) provides electrode assembly constructional advantage, comprises reducing being used for the required program current of memory device replacement, setting and read operation.By using ALD or atomic layer chemical vapor deposition (ALCVD) to replace the chemical vapor deposition (CVD) technology, provide electrode assembly constructional advantage, comprise the ability of the film that deposition is extremely thin and conformal.This film thickness is that the quantity of passing through the deposition step that applied controls, and its resolution is limited by the thickness of an individual layer.In addition, the ALD deposition provides the uniformity and the accuracy of large area film.
The schematic diagram of an embodiment of the memory array that constitutes according to a plurality of memory elements that provide and form in the context of this explanation is provided Fig. 1.In this example, the circuit of memory array 5 comprises the xy grid, and it has the memory element 30 of isolating device 25 series electrical interconnection on the part with chip.In one embodiment, address wire 10 (for example row) and 20 (for example going) are connected to the outside addressing circuit in a usual manner.A purpose of the xy grid array of the memory element that combines with isolating device is, makes each discrete memory element be read out and write there not be interference to be stored under the situation of the vicinity of array or the information in the remote storage element.
Can be formed on such as the memory array of the memory device 5 of Fig. 1 in the part of substrate (comprising entire portion).Typical substrate comprises the Semiconductor substrate such as silicon substrate.Other include but not limited to contain ceramic material, organic material or also are fit to as the substrate of the glass material of part infrastructure.Under the situation of silicon semiconductor substrate, can be in the memory array on the wafer-level fabrication area 5, and become discrete tube core or chip to reduce this wafer by this wafer being cut apart (singulation) then, tube core or chip have formation memory array thereon partly or completely.As known to the skilled person, can form additional addressing circuit (for example decoder etc.).
Fig. 2-14 has described an embodiment of the representative memory element 15 of construction drawing 1.Fig. 2 has described the part of substrate 100, for example semiconductor (for example silicon) substrate.In this example, the P type dopant of introducing such as boron in part 110.In an example, the debita spissitudo of P type dopant is about 5 * 10 19-1 * 10 20Every cubic centimetre of (atoms/cm of atom 3) magnitude, make the part 110 of substrate 100 become P ++In this example, the part 110 of covering substrate 100 is P type epitaxial silicon part 120.In an example, the concentration of dopant is about 10 16-10 17Atoms/cm 3Magnitude.
Fig. 2 has also described latent channel isolation (STI) structure 130 that forms in the epitaxial part 120 of substrate 100.As conspicuous in discussion subsequently, sti structure 130 is used to limit the z direction thickness of memory cell on the one hand, only limits the thickness of the z direction of memory cell in this.In one embodiment, memory cell z direction zone 135A and 135B are patterned as bar shaped, and x direction size is greater than z direction size.On the other hand, sti structure 130 is used for the single memory element that is formed on substrate and the substrate is isolated mutually and isolated mutually with relevant circuit element (for example, transistor device).The current existing photoetching technique that is used for the patterning sti structure limits the z direction thickness of memory cell region 135A and 135B, can produce and 0.18 micron (μ m) the same little characteristic size (z direction thickness).
Fig. 3 has described and carried out the structure that other make operation Fig. 2 afterwards in memory cell region 135A and 135B.In each memory cell region (bar shaped), cover substrate 100 epitaxial part 120 be signal line material 140.In an example, signal line material 140 is to be approximately 10 by for example introducing concentration 18-10 19Atoms/cm 3The phosphorus of magnitude or arsenic and polysilicon (for example, N that the N type that forms mixes +Silicon).In this example, signal line material 140 is as address wire, line (for example, the line among Fig. 1 20).What cover signal line material 140 is isolating device (for example isolating device among Fig. 1 25).In an example, isolating device is that (for example concentration of dopant is approximately 10 by N type silicon part 150 14-10 18Atoms/cm 3Magnitude) and P type silicon part 160 (for example concentration of dopant is approximately 10 19-10 20Atoms/cm 3Magnitude) the PN diode that forms.Although what illustrate is the PN diode, should be understood that other isolation structures also are fit to.Such device includes, but are not limited to metal-oxide semiconductor (MOS) (MOS) device.
Fig. 4 shows in the epitaxial part 120 of substrate 100 and to form after the raceway groove 190, from the structure of Fig. 3 of xy direction perspective.In this example, raceway groove 190 is perpendicular to sti structure 130 formation.Raceway groove 190 limits the x direction thickness of memory cell.According to current photoetching technique, the suitable characteristic size of x direction thickness is the same little with 0.25 μ m.Fig. 4 also describes memory cell 145A and the 145B that is separated by raceway groove 190, and its z direction thickness is limited by sti structure 130, and x direction thickness is limited by raceway groove 190.In one embodiment, the qualification of the x direction thickness etching that relates to conductor that memory lines is piled up or holding wire 140 limits memory cell 145A and the 145B of memory cell region 135A.In this example, under etched situation, etching is passed memory lines and is piled up a part up to conductor or holding wire 140.Can use regularly etching to stop etching in this point.After patterning, between memory cell 145A and 145B, introduce concentration of dopant at the base portion of each raceway groove 190 and be approximately 10 18-10 20Atoms/cm 3The N type dopant of magnitude (N for example +The zone) forms bag (pocket) 200.
After introducing bag 200, the dielectric substance of introducing such as silicon dioxide in raceway groove 190 forms sti structure 132.Then, for example use chemico-mechanical polishing with upper surface (as seeing) planarization.Fig. 5 has described the xy perspective view of Fig. 4 structure, and this structure has by sti structure 130 and the memory cell (for example memory cell 145A and 145B) opened in 132 minutes.
Fig. 6 describes in this example, forms such as cobalt silicide (CoSi in the part of P type silicon part 160 2) the refractory metal silicide material limit the structure (that is xy direction perspective) of the Fig. 4 after the contact 170.On the one hand, contact 170 is used as low electrical resistant material in the peripheral circuit (for example, addressing circuit) of making the circuit structure on the chip.
Fig. 7 has described the structure of the Fig. 6 after introducing mask material 180.As subsequently will be more clearly, in some sense, mask material 180 stops as the etching with post-etch operations.In one embodiment, the suitable material that is used for mask material 180 is such as silicon nitride (Si 3N 4) dielectric substance.
It is the dielectric substance 210 of about 100 -50,000 magnitude that Fig. 7 also describes structurally the thickness that being enough to of introducing cover memory cell 145A and 145B.In one embodiment, dielectric substance 210 is SiO 2In another embodiment, dielectric substance 210 is materials of selecting according to its thermal conductivity κ that reduces, and preferably its thermal conductivity is less than κ SiO2, more preferably less than κ SiO23-10 doubly.As is generally known, SiO 2And Si 3N 4The κ value be magnitude 1.0.Like this, except SiO 2Outside, the material that is suitable for dielectric substance 210 comprises that those κ values are less than 1.0 material.Some κ value comprises carbide material, aeroge, xerogel (κ is in 0.1 magnitude) and their derivative less than 1.0 high temperature polymer.
Fig. 8 is described in by dielectric 210 and mask material 180 and forms after openings 220, the exposed contact 170, the structure of passing Fig. 7 of same cross sectional view.Use to etching dielectric substance 210 and mask material 180 but not the etchant selected of contact 170 (for example, contact 170 stops as etching) come etched patternization can form opening 220.
Fig. 9 describes the structure of using ALD to be conformally formed electrode material 230, to pass Fig. 8 of same cross sectional view.Use ALD, once introduce a kind of reacting gas.First gas quilt " chemical absorbing " is to the surface of the dielectric 210, mask material 180 and the contact 170 that form chemical absorbing layer 230A.Remove superfluous gas then and introduce second gas.This gas and chemical absorbing layer 230A reaction, the deposited film 230B of generation individual layer.In gas phase, do not have in a sequential manner single predecessor to be pulsed to the surface under the situation of mixed precursor (precursor).Predecessor that each is single and surface reaction form atomic layer in the mode that once forms one deck.This ALD technology is from restriction.That is, surface reaction takes place and finishes to make primary depositing be no more than one deck, and no matter in the overtreatment pattern, be applied to the quantity of lip-deep molecule.Thereby form film by in circulation, introducing short burst gas.Conventional CVD technology is operated in more than 500 ℃ typically, and ALD might be lower than below 400 ℃, makes that its industry trends with low temperature is compatible mutually.
Thin sidewall film limits the x shaft size (as will become more obvious in Figure 11) of electrode, and the x shaft size is important size with regard to device performance.The x shaft size has been determined to be used to reset, setting and the required program current of read operation.The x shaft size that can repeat to produce is more little, and the needed required program current of operated device is more little.This is because its phase (phase) is just less at the volume of reformed programmable material, and thermal loss reduces and to cause.
In one embodiment, electrode material 230 (summarized 230A, 230B ..., the 230N atomic layer) have uniform film thickness, ultrathin (with respect to the x shaft size of describing among Figure 11), and be conformal film.In one embodiment, electrode material 230 has the x shaft size of 10 dusts to 1000 dust magnitudes.In one embodiment, electrode material 230 be in tungsten (W), tungsten nitride (WN), titanium nitride (TiN), titanium silicon nitride (TiSiN) and the tantalum nitride (TaN) at least one of them.In one embodiment, electrode material 230 has the resistivity of 0.001-0.05ohm-cm magnitude.
Figure 10 is described in and finishes the structure that is conformally formed electrode material 230 Fig. 9 afterwards.This introducing is conformal in some sense, and electrode material 230 is along (the showing electrode material part 230A, 230B and 230C) of the sidewall of opening 220 and base portion formation, makes electrode material 230 contact with contact 170.Can realize the isolation of single conductive path (such as electrode material 230A) by introduce dopant (angle deviating electrode material 230B) angledly.
Figure 11 is illustrated in and introduces dielectric substance 250 structure afterwards in the opening 220.In one embodiment, dielectric substance 250 is silicon dioxide (SiO 2).In another embodiment, dielectric substance 250 is that its thermal conductivity κ is less than SiO 2Thermal conductivity κ SiO2Material, preferably its thermal conductivity is less than κ SiO210 times.After introducing, this structure is carried out planarization to remove the horizontal part of electrode material 230.Suitable planarization comprises known for those skilled in the art those technology, such as chemistry or chemico-mechanical polishing (CMP) technology.
Figure 12 is described in the structure of using the randomly conformal formation of ALD to stop after 275, pass Figure 11 of same cross sectional view.In one embodiment, electrode 230 is selective etch, use to stop that 275 ALD fills etched zone, and then to stopping that 275 carry out planarization.
Figure 13 be described in form and patterned conductor 410, stop 408 and programmable material 404 after, the structure of passing Figure 12 of same cross sectional view.Use conventional photoetching and etching technique can realize this patterning.In this example, except stop 275, dielectric 210 and the dielectric 250, etching passes programmable material 404, stop 408 and the part of conductor 410.In one embodiment, programmable material 404 is phase-change materials, and this phase-change material has the character that can change its physical state (for example crystalline state and amorphous state) under the situation of using energy (for example, electric energy, heat energy).Be well known that the chalcogenide material with general formula is suitable for this situation.In one embodiment, the chalcogenide alloy that is suitable as programmable material 404 comprises at least one element in the VI family of the periodic table of elements.In one embodiment, Ge 2Sb 2Te 5As programmable material 404.Other chalcogenide alloys as programmable material 404 comprise GaSb, InSb, InSe, Sb 2Te 3, GeTe, InSbTe, GaSeTe, SnSb 2Te 4, InSbGe, AgInSbTe, (GeSn) SbTe, GeSb (SeTe) and Te 81Ge 15Sb 2S 2
Stop that 408 comprise a kind of in for example titanium (Ti) and titanium nitride (TiN).Stop the diffusion between the 408 secondary signal wire materials (for example, second electrode 10) that are used on the one hand be suppressed at the volume of programmable material 404 and cover programmable material 404 volumes.Covering stop 408 be signal line material 410.In this example, signal line material 410 is as address wire, alignment (for example, the alignment 10 of Fig. 1).In one embodiment, signal line material 410 is patterned as usually perpendicular to signal line material 140 (alignment is perpendicular to line).Signal line material 410 is for example such as the aluminum of aluminium alloy.Be used to introduce with patterning stop 408 and the method for signal line material 410 comprise the technology of well known to a person skilled in the art.
Figure 14 is illustrated in the structure that forms dielectric substance 412 Figure 13 afterwards on the conductor 410.Dielectric substance 412 is the SiO that for example are formed on electric isolation conductor 410 on the conductor 410 2Perhaps other materials that are fit to.After forming, in the part of this structure, form through hole up to contact 170 with dielectric substance 412 planarizations and by dielectric substance 412, dielectric substance 210 and dielectric substance 180.This through hole is filled with such as the electric conducting material 340 of tungsten (W) with such as the barrier material 350 of titanium (Ti) and titanium nitride (TiN) combination.The technology that is used to introduce dielectric substance 412, formation and filled conductive through hole and planarization all is known for those skilled in the art.Structure shown in Figure 14 also shows additional signals wire material 414, and this signal line material 414 is formed with patterning and is formed on signal line material 140 (for example line) on the substrate 100 with mapping (mirror).Mirror conductor line material 414 mapping signal wire materials 140 and be coupled to signal line material 140 by conductive through hole.By mapping such as the doped semiconductor of N type silicon, on the one hand, mirror conductor line material 414 is used for reducing the resistance of signal line material 140 of the memory array of all memory arrays as shown in Figure 15.The material that is fit to that is used for mirror conductor line material 414 comprises the aluminum such as aluminium alloy.
According to an embodiment, Figure 15 describes the method that forms programmable storage device, and this device has and is similar to structure shown in Figure 14.
In addition, as shown in figure 16, can comprise that in the system that is fit to single memory cell has the structure that is similar to reference to shown in Figure 14 in this memory array such as the memory array of memory device 5 (Fig. 1) and the text of following.In one embodiment, system 700 comprises microprocessor 704, I/O (I/O) port 706 and memory 702.Microprocessor 704, I/O port 706 and memory 702 connect by data/address bus 712, address bus 716 and control bus 714.Microprocessor 704 is by sending the address and sending the memory read number of winning the confidence on control bus 714 to take out instruction or reading of data from memory 702 on the address bus 716.Memory 702 is exported the instruction or the data word of addressing to microprocessor 704 on data/address bus 712.By sending the address on the address bus 716, sending data word on the data/address bus 712 and write signal to memory 702 transmission memories on control bus 714, microprocessor 704 writes data word to memory 702.I/O port 706 be used for being coupled to input unit 708 and output device 710 at least one of them.
Disclose exemplary embodiment, in remaining on the spirit and scope of the present invention that appended claims limits, can make amendment and modification disclosed embodiment.

Claims (15)

1. method comprises:
Form dielectric on the contact, described contact is formed on the substrate;
Form opening by the described dielectric that exposes described contact;
Use ald (ALD) depositing electrode conformally on described dielectric wall;
On described electrode, form programmable material; And
Be formed into the conductor of described programmable material.
2. according to the method for claim 1, also comprise:
Between described electrode and programmable material, use the ALD deposition to stop, described stop comprise in titanium silicide and the titanium nitride at least one of them.
3. according to the process of claim 1 wherein that conformally depositing electrode comprises the electrode film thickness that conformally deposits from 10 dusts to 1000 dusts.
4. according to the method for claim 1, wherein conformally depositing electrode comprise in conformally deposits tungsten (W), tungsten nitride (WN), titanium nitride (TiN), titanium silicon nitride (TiSiN) and the tantalum nitride (TaN) at least one of them, have the resistivity of 0.001ohm-cm to 0.05ohm-cm.
5. according to the process of claim 1 wherein that forming programmable material comprises formation chalkogenide memory element.
6. equipment comprises:
Be positioned at the contact on the substrate;
Be positioned at the dielectric on the described contact, described dielectric has the opening that exposes described contact;
By ald (ALD) on described dielectric wall conformally the deposition electrode;
Be positioned at the programmable material on the described electrode; And
Be formed into the conductor of described programmable material.
7. according to the equipment of claim 6, also comprise:
Between described electrode and programmable material, stop by ALD deposition, described stop comprise in titanium silicide and the titanium nitride at least one of them.
8. according to the equipment of claim 6, wherein said electrode has the film thickness from 10 dusts to 1000 dusts.
9. according to the equipment of claim 6, wherein said electrode has the resistivity from 0.001ohm-cm to 0.05ohm-cm, and described electrode comprise in tungsten (W), tungsten nitride (WN), titanium nitride (TiN), titanium silicon nitride (TiSiN) and the tantalum nitride (TaN) at least one of them.
10. according to the equipment of claim 6, wherein said programmable material comprises the chalkogenide memory element.
11. a system comprises:
Microprocessor;
I/O (I/O) port; And
Memory, comprise contact that is positioned on the substrate and the dielectric that is positioned on the described contact, described dielectric has the opening that exposes described contact, by ald (ALD) on described dielectric wall conformally the deposition electrode, be positioned at the programmable material on the described electrode, and the conductor that is formed into described programmable material; And
Wherein said microprocessor, I/O port and memory connect by data/address bus, address bus and control bus.
12. the system according to claim 11 also comprises:
Between described electrode and programmable material, stop by ALD deposition, described stop comprise in titanium silicide and the titanium nitride at least one of them.
13. according to the system of claim 11, wherein said electrode has the film thickness from 10 dusts to 1000 dusts.
14. system according to claim 11, wherein said electrode has the resistivity from 0.001ohm-cm to 0.05ohm-cm, and described electrode comprise in tungsten (W), tungsten nitride (WN), titanium nitride (TiN), titanium silicon nitride (TiSiN) and the tantalum nitride (TaN) at least one of them.
15. according to the system of claim 11, wherein said programmable material comprises the chalkogenide memory element.
CN02829486.6A 2002-08-21 2002-08-21 Utilizing atomic layer deposition for programmable device Pending CN1650443A (en)

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