CN2545706Y - Sheet type miniature bridge stack - Google Patents
Sheet type miniature bridge stack Download PDFInfo
- Publication number
- CN2545706Y CN2545706Y CN02219702U CN02219702U CN2545706Y CN 2545706 Y CN2545706 Y CN 2545706Y CN 02219702 U CN02219702 U CN 02219702U CN 02219702 U CN02219702 U CN 02219702U CN 2545706 Y CN2545706 Y CN 2545706Y
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- Prior art keywords
- junction
- chip
- chips
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 238000000034 method Methods 0.000 claims abstract description 11
- 238000004806 packaging method and process Methods 0.000 claims abstract description 7
- 229910000679 solder Inorganic materials 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229920002379 silicone rubber Polymers 0.000 claims description 2
- 238000012797 qualification Methods 0.000 abstract description 2
- 238000003466 welding Methods 0.000 description 15
- 230000004907 flux Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Rectifiers (AREA)
Abstract
The utility model provides a sheet type miniature bridge. A bridge rectifier is formed by four rectifier diodes in a packaging body. The four rectifier diodes consist of four same PN junction chips which are a D1, a D2, a D3 and a D4. Two of the four PN junction chips are juxtaposed on the top and the other two of the four PN junction chips are juxtaposed at the bottom. The P-area and the N-area of each PN junction chip are arranged from top to bottom. The P-area and the N-area of the angular position PN junction chip are arranged in the same position. Two overlapped PN junction chips are connected with each other by a connection lug. The two PN junction chips which are juxtaposed on the top and the other two PN junction chips which are juxtaposed at the bottom are respectively connected by another connection lug. Two connection lugs in a middle layer are regarded as a group of electrode terminal. Two connection lugs in an upper layer and in a lower layer are regarded as another group of electrode terminal and are respectively fetched out from the packaging body, so a miniature five-layer rectifier bridge structure is formed. The utility model is characterized in that the bulk is small; only one chip is needed, so the uniformity of variety is good; the process is simple; the cost is low and the qualification rate is high. The utility model has much better market potential.
Description
Technical Field
The utility model relates to a bridge rectifier, concretely relates to adopt four chips to press miniature semiconductor rectifier bridge piles that single-phase bridge rectifier circuit connects.
Background
With the progress of science and technology, bridge rectifiers are being developed toward miniaturization as electronic components. Much research and research has been done in this regard. China specially for 1998, 11.4.A patent application with patent application number 97104255.1 and publication number CN1197989A, entitled "micro semiconductor bridge rectifier and manufacturing method thereof", is disclosed. The patent application discloses a micro semiconductor bridge rectifier, which specifically includes a common N-type dual diode die and a common P-type dual diode die, wherein a P-type region of the common N-type die and a corresponding N-type region of the common P-type die are connected to a terminal electrode of a first group of lead frames, another P-type region of the common N-type die and another N-type region of the common P-type die are connected to another terminal electrode of the first group of lead frames, and the N-type region of the common N-type die and the P-type region of the common P-type die are respectively connected to two terminal electrodes of a second group of lead frames, thereby forming a bridge rectifier. Although the micro rectifier is advantageous to miniaturization in structure, two kinds of double-diode chips, namely a common N-type double-diode chip and a common P-type double-diode chip, are required to be used for manufacturing. Therefore, the disadvantages that come with are: 1. the core chip has multiple unit varieties and increased process complexity. 2. The chip yield is relatively low. 3. The uniformity of two chip varieties is poor. 4. The chip of the P-type substrate is relatively difficult to make. Therefore, the utility model discloses from the angle that adopts four same variety chips, designed a small, simple structure's miniature semiconductor rectifier bridge rectifier to overcome above-mentioned not enough.
Disclosure of Invention
In order to achieve the above purpose, the utility model adopts the technical scheme that: a chip type miniature bridge stack is characterized in that a bridge rectifier is formed by four rectifier diodes in a packaging body, the four rectifier diodes are formed by the same PN junction chips D1, D2, D3 and D4, two of the four PN junction chips are arranged in parallel at the upper part and the other two of the four PN junction chips are arranged at the lower part in parallel in space, a P-type region and an N-type region of each PN junction chip are arranged up and down, the P-type region and the N-type region of the PN junction chip at the diagonal position are in the same direction, the two superposed PN junction chips are connected through a connecting sheet respectively, the two superposed PN junction chips are connected through another connecting sheet respectively, two connecting sheets on the middle layer are used as a group of electrode terminals, and two connecting sheets on the upper layer and the lower layer are used as another group of electrode terminals and are respectively led out of the packaging body, so that a space-contracted laminated bridge stack structure is.
The content and structural changes in the above technical solution are explained as follows:
1. the same PN junction chip refers to chips with the same variety, specification and performance. The upper, lower, left and right aspects of the present invention are described with reference to the orientation in the drawings provided, and if the drawing direction is rotated, the upper, lower, left and right aspects should be changed and explained accordingly. The present solution is therefore described with reference to the orientation of the figures, on the one hand for easy understanding with respect to the figures and, on the other hand, for accurate representation of the spatial structure and its connections. The "two connecting pieces on the intermediate layer" refer to a connecting piece between an upper PN junction chip and a lower PN junction chip, and the "two connecting pieces on the upper layer and the lower layer" refer to a connecting piece for connecting the two PN junction chips which are arranged in parallel up and down.
2. Among the above-mentioned technical scheme, according to bridge rectifier circuit principle, four PN junction chips can arrange into two kinds of forms, four schemes according to P type district and N type district position:
(1) the first form is: the P-type region and the N-type region of the four PN junction chips have the same direction in space. Wherein,
the first scheme is as follows: as shown in FIG. 4, the P-type region of four PN junction chips is on the top, and the N-type region is on the bottom. At this time, the two connecting sheets in the middle are alternating current input ends, the upper connecting sheet is a direct current output cathode, and the lower connecting sheet is a direct current output anode.
Scheme II: as shown in FIG. 5, the N-type region of four PN junction chips is on the top, and the P-type region is on the bottom. At this time, the two connecting sheets in the middle are alternating current input ends, and the polarities of the upper connecting sheet and the lower connecting sheet are opposite to that of the first scheme.
(2) The second form is: the P-type region and the N-type region of the PN junction chip at different diagonal positions are opposite in orientation in space. Wherein,
the third scheme is as follows: as shown in fig. 6, the P-type regions of the PN junction chips at the upper left and lower right are on the top, and the N-type regions are on the bottom; the PN junction chips at the left lower part and the right upper part have the N-type area at the upper part and the P-type area at the lower part. At the moment, the upper connecting sheet and the lower connecting sheet are alternating current input ends, the connecting sheet on the left side in the middle is a direct current output anode, and the connecting sheet on the right side is a direct current output cathode.
And the scheme is as follows: as shown in fig. 7, the N-type regions of the PN junction chips at the upper left and the lower right are on the top, and the P-type regions are on the bottom; the P type area of the PN junction chip at the lower left and the upper right is arranged at the upper part, and the N type area is arranged at the lower part. At this time, the upper and lower connecting sheets are AC input ends, and the polarity of the middle two connecting sheets is opposite to that of the third scheme.
3. In the above technical solution, each connecting piece and the PN junction chip are connected by solder for connection.
4. In the technical scheme, the PN junction chip can adopt a square structure, a round structure and even other shapes.
5. In the above technical solution, the passivation layer on the PN junction chip may be a glass or silicon dioxide passivation layer, or a silicon rubber passivation layer.
The utility model discloses the technical core is: four identical PN junction chips and four connecting sheets are spatially superposed to form a miniature five-layer bridge stack structure.
Because of the application of the technical scheme, compared with the prior art, the utility model has the following advantages:
1. the utility model discloses a four the same PN junction chips connect into miniature five-layer bridge heap structure with the connection piece, and its body volume only is: 4.7X 3.8X 2.5mm3. The invented method overcomes the prejudice of the prior art-CN 1197989A patent application, and only the conventional bridge rectifier manufacturing method must connect four silicon diodes with electrodes for packaging, so that the volume of the bridge rectifier can not be reduced to be small, and the bridge rectifier can not meet the requirement of electronic products, and the manufacturing process is complex, and the yield is not easy to be increased.
2. The utility model discloses the variety of chip only needs one, and the homogeneity improves greatly.
3. The utility model discloses the chip qualification rate is higher relatively.
4. When the utility model discloses a N type substrate chip does not have the chip of P type substrate, can reduce the technology degree of difficulty from manufacturing.
Drawings
FIG. 1 is a perspective view of an embodiment of a micro rectifier bridge stack according to the present invention;
FIG. 2 is a diagram of a diode bridge rectifier circuit;
FIG. 3 is a schematic structural diagram of an embodiment of the micro rectifier bridge stack of the present invention;
FIG. 4 is a schematic diagram of a first embodiment of the present invention;
FIG. 5 is a schematic diagram of a second embodiment of the present invention;
FIG. 6 is a schematic diagram of a third embodiment of the present invention;
fig. 7 is a schematic diagram of a fourth embodiment of the present invention.
In the above drawings: 1. a P connecting sheet; 2. welding flux; 3. welding flux; 4. a lead sheet; 5. welding flux; 6. welding flux; 7. an epoxy resin; 8. n connecting sheets; 9. welding flux; 10. welding flux; 11. a lead sheet; 12. welding flux; 13. welding flux; D1-D4 are four PN junction chips.
Detailed Description
The invention will be further described with reference to the following drawings and examples:
example (b): referring to fig. 1 and 3, a chip-type silicon diffusion micro rectifier bridge stack is provided, in which a bridge rectifier is formed by four rectifier diodes composed of identical PN junction chips D1, D2, D3 and D4 in a package. The PN junction chips D4 and D2 are juxtaposed in space above and D3 and D1 are juxtaposed below. The P type regions of the four PN junction chips D1, D2, D3 and D4 are arranged above the N type regions. A connecting piece is placed between D4 and D3 and is a lead piece 4, another connecting piece is placed between D2 and D1 and is a lead piece 11, the upper end faces of D4 and D2 are connected through a P connecting piece 1, and the lower end faces of D3 and D1 are connected through an N connecting piece 8. Each connecting sheet is connected with the PN junction chip through welding flux, and the method specifically comprises the following steps: the P connecting piece 1 is connected with the D4 and the D2 by the solder 2 and the solder 13 respectively, the N connecting piece 8 is connected with the D3 and the D1 by the solder 6 and the solder 9 respectively, the lead piece 4 is connected with the D4 and the D3 by the solder 3 and the solder 5 respectively, and the lead piece 11 is connected with the D2 and the D1 by the solder 12 and the solder 10 respectively. At this time, the lead tab 4 and the lead tab 11 are ac input terminals, the P connection tab 1 is a dc output negative electrode, the N connection tab 8 is a dc output positive electrode, and the lead tab 4, the lead tab 11, the P connection tab 1, and the N connection tab 8 are respectively led out from the package. The packaging body is epoxy resin 7, the PN junction chip is of a square structure, and a glass or silicon dioxide passivation structure is adopted on the PN junction chip to form a miniature five-layer rectifier bridge stack structure.
During assembly and connection, a connecting sheet is used for prewelding the N-shaped surfaces of two chips together with the connecting sheet by using welding flux, the connecting sheet is an N-shaped connecting sheet 8, the P-shaped surfaces of the other two chips are prewelded together with the connecting sheet by using welding flux on the other connecting sheet, the connecting sheet is a P-shaped connecting sheet 1, and when the four chips are prewelded, the other surface is prewelded simultaneously by using welding flux. Before the above welding, the legs (and outer leads-, + connecting portions) of the P connecting piece 1 and the N connecting piece 8 need to be pre-welded with solder. And aligning the N connecting sheet 8, the P connecting sheet 1 and the lead in the lead sheet up and down, and welding the N connecting sheet with the chip, the P connecting sheet and the corresponding lead on the lead sheet together through formal welding to form the connection of the bridge rectifier.
Claims (8)
1. A chip type micro bridge stack is characterized in that a bridge rectifier is formed by four rectifier diodes in a packaging body, and the chip type micro bridge stack is characterized in that: the four rectifier diodes are composed of the same PN junction chips [ D1, D2, D3 and D4], two of the four PN junction chips are arranged in parallel at the upper part and the other two of the four PN junction chips are arranged in parallel at the lower part, the P type region and the N type region of each PN junction chip are arranged at the upper part and the lower part, the positions of the P type region and the N type region of the PN junction chip at the diagonal position are the same, the two PN junction chips which are stacked at the upper part and the lower part are respectively connected by adopting a connecting sheet, the two PN junction chips which are arranged in parallel at the upper part and the lower part are respectively connected by adopting another connecting sheet, the two connecting sheets on the middle layer are used as a group of electrode terminals, the two connecting sheets on the upper layer and the lower layer are used as another group of electrode terminals.
2. The method of claim 1, wherein: the P-type region and the N-type region of the four PN junction chips are identical in position in space.
3. The method of claim 1, wherein: the P-type region and the N-type region of the PN junction chip at different diagonal positions are opposite in direction in space.
4. The method of claim 1, wherein: and each connecting sheet is connected with the PN junction chip through solder.
5. The method of claim 1, wherein: the PN junction chip is of a square structure.
6. The method of claim 1, wherein: the PN junction chip is of a circular structure.
7. The method of claim 1, wherein: and a glass or silicon dioxide passivation layer is arranged on the PN junction chip.
8. The method of claim 1, wherein: and a silicon rubber passivation layer is arranged on the PN junction chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02219702U CN2545706Y (en) | 2002-03-29 | 2002-03-29 | Sheet type miniature bridge stack |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02219702U CN2545706Y (en) | 2002-03-29 | 2002-03-29 | Sheet type miniature bridge stack |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2545706Y true CN2545706Y (en) | 2003-04-16 |
Family
ID=33698135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN02219702U Expired - Lifetime CN2545706Y (en) | 2002-03-29 | 2002-03-29 | Sheet type miniature bridge stack |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2545706Y (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101886759A (en) * | 2010-05-24 | 2010-11-17 | 晶科电子（广州）有限公司 | Light emitting device using alternating current and manufacturing method thereof |
| CN101373932B (en) * | 2007-08-25 | 2011-06-29 | 绍兴旭昌科技企业有限公司 | Miniature surface-pasted single-phase full wave bridge rectifier and manufacturing method thereof |
| CN102842572A (en) * | 2011-06-24 | 2012-12-26 | 上海金克半导体设备有限公司 | Small double-row bridge rectifier |
| WO2019085442A1 (en) * | 2017-10-31 | 2019-05-09 | 苏州固锝电子股份有限公司 | High-strength rectifier bridge device |
-
2002
- 2002-03-29 CN CN02219702U patent/CN2545706Y/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101373932B (en) * | 2007-08-25 | 2011-06-29 | 绍兴旭昌科技企业有限公司 | Miniature surface-pasted single-phase full wave bridge rectifier and manufacturing method thereof |
| CN101886759A (en) * | 2010-05-24 | 2010-11-17 | 晶科电子（广州）有限公司 | Light emitting device using alternating current and manufacturing method thereof |
| CN102842572A (en) * | 2011-06-24 | 2012-12-26 | 上海金克半导体设备有限公司 | Small double-row bridge rectifier |
| WO2019085442A1 (en) * | 2017-10-31 | 2019-05-09 | 苏州固锝电子股份有限公司 | High-strength rectifier bridge device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: SUZHOU GUDE ELECTRONICS CO LTD Free format text: FORMER NAME OR ADDRESS: GUDE ELECTRONIC CO., LTD., SUZHOU |
|
| CP01 | Change in the name or title of a patent holder |
Patentee after: Gude Electronics Co., Ltd., Suzhou Patentee before: Gude Electronic Co., Ltd., Suzhou |
|
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20120329 Granted publication date: 20030416 |