CN220795346U - Bootstrap capacitor undervoltage protection detection circuit - Google Patents

Abstract

The utility model discloses a bootstrap capacitor undervoltage protection detection circuit which comprises a low-to-high level conversion module, a synchronous BUCK upper tube driving module, a synchronous BUCK topological circuit module, a logic signal level conversion module and a bootstrap capacitor undervoltage detection module, wherein a power supply of the bootstrap capacitor undervoltage detection module is connected with a low power rail VDD, a bootstrap capacitor signal in the synchronous BUCK topological circuit module is connected with a signal of the bootstrap capacitor undervoltage detection module, the signal of the bootstrap capacitor undervoltage detection module is respectively connected with a signal of the low-to-high level conversion module and a signal of the logic signal level conversion module, and the signal of the low-to-high level conversion module and the signal of the logic signal level conversion module are respectively connected with a signal of the synchronous BUCK upper tube driving module. The utility model detects the voltages at two ends of the bootstrap capacitor and outputs the logic protection signal, and the logic signal and the internal low-voltage logic signal are the same as the power rail, so that the switching action of the chip can be effectively closed, and the chip is prevented from being burnt.

Description

Bootstrap capacitor undervoltage protection detection circuit

Technical Field

The utility model relates to the technical field of detection protection circuits, in particular to a bootstrap capacitor under-voltage protection detection circuit.

Background

In the synchronous rectification topology structure of the high-voltage switching power supply, an N-tube is usually used as a power tube, the on-resistance is smaller than that of a P-tube under the same area, such as a switching tube of a synchronous BUCK or a rectifying tube of a synchronous BOOST, and the grid voltage of the N-tube is higher than that of a source electrode to be started. Taking synchronous BUCK as an example, when the upper tube adopts an N tube as a switching tube, the drain electrode is connected with the power supply input voltage of the system, a power supply which is about 5V higher than the power supply of the system is required to be generated to drive the grid electrode of the N tube, and the circuit control is relatively complex by adopting a charge pump mode and is not applicable to the switching power supply. And the bootstrap capacitor port 1 is connected to the source electrode of the switching tube, when the source electrode voltage of the switching tube is 0, the bootstrap capacitor is charged to 5V, the other end port 2 of the bootstrap capacitor is used as a power supply to drive the grid electrode of the switching tube, when the switching tube is opened, the source electrode is lifted along with the drain electrode, and meanwhile, the node voltage of the bootstrap capacitor port 2 is pumped up, the voltage difference of 5V between the grid electrode and the source electrode of the switching tube is maintained, and the opening of the switching tube is ensured.

In the time sequence control, the switching tube needs to be turned on or off to transmit a logic signal with low voltage through the level shifter, and in some special cases, such as low power supply voltage or open bootstrap capacitor, the voltage across the bootstrap capacitor is reduced to a certain extent, which can cause the level shifter to not transmit a correct logic signal, but the rest voltage is still enough to turn on the N-type switching tube. Taking synchronous BUCK as an example, when the lower tube is opened, the upper tube drives the rear stage of the level converter to output an incorrect opening signal, and the upper tube is opened to cause the serial connection of the upper tube and the lower tube, so that the chip is extremely easy to burn.

In the conventional under-voltage protection scheme of the bootstrap capacitor, as shown in fig. 2, after the level converter is turned from low to high, resistor voltage division is performed and the voltage is compared with a threshold voltage VTH of one MOS to generate a logic signal, so as to control driving logic after the level converter, and enable a later stage driving circuit to output a low signal at low voltage, thereby avoiding false turn-on of an upper tube. However, MOS threshold voltage varies greatly with temperature and process, and compared with a fixed resistor voltage division, the MOS threshold voltage has great uncertainty, the design of an excessively large threshold value affects the performance of a chip, and an excessively small threshold value cannot protect the chip. On the other hand, the protection scheme only controls the rear stage driving after the low-to-high level converter, if the logic signal of the same power rail as the low-voltage logic is to be output, the logic signal also needs to pass through a high-to-low level converter, but under the undervoltage state, the high-to-low level converter may also output an error logic signal.

Disclosure of Invention

The present utility model aims to solve at least one of the technical problems in the related art to some extent. Therefore, an object of the present utility model is to provide a bootstrap capacitor under-voltage protection detection circuit, which is independent of a driving and level shifter module, has extremely high detection precision, can directly output an under-voltage protection signal of a power rail with low voltage logic, and can also be normally closed when the driving stage circuit is under low voltage by matching with an independent pull-down circuit.

The utility model provides a bootstrap capacitor undervoltage protection detection circuit which comprises a low-to-high level conversion module, a synchronous BUCK upper tube driving module, a synchronous BUCK topology circuit module, a logic signal level conversion module and a bootstrap capacitor undervoltage detection module, wherein the power input end of the bootstrap capacitor undervoltage detection module is connected with a low power rail VDD, the bootstrap capacitor signal output end in the synchronous BUCK topology circuit module is connected with the signal input end of the bootstrap capacitor undervoltage detection module, the signal output end of the bootstrap capacitor undervoltage detection module is respectively connected with the signal input end of the low-to-high level conversion module and the signal input end of the logic signal level conversion module, the signal output end of the low-to-high level conversion module and the signal output end of the logic signal level conversion module are respectively connected with the signal input end of the synchronous BUCK upper tube driving module, and the signal output end of the synchronous BUCK upper tube driving module is connected with the signal input end of the synchronous BUCK topology circuit module.

Preferably, a bootstrap capacitor charging diode is included, the positive pole of which is connected to the low power rail VDD, and the cathode of the bootstrap capacitor charging diode is respectively connected with the low-to-high level conversion module, the logic signal level conversion module and the synchronous BUCK upper tube driving module.

Preferably, the bootstrap capacitor under-voltage detection module includes a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a MOS transistor HVNM1, a MOS transistor HVPM2, a resistor R1, a resistor R2, a resistor R3, and a current source I0, wherein one end of the resistor R2 and a gate of the MOS transistor HVPM2 are respectively connected to two ends of a bootstrap capacitor signal in the synchronous BUCK topology circuit module, the current source I0 is respectively connected to a drain of the MOS transistor M1, a gate of the MOS transistor M1 and a gate of the MOS transistor M2, a gate of the MOS transistor M3 and a gate of the MOS transistor M4 are respectively connected, a drain of the MOS transistor M2 is respectively connected to one end of the resistor R3 and a gate of the MOS transistor hv1, one end of the resistor R4 is connected to a low power supply rail, a drain of the MOS transistor HVPM 6 is respectively connected to another end of the resistor R4 and another end of the resistor R3, a drain of the transistor nm1 is connected to a drain of the MOS transistor HVPM1 and a drain of the MOS transistor HVPM1 is connected to a drain of the transistor HVPM1, and a drain of the transistor HVPM1 is connected to a drain of the transistor HVPM 1.

Preferably, the MOS tube M1, the MOS tube M2, the MOS tube M3, the MOS tube M4, the MOS tube M5 and the MOS tube HVNM1 are all N-type MOS tubes, and the MOS tube M6, the MOS tube HVPM1 and the MOS tube HVPM2 are all P-type MOS tubes.

Preferably, the gate of the MOS tube M1 and the gate of the MOS tube M2 are connected to form a 1:1 current mirror, and the gate of the MOS tube M3 and the gate of the MOS tube M4 are connected to form a 1:1 current mirror.

The beneficial effects of the utility model are as follows: the problem of low precision of the existing detection structure is improved through the undervoltage detection structure of the bootstrap capacitor, high-precision detection of undervoltage protection of the bootstrap capacitor is realized, safe and efficient operation of a chip is guaranteed, meanwhile, protection logic signals of the same power supply rail as an internal power supply can be output, and the accuracy and stability of signal logic inside the chip can be guaranteed even if the protection logic signals exceed the working voltage range of the level converter.

Drawings

In the drawings:

FIG. 1 is a schematic diagram of a bootstrap capacitor under-voltage protection detection circuit according to the present utility model;

fig. 2 is a schematic diagram of a bootstrap capacitor under-voltage protection circuit according to the present utility model.

In the figure: the device comprises a 1-low-to-high level conversion module, a 2-bootstrap capacitor charging diode, a 3-synchronous BUCK upper tube driving module, a 4-synchronous BUCK topology circuit module, a 5-existing bootstrap capacitor undervoltage detection module, a 6-logic signal level conversion module and a 7-bootstrap capacitor undervoltage detection module.

Detailed Description

Referring to fig. 1, a bootstrap capacitor under-voltage protection detection circuit includes a low-to-high level conversion module 1, a synchronous BUCK upper tube driving module 3, a synchronous BUCK topology circuit module 4, a LOGIC signal level conversion module 6 and a bootstrap capacitor under-voltage detection module 7, wherein a low power rail VDD supplies power to the bootstrap capacitor under-voltage detection module 7, the voltages at two ends of a bootstrap capacitor C1 in the synchronous BUCK topology circuit module 4 are detected, an under-voltage protection LOGIC UV LOGIC is output to the low-to-high level conversion module 1 and the LOGIC signal level conversion module 6, the LOGIC of the low-to-high level conversion module 1 and the LOGIC signal level conversion module 6 is converted into a high power rail through the low power rail and is input to the synchronous BUCK upper tube driving module 3, and the synchronous BUCK upper tube driving module 3 controls the turn-off and turn-on of an N-type upper tube in the synchronous BUCK topology circuit module 4. The positive pole of the bootstrap capacitor charging diode 2 is connected with a low power rail VDD, the negative pole is connected with a high-voltage power supply of the level conversion module 1, the logic signal level conversion module 6 and the synchronous BUCK upper tube driving module 3, and the bootstrap capacitor charging diode charges in the lower tube opening period of the synchronous BUCK topology circuit module 4.

The bootstrap capacitor undervoltage detection module 7 comprises a low-voltage NMOS M1, an NMOS M2, an NMOS M3, an NMOS M4, an NMOS M5, a low-voltage PMOS M6, a high-voltage NMOS HVNM1, a high-voltage PMOS HVPM1, a PMOS HVPM2, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a current source I0. One end of the resistor R2 and the grid electrode of the high-voltage PMOS HVPM2 are respectively connected with two poles of the bootstrap capacitor C1, and the voltages at two ends of the bootstrap capacitor C1 are detected and converted into currents. The reference current source I0 is derived from a reference generating circuit in a chip and is obtained through a V-I conversion circuit, VREF is the reference voltage in the chip, and R0 is the resistance of the reference current generating circuit

The current source I0 flows into the drain electrode of the NMOS M1, the grid connection of the NMOS M1 and the NMOS M2 forms a 1:1 current mirror, and the grid connection of the NMOS M3 and the NMOS M4 forms a 1:1 current mirror. The drain electrode of the NMOS M2 is connected with the grid electrode of the PMOS HVPM1, and one end of each of the resistor R3 and the resistor R4 is connected with the drain electrode of the PMOS M6. Resistor R1 is connected between low power rail VDD and PMOS HVPM1 source, PMOS HVPM1 drain is connected with M3 drain. The drain electrode of the NMOS M4 is connected with the source electrode of the NMOS HVNM1 and the grid electrode of the NMOS M5, and the drain electrode of the NMOS M5 outputs a UV-LOGIG control signal. The grid electrode of the NMOS HVNM1 is connected with the low power supply rail VDD, the drain electrode of the NMOS HVNM1 is connected with the drain electrode of the PMOS HVPM2, the source electrode of the PMOS HVPM2 is connected with the resistor R2, and the other ends of the grid electrode of the PMOS HVPM2 and the resistor R2 are respectively connected with two ends of the bootstrap capacitor C1. The resistor R1 and the resistor R2 are the same in type, size and resistance, the high-voltage PMOS HVPM1 and the PMOS HVPM2 are the same in type and size, and the resistor R2 and the resistor R3 are the same in type and proportional to the resistor R0. On the layout design, the resistor R1 and the resistor R2 are properly matched with the PMOS HVPM1 and the PMOS HVPM2, so that the same offset is ensured when the conditions of the process, the temperature and the like are changed, and the stability of the undervoltage protection threshold voltage is ensured.

And when the following equation is satisfied, the UV-LOGIC signal becomes high to trigger the under-voltage protection LOGIC.

The resistor R1 and the resistor R2 are equal, and the source gate voltages of the high-voltage PMOS HVPM1 and the PMOS HVPM2 are equal, so the undervoltage protection threshold is as follows, and the precision is extremely high.

The UV-LOGIC signal output by the bootstrap capacitor undervoltage protection circuit is input into the high-voltage control circuit to control the high-voltage driving module. When the voltage across the bootstrap capacitor is lower than V _UV-TH And outputting a protection logic signal of the same power rail as the internal power supply, so as to realize high-precision detection of the bootstrap capacitor under-voltage protection. At the same time, the resistor R4 realizes the hysteresis of undervoltage protection only when the voltage at the two ends of the bootstrap capacitor is higher than that of the bootstrap capacitorThe UV-LOGIC signal will go low again.

In summary, the bootstrap capacitor undervoltage detection structure improves the problem of low precision of the existing detection structure, realizes high-precision detection of the bootstrap capacitor undervoltage protection, ensures safe and efficient operation of a chip, can output a protection logic signal of the same power supply rail as an internal power supply, and can still ensure accurate and stable signal logic inside the chip beyond the working voltage range of a level converter.

Claims (5)

1. The bootstrap capacitor undervoltage protection detection circuit is characterized in that: comprises a low-to-high level conversion module (1), a synchronous BUCK upper tube driving module (3), a synchronous BUCK topology circuit module (4), a logic signal level conversion module (6) and a bootstrap capacitor undervoltage detection module (7), wherein the power input end of the bootstrap capacitor undervoltage detection module (7) is connected with a low power rail VDD, the bootstrap capacitor signal output end in the synchronous BUCK topology circuit module (4) is connected with the signal input end of the bootstrap capacitor undervoltage detection module (7), the signal output end of the bootstrap capacitor undervoltage detection module (7) is respectively connected with the signal input end of the low-to-high level conversion module (1) and the signal input end of the logic signal level conversion module (6), the signal output end of the low-to-high level conversion module (1) and the signal output end of the logic signal level conversion module (6) are respectively connected with the signal input end of the synchronous BUCK upper tube driving module (3), and the signal output end of the synchronous BUCK upper tube driving module (3) is connected with the signal input end of the synchronous BUCK topological circuit module (4).

2. The bootstrap capacitor under-voltage protection detection circuit as defined in claim 1, wherein: comprises a bootstrap capacitor charging diode (2), wherein the anode of the bootstrap capacitor charging diode (2) is connected with the low power rail VDD, the negative electrode of the bootstrap capacitor charging diode (2) is respectively connected with the low-to-high level conversion module (1), the logic signal level conversion module (6) and the synchronous BUCK upper tube driving module (3).

3. The bootstrap capacitor under-voltage protection detection circuit as defined in claim 1, wherein: the bootstrap capacitor under-voltage detection module (7) comprises a MOS tube M1, a MOS tube M2, a MOS tube M3, a MOS tube M4, a MOS tube M5, a MOS tube M6, a MOS tube HVNM1, a MOS tube HVPM2, a resistor R1, a resistor R2, a resistor R3 and a current source I0, wherein one end of the resistor R2 and the grid electrode of the MOS tube HVPM2 are respectively connected with two ends of bootstrap capacitor signals in the synchronous BUCK topology circuit module (4), the current source I0 is respectively connected with the drain electrode of the MOS tube M1, the grid electrode of the MOS tube M1 and the grid electrode of the MOS tube M2, the grid electrode of the MOS tube M3 is connected with the grid electrode of the MOS tube M4, the drain electrode of the MOS tube M2 is respectively connected with one end of the resistor R3 and the grid electrode of the MOS tube HVPM1, one end of the resistor R4 is connected with the low power supply rail, the drain electrode of the MOS tube HVR 6 is respectively connected with the other end of the resistor R4 and the drain electrode of the MOS tube HVR 1, the drain electrode of the MOS tube HVR 1 is connected with the drain electrode of the MOS tube HVM 1, the drain electrode of the MOS tube HVM 1 is connected with the drain electrode of the MOS tube HVM 1, and the drain electrode of the MOS tube HVM 1 is connected with the drain electrode of the drain electrode HVM 1.

4. A bootstrap capacitor under-voltage protection detection circuit as defined in claim 3, characterized in that: the MOS tube M1, the MOS tube M2, the MOS tube M3, the MOS tube M4, the MOS tube M5 and the MOS tube HVNM1 are all N-type MOS tubes, and the MOS tube M6, the MOS tube HVPM1 and the MOS tube HVPM2 are all P-type MOS tubes.

5. A bootstrap capacitor under-voltage protection detection circuit as defined in claim 3, characterized in that: the grid electrode of the MOS tube M1 and the grid electrode of the MOS tube M2 are connected to form a 1:1 current mirror, and the grid electrode of the MOS tube M3 and the grid electrode of the MOS tube M4 are connected to form a 1:1 current mirror.