CN219960577U

CN219960577U - Radio frequency front-end circuit

Info

Publication number: CN219960577U
Application number: CN202321027686.4U
Authority: CN
Inventors: 赖钦杰; 葛潇; 倪建兴
Original assignee: Radrock Shenzhen Technology Co Ltd
Current assignee: Radrock Shenzhen Technology Co Ltd
Priority date: 2023-04-28
Filing date: 2023-04-28
Publication date: 2023-11-03
Anticipated expiration: 2033-04-28

Abstract

The utility model discloses a radio frequency front-end circuit. The radio frequency front-end circuit comprises a control circuit and a radio frequency switch circuit, wherein the control circuit comprises a PMOS transistor, and is configured to provide control voltage for the radio frequency switch circuit and control the radio frequency switch circuit to be conducted; the radio frequency front-end circuit further comprises a voltage adjusting circuit, wherein the voltage adjusting circuit is connected with the grid electrode of the PMOS transistor and is used for adjusting the voltage difference between the grid electrode and the source electrode of the PMOS transistor in a conducting state, so that the voltage difference is within a target voltage difference range, the situation that the performance of the radio frequency switching circuit is influenced due to the fact that the voltage difference between the grid electrode and the source electrode is too small is avoided, the situation that the NBTI effect is generated by the PMOS transistor can be avoided, the performance of the control circuit and the performance of the radio frequency switching circuit are considered, and the overall performance and the service life of the radio frequency front-end circuit are guaranteed.

Description

Radio frequency front-end circuit

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a radio frequency front-end circuit.

Background

The conventional radio frequency front-end circuit generally comprises a control circuit and a radio frequency switch circuit, wherein a PMOS transistor is arranged on the control circuit, and the control circuit is connected with the radio frequency switch circuit and is used for providing control voltage for the radio frequency switch circuit so as to control the on-off of the radio frequency switch circuit.

In order to enable the radio frequency switch circuit to have good performance, the control circuit is required to provide a control voltage with a larger voltage value for the radio frequency switch circuit, but in the process that the control circuit forms the control voltage with the larger voltage value, the PMOS transistor in the control circuit can generate an NBTI effect, the response efficiency of the PMOS transistor is reduced, the control circuit is disabled, and the performance and the service life of the radio frequency switch circuit are further affected. The NBTI (Negative Bias Temperature Instability, i.e., negative bias temperature instability) is an index for evaluating the reliability of the PMOS transistor, and refers to a phenomenon that the PMOS transistor is subject to drift in threshold voltage and saturated drain current due to interface defect charges formed by breaking hydrogen-silicon bonds at the interface between the gate oxide layer and the substrate of the PMOS transistor under the action of a negative bias gate voltage and a high temperature.

Disclosure of Invention

The embodiment of the utility model provides a radio frequency front-end circuit, which aims to solve the problem that a PMOS transistor of the existing control circuit is easy to generate NBTI effect.

The embodiment of the utility model provides a radio frequency front-end circuit, which comprises a control circuit and a radio frequency switch circuit, wherein the control circuit comprises a PMOS transistor, and is configured to provide control voltage for the radio frequency switch circuit and control the radio frequency switch circuit to be conducted; the radio frequency front-end circuit further comprises a voltage adjusting circuit, wherein the voltage adjusting circuit is connected with the grid electrode of the PMOS transistor and is used for adjusting the voltage difference between the grid electrode and the source electrode of the PMOS transistor in a conducting state so that the voltage difference is within a target voltage difference range.

Preferably, the target differential pressure range includes a minimum differential pressure value and a maximum differential pressure value;

the minimum differential pressure value is configured as a differential pressure value for turning on the PMOS transistor;

the maximum voltage difference value is configured to be a threshold value for the PMOS transistor to produce an NBTI effect.

Preferably, the target pressure differential range is [0.7V-3V ].

Preferably, the voltage adjusting circuit includes a reference circuit, a step-down circuit, and a voltage stabilizing circuit;

the reference circuit is used for outputting a reference voltage;

the step-down circuit is connected with the reference circuit and is used for carrying out step-down processing on the reference voltage and outputting a first voltage;

the voltage stabilizing circuit is connected with the voltage reducing circuit and the signal output end and is used for stabilizing the first voltage and outputting an adjusting voltage to the signal output end.

Preferably, the reference circuit comprises a bandgap reference circuit for outputting a reference voltage independent of both supply voltage and temperature.

Preferably, the step-down circuit includes a first operational amplifier, a first switching transistor, and a voltage dividing circuit;

the inverting terminal of the first operational amplifier is connected with the reference circuit, and the non-inverting terminal of the first operational amplifier is connected with the first switching transistor and the voltage dividing circuit;

the control end of the first switching transistor is connected with the output end of the first operational amplifier, the first connecting end of the first switching transistor is connected with the power supply end, and the second connecting end of the first switching transistor is grounded through the voltage dividing circuit;

the voltage dividing circuit is connected with the voltage stabilizing circuit.

Preferably, the first switching transistor is an NMOS transistor or a PMOS transistor.

Preferably, the voltage dividing circuit comprises a first resistor and a second resistor which are connected in series, and a connecting node between the first resistor and the second resistor is connected with the voltage stabilizing circuit.

Preferably, the voltage stabilizing circuit comprises a second operational amplifier, a second switching transistor and a bias resistor;

the inverting terminal of the second operational amplifier is connected with the voltage reduction circuit, and the non-inverting terminal of the second operational amplifier is connected with the bias resistor, the second switching transistor and the signal output terminal;

the control end of the second switching transistor is connected with the output end of the second operational amplifier, the first connection end of the second switching transistor is connected with the power supply end through the bias resistor, and the second connection end of the second switching transistor is grounded.

Preferably, the second switching transistor is an NMOS transistor.

Preferably, the voltage stabilizing circuit further comprises a voltage stabilizing branch, one end of the voltage stabilizing branch is connected with the signal output end, and the other end of the voltage stabilizing branch is grounded.

Preferably, the voltage stabilizing branch circuit comprises a voltage stabilizing capacitor.

The embodiment of the utility model also provides a radio frequency front-end circuit, which comprises a control circuit and a radio frequency switch circuit, wherein the control circuit comprises a PMOS transistor, the control circuit is used for providing control voltage for the radio frequency switch circuit and the source electrode of the PMOS transistor, and the radio frequency front-end circuit further comprises a voltage adjusting circuit which is connected with the grid electrode of the PMOS transistor and is used for adjusting the voltage of the grid electrode of the PMOS transistor in a conducting state so that the voltage of the grid electrode of the PMOS transistor in the conducting state is a non-negative value.

Preferably, the voltage of the gate of the PMOS transistor in the on state is greater than or equal to 0.1V.

In the radio frequency front-end circuit, after the PMOS transistor is conducted, the control circuit outputs control voltage to the radio frequency switch circuit to control the radio frequency switch circuit to conduct. Generally, the larger the voltage value of the control voltage is, the better the performance of the radio frequency switch circuit is, but, because the control voltage also provides voltage for the source electrode of the PMOS transistor in the control circuit, the PMOS transistor in the control circuit is easy to generate NBTI effect, in order to reduce the NBTI effect, a voltage adjusting circuit can be arranged, the voltage adjusting circuit is connected with the grid electrode of the PMOS transistor and is used for providing adjusting voltage for the grid electrode of the PMOS transistor so as to adjust the voltage difference between the grid electrode and the source electrode of the PMOS transistor in the conducting state, so that the voltage difference is in the target voltage difference range, the performance of the radio frequency switch circuit is prevented from being influenced, the NBTI effect generated by the PMOS transistor is prevented from being excessively large, the performance of the control circuit and the radio frequency switch circuit is considered, and the integral performance and the service life of the radio frequency front-end circuit are ensured.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments of the present utility model will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an RF front-end circuit according to an embodiment of the utility model;

FIG. 2 is a schematic diagram of a voltage adjusting circuit according to an embodiment of the utility model.

In the figure: 1. a control circuit; 2. a radio frequency switching circuit; 3. a voltage adjustment circuit; 31. a reference circuit; 32. a step-down circuit; 33. and a voltage stabilizing circuit.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be understood that the present utility model may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the utility model to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for the same elements throughout for clarity.

It will be understood that when an element or layer is referred to as being "on" …, "" adjacent to "…," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" …, "" directly adjacent to "…," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present utility model.

Spatially relative terms, such as "under …," "under …," "below," "under …," "above …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under …" and "under …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for the purpose of providing a thorough understanding of the present utility model, detailed structures and steps are presented in order to illustrate the technical solution presented by the present utility model. Preferred embodiments of the present utility model are described in detail below, however, the present utility model may have other embodiments in addition to these detailed descriptions.

An embodiment of the present utility model provides a radio frequency front-end circuit, as shown in fig. 1, where the radio frequency front-end circuit includes a control circuit 1 and a radio frequency switch circuit 2, the control circuit 1 includes a PMOS transistor Q11, and the control circuit 1 is configured to provide a control voltage VPCP to the radio frequency switch circuit 2 to control the radio frequency switch circuit 2 to be turned on; the radio frequency front-end circuit further comprises a voltage adjusting circuit 3, wherein the voltage adjusting circuit 3 is connected with the grid electrode of the PMOS transistor Q11 and is used for adjusting the voltage difference between the grid electrode and the source electrode of the PMOS transistor Q11 in a conducting state so as to enable the voltage difference to be within a target voltage difference range.

The control voltage VPCP refers to a signal that the control circuit 1 outputs to the radio frequency switch circuit 2 and is used for controlling on-off of the radio frequency switch circuit 2, and may be represented by VPCP. Generally, in order to ensure the performance of the rf switch circuit 2, the control circuit 1 needs to output a control voltage VPCP with a larger voltage value to the rf switch circuit 2 to control the on-off of the rf switch circuit 2, where a larger voltage value means that the voltage value is greater than a preset voltage threshold.

The voltage adjustment circuit 3 is a circuit for adjusting the voltage VL. As an example, the voltage adjusting circuit 3 is connected to the gate of the PMOS transistor Q11 and is configured to provide the adjusting voltage VL to the gate of the PMOS transistor Q11, where the adjusting voltage VL is a voltage provided by the voltage adjusting circuit 3 to the gate of the PMOS transistor Q11.

The target voltage difference range is a preset voltage difference range, and is a voltage difference range capable of guaranteeing normal conduction of the PMOS transistor Q11 and effectively avoiding an NBTI effect.

In this embodiment, during the operation of the rf front-end circuit, after the PMOS transistor Q11 is turned on, the control circuit 1 outputs the control voltage VPCP to the rf switch circuit 2 to control the rf switch circuit 2 to be turned on. Generally, the larger the voltage value of the control voltage VPCP, the better the performance of the radio frequency switch circuit 2, but, since the control voltage VPCP also supplies power to the source of the PMOS transistor Q11 in the control circuit 1, this easily causes the PMOS transistor Q11 in the control circuit 1 to generate the NBTI effect, in order to reduce the NBTI effect, the voltage adjusting circuit 3 may be provided, and the voltage adjusting circuit 3 may be connected to the gate of the PMOS transistor Q11 and used to provide the adjusting voltage VL to the gate of the PMOS transistor Q11, so as to adjust the voltage difference between the gate and the source of the PMOS transistor Q11 in the on state, so that the voltage difference is within the target voltage difference range, which not only avoids the influence of the performance of the radio frequency switch circuit 2 due to the too small voltage difference, but also avoids the excessively large voltage difference of the PMOS transistor Q11, so as to achieve the performance of the control circuit 1 and the radio frequency switch circuit 2, and ensure the overall performance and the service life of the radio frequency front-end circuit.

In one embodiment, the target differential pressure range includes a minimum differential pressure value and a maximum differential pressure value;

a minimum differential voltage value configured as a differential voltage value for turning on the PMOS transistor Q11;

the maximum voltage difference value is configured as a threshold value for the PMOS transistor Q11 to generate the NBTI effect.

Wherein the minimum differential pressure value is the minimum value of the target differential pressure range. The maximum differential pressure value is the maximum value of the target differential pressure range.

As an example, the voltage adjusting circuit 3 is connected to the gate of the PMOS transistor Q11, and is configured to adjust the voltage difference between the gate and the source of the PMOS transistor Q11 in the on state so that the voltage difference between the two is greater than a minimum voltage difference value, where the minimum voltage difference value is configured as a voltage difference value that causes the PMOS transistor Q11 to be turned on, so as to ensure that the PMOS transistor Q11 can be in the on state, and ensure normal operation of the radio frequency front end circuit. Generally, if the voltage difference between the gate and the source of the PMOS transistor Q11 in the on state is larger, the control voltage VPCP provided by the control circuit 1 to the rf switch circuit 2 is larger, which is more beneficial to guaranteeing the performance of the rf switch circuit 2.

In one embodiment, the target pressure differential range is [0.7V-3V ].

As an example, the voltage adjusting circuit 3 is connected to the gate of the PMOS transistor Q11, and is configured to adjust the voltage difference between the gate and the source of the PMOS transistor Q11 in the on state so that the voltage difference is greater than or equal to a minimum voltage difference value, which is configured as a voltage difference value for turning on the PMOS transistor Q11, wherein the minimum voltage difference value may be set to 0.7V; and the voltage difference between the two is smaller than or equal to the maximum voltage difference value, and the maximum voltage difference value is configured to enable the PMOS transistor to generate a critical value of NBTI effect, wherein the maximum voltage difference value can be set to be 3V so as to ensure that the PMOS transistor Q11 can be in a conducting state and ensure the normal operation of the radio frequency front-end circuit. Generally, if the voltage difference between the gate and the source of the PMOS transistor Q11 in the on state is larger, the control voltage VPCP provided by the control circuit 1 to the rf switch circuit 2 is larger, which is more beneficial to guaranteeing the performance of the rf switch circuit 2.

As an example, the voltage adjusting circuit 3 is connected to the gate of the PMOS transistor Q11 and is configured to adjust the voltage difference between the gate and the source of the PMOS transistor Q11 in the on state so that the voltage difference is smaller than a maximum voltage difference value, and the maximum voltage difference value is configured to enable the PMOS transistor Q11 to generate the threshold value of the NBTI effect, so that the PMOS transistor Q11 does not generate the NBTI effect in the on state.

In this example, the voltage adjusting circuit 3 is connected to the gate of the PMOS transistor Q11, and is configured to output an adjusting voltage VL to the gate of the PMOS transistor Q11, so as to adjust a voltage difference between the gate and the source of the PMOS transistor Q11 in a conducting state to be between a minimum voltage difference value and a maximum voltage difference value, thereby achieving the purpose of considering the performance of the control circuit 1 and the rf switch circuit 2, and guaranteeing the overall performance and the service life of the rf front-end circuit.

In one embodiment, as shown in fig. 2, the voltage adjusting circuit 3 includes a reference circuit 31, a step-down circuit 32, and a voltage stabilizing circuit 33;

a reference circuit 31 for outputting a reference voltage Vbg;

the voltage step-down circuit 32 is connected to the reference circuit 31, and is configured to step down the reference voltage Vbg and output a first voltage V1;

the voltage stabilizing circuit 33 is connected to the voltage reducing circuit 32 and the PMOS transistor Q11, and is configured to perform voltage stabilizing processing on the first voltage V1, and output the adjustment voltage VL to the PMOS transistor Q11.

The reference circuit 31 is a circuit for supplying the reference voltage Vbg. As an example, the reference voltage Vbg outputs the reference voltage Vbg to the step-down circuit 32, which may be set to about 1.2V.

The step-down circuit 32 is a circuit for realizing a step-down function. As an example, the voltage-reducing circuit 32 is connected to the reference circuit 31 for performing a reduction process on the reference voltage Vbg to obtain a reduced first voltage V1. In this example, the voltage step-down circuit 32 may step down the reference voltage Vbg to a first voltage V1 having no load capability, for example, the reference voltage Vbg of 1.2V may be reduced to a first voltage V1 of 500mA or other several hundred milliamperes, the first voltage V1 being a voltage value required for repairing the NBTI characteristics of the PMOS transistor Q11.

The voltage stabilizing circuit 33 is a circuit for realizing a voltage stabilizing function. As an example, the voltage stabilizing circuit 33 is connected to the voltage reducing circuit 32, and is configured to perform voltage stabilizing processing on the first voltage V1 without load capability, obtain the adjustment voltage VL with load capability, and stably output the adjustment voltage VL to the PMOS transistor Q11 in the control circuit 1.

Generally, under the bias action of the negative gate voltage, the control circuit 1 operates under the conditions of high electric field and high temperature, the saturated drain current Idsat and the transconductance Gm of the PMOS transistor Q11 are continuously reduced, and the absolute value of the corresponding threshold voltage is continuously increased, so that the performance of the control circuit 1 is affected. The voltage adjusting circuit 3 provided in this example can stably output an adjusting voltage VL to the gate of the PMOS transistor Q11, so that the absolute value of the voltage difference between the gate and the source of the PMOS transistor Q11 becomes smaller, thereby reducing the influence of the NBTI effect on the PMOS transistor Q11 and improving the service life of the PMOS transistor Q11.

In an embodiment, the reference circuit 31 comprises a bandgap reference circuit for outputting a bandgap reference voltage Vbg that is independent of both supply voltage and temperature.

The Bandgap reference voltage Vbg (Bandgap voltage reference, abbreviated as Bandgap) may be formed by using a classical Bandgap reference circuit, and the Bandgap reference circuit 31 is formed by using a sum of a voltage proportional to temperature and a voltage inversely proportional to temperature, and temperature coefficients of the two voltages cancel each other to form a Bandgap reference voltage Vbg independent of temperature, and the Bandgap reference voltage Vbg is about 1.25V.

In this example, the reference circuit 31 may be a bandgap reference circuit 31, and may output a bandgap reference voltage Vbg that is not related to both the power supply voltage and the temperature to the step-down circuit 32, so that the adjustment voltage VL output by the final voltage stabilizing circuit 33 is also not related to both the power supply voltage and the temperature, and the adjustment voltage VL is prevented from being affected by the temperature, and the NBTI characteristics of the PMOS transistor Q11 are affected.

In one embodiment, as shown in fig. 2, the voltage step-down circuit 32 includes a first operational amplifier U31, a first switching transistor Q31, and a voltage dividing circuit 321;

the inverting terminal of the first operational amplifier U31 is connected with the reference circuit 31, and the non-inverting terminal of the first operational amplifier U31 is connected with the first switching transistor Q31 and the voltage dividing circuit 321;

the control end of the first switching transistor Q31 is connected with the output end of the first operational amplifier U31, the first connection end of the first switching transistor Q31 is connected with the power supply end, and the second connection end of the first switching transistor Q31 is grounded through the voltage dividing circuit 321;

the voltage dividing circuit 321 is connected to the voltage stabilizing circuit 33.

The first operational amplifier U31 is an operational amplifier in the step-down circuit 32. The first switching transistor Q31 is a switching transistor of the step-down circuit 32. The voltage dividing circuit 321 is a circuit for realizing a voltage dividing function.

As an example, the inverting terminal of the first operational amplifier U31 is connected to the reference circuit 31, and the non-inverting terminal of the first operational amplifier U31 is connected to the first switching transistor Q31 and the voltage dividing circuit 321; the control end of the first switching transistor Q31 is connected with the output end of the first operational amplifier U31, the first connection end of the first switching transistor Q31 is connected with the power supply end, and the second connection end of the first switching transistor Q31 is grounded through the voltage dividing circuit 321; the voltage dividing circuit 321 is connected to the voltage stabilizing circuit 33 to form a negative feedback loop, so that the voltage reducing circuit 32 can reduce the reference voltage Vbg to the first voltage V1. In this example, the inverting terminal of the first operational amplifier U31 receives the reference voltage Vbg input by the reference circuit 31, and generates a small fluctuation, that is, a +v change is formed, and then the change of-a-v output by the first operational amplifier U31 is performed, a is the operational amplifier gain, and then the drain voltage of the first switching transistor Q31 is adjusted to be positive through the amplification of the first switching transistor Q31, and the positive voltage is input to the non-inverting terminal of the first operational amplifier U31, so that the output voltage of the first operational amplifier U31 becomes high, and the cycle is repeated, so that the output voltage of the first operational amplifier U31 is more stable.

In an embodiment, the first switching transistor Q31 is an NMOS transistor or a PMOS transistor.

As an example, the first switching transistor Q31 may be an NMOS transistor, the control terminal of the first switching transistor Q31 is a gate of the NMOS transistor, the first connection terminal of the first switching transistor Q31 is a source of the NMOS transistor, and the second connection terminal of the first switching transistor Q31 is a drain of the NMOS transistor. It is understood that the first switching transistor Q31 may be a PMOS transistor, and the connection relationship between the gate, the source and the drain of the PMOS transistor may be adjusted according to practical situations.

In one embodiment, as shown in fig. 2, the voltage dividing circuit 321 includes a first resistor R31 and a second resistor R32 connected in series, and a connection node between the first resistor R31 and the second resistor R32 is connected to the voltage stabilizing circuit 33.

As an example, the voltage dividing circuit 321 includes a first resistor R31 and a second resistor R32 connected in series, and a connection node between the first resistor R31 and the second resistor R32 is connected to the voltage stabilizing circuit 33. That is, a first end of the first resistor R31 is connected to the non-inverting end of the first operational amplifier U31 and the second connection end of the first switching transistor Q31, a second end of the first resistor R31 is connected to a first end of the second resistor R32, and a second end of the second resistor R32 is grounded; the connection node between the first resistor R31 and the second resistor R32 is connected to the voltage stabilizing circuit 33. In this example, the inverting terminal of the first operational amplifier U31 is connected to the reference circuit 31 and is configured to receive the reference voltage Vbg, the voltages at the non-inverting terminal of the first operational amplifier U31 and the second connecting terminal of the first switching transistor Q31 are V0, the resistance values of the first resistor R31 and the second resistor R32 are R1 and R2, respectively, the first voltage V1 output by the voltage dividing circuit 321 is V1, and during the operation of the voltage reducing circuit 32, v0=vbg, v1=v0×r2/(r1+r2) are used to achieve the purpose of reducing the reference voltage Vbg to the first voltage V1.

In general, when the voltage step-down circuit 32 decreases the reference voltage Vbg to the first voltage V1, and the output first voltage V1 is a voltage having no load capacity, if the reverse current Iout of the external circuit is supplied to the connection node between the first resistor R31 and the second resistor R32, the first voltage V1 output by the voltage dividing circuit 321 is difficult to stabilize, and therefore, the voltage stabilizing circuit 33 is required to perform voltage stabilizing processing.

In one embodiment, as shown in fig. 2, the voltage stabilizing circuit 33 includes a second operational amplifier U32, a second switching transistor Q32, and a bias resistor R33;

the inverting terminal of the second operational amplifier U32 is connected with the voltage reduction circuit 32, and the non-inverting terminal of the second operational amplifier U32 is connected with the bias resistor R33, the second switching transistor Q32 and the signal output terminal;

the control end of the second switching transistor Q32 is connected with the output end of the second operational amplifier U32, the first connection end of the second switching transistor Q32 is connected with the power supply end through the bias resistor R33, and the second connection end of the second switching transistor Q32 is grounded.

As an example, the voltage stabilizing circuit 33 includes a second operational amplifier U32, a second switching transistor Q32, and a bias resistor R33, where an inverting terminal of the second operational amplifier U32 is connected to the voltage reducing circuit 32, and is configured to receive the first voltage V1 output by the voltage reducing circuit 32; the non-inverting terminal of the second operational amplifier U32 is connected with the bias resistor R33, the second switching transistor Q32 and the signal output terminal; the control end of the second switching transistor Q32 is connected with the output end of the second operational amplifier U32, the first connection end of the second switching transistor Q32 is connected with the power supply end through the bias resistor R33, and the second connection end of the second switching transistor Q32 is grounded. In this example, the bias resistor R33 forms a dc bias point, the bias current outputted by the bias resistor R is Ir3, the current at the signal output end of the bias resistor R is Iout, that is, the reverse current of the external circuit is Iout, and the operation process of the voltage stabilizing circuit 33 is as follows: when the external circuit does not have the backward current Iout, a loop formed by the second operational amplifier U32, the second switching transistor Q32 and the bias resistor R33 outputs a stable adjustment voltage VL; when the external circuit has a constant reverse current Iout, the second switching transistor Q32 adjusts its own operating current to be equal to ir3+iout, so that the loop formed by the second operational amplifier U32, the second switching transistor Q32 and the bias resistor R33 outputs a stable adjusting voltage VL, which is a driving voltage with load capability, for driving the PMOS transistor Q11 in the control circuit 1 to operate.

In this example, no matter whether the voltage stabilizing circuit 33 has the backward current Iout of the external circuit, the second operational amplifier U32, the second switching transistor Q32 and the bias resistor R33 cooperate to output the adjustment voltage VL having the same voltage value as the first voltage V1, that is, vl=v1, and the adjustment voltage VL is input to the gate of the PMOS transistor Q11 in the control circuit 1, so that the voltage difference between the gate and the source of the PMOS transistor Q11 in the on state is adjusted by using the adjustment voltage VL, so that the voltage difference is within the target voltage difference range, which not only avoids the too small voltage difference between the two voltage differences and affects the performance of the radio frequency switching circuit 2, but also avoids the too large voltage difference between the two voltage differences, so that the PMOS transistor Q11 generates the NBTI effect, thereby achieving the performance of both the control circuit 1 and the radio frequency switching circuit 2, and ensuring the overall performance and the service life of the radio frequency front-end circuit.

In one embodiment, the second switching transistor Q32 is an NMOS transistor.

As an example, the second switching transistor Q32 is an NMOS transistor, and the operating current of the NMOS switching transistor, that is, the drain current IdNmos thereof, may be adjusted according to practical situations, so that the voltage stabilizing circuit 33 outputs a stable adjustment voltage VL. For example, when the external circuit has a constant backward current Iout, the second switching transistor Q32 adjusts its own operating current to be equal to the sum of the bias current Ir3 and the backward current Iout, that is, the drain current idnmos=ir3+iout, so as to ensure that a stable adjustment voltage VL is output for driving the PMOS transistor Q11 in the control circuit 1 to operate.

In one embodiment, as shown in fig. 2, the voltage stabilizing circuit 33 further includes a voltage stabilizing branch 331, where one end of the voltage stabilizing branch 331 is connected to the signal output terminal, and the other end is grounded.

As an example, when the external circuit has a large current change, the instantaneous backward current Iout is large, which results in that the voltage stabilizing circuit 33 cannot respond timely, so the voltage stabilizing branch 331 needs to be set, one end of the voltage stabilizing branch 331 is connected to the signal output end, and the other end is grounded, and the transient current generated by the severe fluctuation of the external circuit is provided or absorbed timely by using the voltage stabilizing branch 331, so that the adjustment voltage VL output by the voltage stabilizing circuit 33 does not change severely, which is helpful for guaranteeing the stability of the radio frequency front end circuit.

In one embodiment, as shown in fig. 2, the voltage stabilizing branch 331 includes a voltage stabilizing capacitor C31, where one end of the voltage stabilizing capacitor C31 is connected to the signal output end, and the other end is grounded.

As an example, the voltage stabilizing branch 331 includes a voltage stabilizing capacitor C31, where one end of the voltage stabilizing capacitor C31 is connected to the signal output end, and the other end is grounded, and the voltage stabilizing capacitor C31 can be used to absorb transient current generated by severe fluctuation of an external circuit, so as to avoid severe variation of the adjustment voltage VL output by the voltage stabilizing circuit 33, and help to ensure stability of the radio frequency front end circuit.

Another embodiment of the present utility model provides a radio frequency front-end circuit, where the radio frequency front-end circuit includes a control circuit 1 and a radio frequency switch circuit 2, the control circuit 1 includes a PMOS transistor Q11, the control circuit 1 is configured to provide a control voltage VPCP to the radio frequency switch circuit 2 and a source of the PMOS transistor Q11, and the radio frequency front-end circuit further includes a voltage adjusting circuit 3, where the voltage adjusting circuit 3 is connected to a gate of the PMOS transistor Q11, and is configured to adjust a voltage of the gate of the PMOS transistor Q11 in an on state, so that the voltage of the gate of the PMOS transistor Q11 in the on state is a non-negative value.

In the working process of the radio frequency front-end circuit, after the PMOS transistor Q11 is conducted, the control circuit 1 outputs a control voltage VPCP to the radio frequency switch circuit 2 to control the radio frequency switch circuit 2 to conduct. Generally, the greater the voltage value of the control voltage VPCP, the better the performance of the radio frequency switch circuit 2, and the more likely the PMOS transistor Q11 in the control circuit 1 will generate an NBTI effect, in order to reduce the NBTI effect, a voltage adjusting circuit 3 may be provided, where the voltage adjusting circuit 3 is connected to the gate of the PMOS transistor Q11 and is used to provide an adjusting voltage VL for the gate of the PMOS transistor Q11, so as to adjust the voltage of the gate of the PMOS transistor Q11 in the on state, so that the voltage of the gate of the PMOS transistor Q11 in the on state is a non-negative value, so as to avoid the PMOS transistor Q11 from generating an NBTI effect, thereby achieving the purpose of considering the performance of the control circuit 1 and the radio frequency switch circuit 2, and guaranteeing the overall performance and the service life of the radio frequency front-end circuit.

In one embodiment, the voltage of the gate of the PMOS transistor Q11 in the on state is greater than or equal to 0.1V.

As an example, during operation of the rf front-end circuit, after the PMOS transistor Q11 is turned on, the control circuit 1 outputs the control voltage VPCP to the rf switch circuit 2 to control the rf switch circuit 2 to be turned on. Generally, the greater the voltage value of the control voltage VPCP, the better the performance of the radio frequency switch circuit 2, and the more likely the PMOS transistor Q11 in the control circuit 1 will generate the NBTI effect, in order to reduce the NBTI effect, the voltage adjusting circuit 3 may be provided, and the voltage adjusting circuit 3 may be connected to the gate of the PMOS transistor Q11, so as to provide an adjusting voltage VL for the gate of the PMOS transistor Q11, so as to adjust the voltage of the gate of the PMOS transistor Q11 in the on state to be greater than or equal to 0.1V, in this embodiment, the voltage of the gate of the PMOS transistor Q11 in the on state is set to 0.1V, so as to avoid the NBTI effect generated by the PMOS transistor Q11, thereby achieving the performance of the control circuit 1 and the radio frequency switch circuit 2, and guaranteeing the overall performance and the service life of the radio frequency front-end circuit.

The above embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the same; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model, and are intended to be included in the scope of the present utility model.

Claims

1. A radio frequency front-end circuit comprising a control circuit and a radio frequency switching circuit, the control circuit comprising a PMOS transistor, the control circuit configured to provide a control voltage to the radio frequency switching circuit to control the radio frequency switching circuit to conduct; the radio frequency front-end circuit further comprises a voltage adjusting circuit, wherein the voltage adjusting circuit is connected with the grid electrode of the PMOS transistor and is used for adjusting the voltage difference between the grid electrode and the source electrode of the PMOS transistor in a conducting state so that the voltage difference is within a target voltage difference range.

2. The radio frequency front-end circuit of claim 1, wherein the target differential pressure range comprises a minimum differential pressure value and a maximum differential pressure value;

3. The radio frequency front-end circuit of claim 1, wherein the target voltage differential range is [0.7V-3V ].

4. The radio frequency front-end circuit of claim 1, wherein the voltage regulation circuit comprises a reference circuit, a buck circuit, and a voltage regulator circuit;

the reference circuit is used for outputting a reference voltage;

5. The radio frequency front-end circuit of claim 4, wherein the reference circuit comprises a bandgap reference circuit for outputting a reference voltage that is independent of both supply voltage and temperature.

6. The radio frequency front-end circuit of claim 4, wherein the buck circuit comprises a first operational amplifier, a first switching transistor, and a voltage divider circuit;

the voltage dividing circuit is connected with the voltage stabilizing circuit.

7. The radio frequency front-end circuit of claim 6, wherein the first switching transistor is an NMOS transistor or a PMOS transistor.

8. The radio frequency front-end circuit of claim 6, wherein the voltage divider circuit comprises a first resistor and a second resistor connected in series, a connection node between the first resistor and the second resistor being connected to the voltage regulator circuit.

9. The radio frequency front-end circuit of claim 4, wherein the voltage regulator circuit comprises a second operational amplifier, a second switching transistor, and a bias resistor;

10. The radio frequency front-end circuit of claim 9, wherein the second switching transistor is an NMOS transistor.

11. The radio frequency front-end circuit of claim 9, wherein the voltage regulator circuit further comprises a voltage regulator branch having one end connected to the signal output and the other end grounded.

12. The radio frequency front-end circuit of claim 11, wherein the voltage stabilizing branch comprises a voltage stabilizing capacitor.

13. The radio frequency front-end circuit is characterized by comprising a control circuit and a radio frequency switch circuit, wherein the control circuit comprises a PMOS transistor, the control circuit is used for providing control voltage for the radio frequency switch circuit and the source electrode of the PMOS transistor, and the radio frequency front-end circuit further comprises a voltage adjusting circuit which is connected with the grid electrode of the PMOS transistor and is used for adjusting the voltage of the grid electrode of the PMOS transistor in a conducting state so that the voltage of the grid electrode of the PMOS transistor in the conducting state is a non-negative value.

14. The radio frequency front-end circuit of claim 13, wherein the voltage of the gate of the PMOS transistor in the on state is greater than or equal to 0.1V.