CN219831453U - Chip system packaging structure - Google Patents

Abstract

The utility model provides a chip system packaging structure. The chip system packaging structure according to the present utility model includes: an electrical chip package structure unit comprising: the electric chip is arranged on the front surface of the adapter plate, and an electric connection structure which is electrically connected with the conductive wiring in the adapter plate is arranged on the back surface of the adapter plate; the optical chip packaging structure comprises a substrate with a substrate groove formed on the front surface, wherein adhesive is arranged in the substrate groove, an optical chip flush with the surface of the substrate is arranged in the substrate groove, a first electric connection contact and a second electric connection contact are arranged on the surface of the optical chip, and a third electric connection contact which is in the same plane with the first electric connection contact and the second electric connection contact of the optical chip is formed on the surface of the substrate.

Description

Chip system packaging structure

Technical Field

The utility model relates to the field of semiconductor manufacturing, in particular to a chip system packaging structure.

Background

As global internet traffic increases, the demand for data center interconnect bandwidth will continue to increase at an exponential rate.

In order to meet the internet traffic demand, the bandwidth of the data center node needs to reach 10Tb/s, and in order to slow down the trend of increasing the energy consumption of the data center, a method for reducing the power consumption of a system and devices is needed. The I/O pin count per package doubles approximately every 6 years, with the total I/O bandwidth doubling 3 and 4 years. Solving these rate differences requires doubling the bandwidth of 3, 4 years of I/O.

The goal of introducing silicon phototechnology is to increase I/O bandwidth and minimize power consumption. How optical integrated circuits (PICs) and Electrical Integrated Circuits (EIC) are packaged becomes very important. Light has minimal signal attenuation, low power consumption, high bandwidth, and the ability to utilize a mature CMOS ecosystem. These factors, in turn, directly affect I/O bandwidth and power consumption, and thus improper integration of light and electricity would offset all the potential advantages of silicon photons.

I/O to compute nodes may be wire-bonded (wire-bonds) or Flip-Chip bonded (Flip-Chip) to the PCB. Theoretically, the package is very good; however, this is not the case in practice. In particular, silicon photofabrication nodes are relatively late with respect to electrical chip fabrication. The most advanced processes developed for monolithic integration are 45nm and 32nm processes, which are very performance-hungry compared to the 10nm and below processes of the electrical chip, and such packages are not capable of integrating the electrical chip together with the photonic chip. Therefore, it is desired to develop a technical solution capable of effectively realizing a higher density integrated package of an optical chip and an electrical chip.

Chinese patent application CN115588618A discloses a three-dimensional stacked photoelectric packaging structure and a method for preparing the same. However, the first connection bump and the second connection bump have different heights, and the soldering of the soldering blocks with different heights requires the influence of the height difference on the process, thereby greatly improving the process difficulty and possibly reducing the chip stability.

Disclosure of Invention

The utility model aims to solve the technical problem that the prior art has the defects, and provides a chip packaging structure for integrating an optical integrated circuit and an electric integrated circuit so as to realize co-packaging between an optical chip and an electric chip.

According to the present utility model, there is provided a system-on-chip package structure including:

an electrical chip package structure unit comprising: the electric chip is arranged on the front surface of the adapter plate, and an electric connection structure which is electrically connected with the conductive wiring in the adapter plate is arranged on the back surface of the adapter plate;

the optical chip packaging structure comprises a substrate with a substrate groove formed on the front surface, wherein adhesive is arranged in the substrate groove, an optical chip flush with the surface of the substrate is arranged in the substrate groove, a first electric connection contact and a second electric connection contact are arranged on the surface of the optical chip, and a third electric connection contact which is in the same plane with the first electric connection contact and the second electric connection contact of the optical chip is formed on the surface of the substrate.

Preferably, the electrical chip package structure unit is arranged on the optical chip package structure, wherein the electrical connection structure is electrically connected with the first electrical connection contact of the optical chip and the third electrical connection contact of the substrate.

Preferably, the system-on-chip package structure further comprises a fiber optic coupler optically coupled to the second electrical connection contact and extending to the exterior.

Preferably, the second electrical connection contact is arranged outside the first electrical connection contact, facilitating an outwardly extending arrangement of the fiber optic coupler.

Preferably, the chip packaging structure further comprises a cover heat dissipation plate covered on the substrate.

Preferably, an adhesive layer is arranged between the inner side of the heat dissipation plate and the top of the electrical chip package structure to fix the electrical chip package structure.

Preferably, the front surface of the adapter plate is provided with an intermediate dielectric layer, and the surface of the intermediate dielectric layer is provided with an electric contact electrically connected with the adapter plate; the electrical chip is arranged on the front side of the adapter plate by means of electrically conductive contacts, and the electrically conductive contacts are in electrical contact with the electrical contacts.

Preferably, the front surface of the adapter plate and the periphery of the electric chip positioned on the front surface of the adapter plate are coated with the packaging layer, and the upper surface of the electric chip is exposed.

Preferably, an underfill is filled between the electrical chip and the front surface of the interposer.

Preferably, an underfill is filled between the electrical chip packaging structure unit and the optical chip packaging structure.

The utility model can realize high-density integration of the optical chip and the electric chip, wherein the optical chip is embedded into the substrate, and the components of the electric chip arranged on the adapter plate are combined with the substrate, thereby realizing system integration of the photoelectric chip. Wherein, because the electric connection is realized through the electric connection structure in the same plane and the electric contact of the electric connection contact (the first electric connection contact and the third electric connection contact) in the same plane, the welding of the bonding pads or welding spots with different heights is not needed to be considered, the electric connection quality is improved, the connection process is simplified, and the chip stability is improved. Furthermore, the 2.5D technology can be used for high-density I/O integration of the electric chip, so that high operation electrical property is met, powerful performance operation can be achieved, and the obtained structure can be used for large-system integration of a plurality of optical chip modules and electric modules. This structure makes it possible to achieve a minimum line width of 0.4um/0.4um.

Drawings

The utility model will be more fully understood and its attendant advantages and features will be more readily understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, in which:

fig. 1 schematically shows an overall flow chart of a method of manufacturing a system-on-chip package structure according to a preferred embodiment of the present utility model.

Fig. 2 schematically illustrates a temporary substrate provided by a step of manufacturing an electrical chip package structure unit according to a preferred embodiment of the present utility model.

Fig. 3 schematically illustrates an interposer provided by a step of manufacturing an electrical chip package structure unit according to a preferred embodiment of the present utility model.

Fig. 4 schematically shows a structure after the interposer is arranged on the temporary substrate in a step of manufacturing the electrical chip package structure unit according to a preferred embodiment of the present utility model.

Fig. 5 schematically shows a structure after disposing the electric chip packaging structural unit according to a step of manufacturing the electric chip packaging structural unit according to a preferred embodiment of the present utility model.

Fig. 6 schematically illustrates the structure after filling the underfill at the step of manufacturing the electrical chip package structure unit according to the preferred embodiment of the present utility model.

Fig. 7 schematically illustrates the structure after formation of a covering encapsulation layer in a step of manufacturing an electrical chip package structure unit according to a preferred embodiment of the present utility model.

Fig. 8 schematically illustrates a structure after exposing the electrical connection structure of the backside of the interposer in a step of manufacturing an electrical chip package structure unit according to a preferred embodiment of the present utility model.

Fig. 9 schematically illustrates a structure after a step of manufacturing a photo chip package structure unit according to a preferred embodiment of the present utility model provides a substrate.

Fig. 10 schematically illustrates a structure after the step of manufacturing the optical chip package structure unit according to the preferred embodiment of the present utility model is provided with an adhesive.

Fig. 11 schematically shows a structure after the optical chip is disposed according to the step of manufacturing the optical chip package structure unit according to the preferred embodiment of the present utility model.

Fig. 12 schematically illustrates a structure after mounting an electrical chip package structure unit to a substrate according to a preferred embodiment of the present utility model.

Fig. 13 schematically illustrates the structure after forming the fiber coupler according to a preferred embodiment of the present utility model.

Fig. 14 schematically shows a structure after covering the heat dissipation plate according to a preferred embodiment of the present utility model.

Fig. 15 schematically illustrates a perspective view of the package structure of the chip system in fig. 14, wherein the heat dissipation plate and the heat conductive adhesive layer are not illustrated for clarity of illustration of the optical fiber coupler and the electrical chip package structure unit, etc.

Reference numerals illustrate:

a temporary substrate 10; an adapter plate 20; an electrical connection structure 21; an intermediate dielectric layer 22; an electrical contact 23; a conductive contact 24; peelable layer 30; an electrical chip 40; an underfill 41; an encapsulation material 50; a substrate 60; a base groove 61; an adhesive 70; an optical chip 80; a first electrical connection contact 91; a second electrical connection contact 92; an underfill 100; a fiber coupler 110; a heat dissipation plate 130; and a thermally conductive adhesive layer 140.

It should be noted that the drawings are for illustrating the utility model and are not to be construed as limiting the utility model. Note that the drawings representing structures may not be drawn to scale. Also, in the drawings, the same or similar elements are denoted by the same or similar reference numerals.

Detailed Description

Other advantages and effects of the present utility model will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present utility model with reference to specific examples. The utility model may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present utility model.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. In this regard, when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

Such as "between … …" may be used herein, the expression including both end values, and such as "a plurality" may be used, the expression indicating two or more, unless specifically defined otherwise. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature.

In order to fully reveal the features of the utility model, a method of manufacturing a system-on-chip package according to a preferred embodiment of the utility model is first described below.

Fig. 1 schematically shows an overall flow chart of a system-on-chip package manufacturing method according to a preferred embodiment of the utility model. As shown in fig. 1, the system-on-chip package manufacturing method according to the preferred embodiment of the present utility model includes:

a first step S1: providing an adapter plate and an electric chip, and manufacturing an electric chip packaging structure unit, wherein the electric chip is arranged on the front surface of the adapter plate, and an electric connection structure which is electrically connected with the electric chip and is positioned on the same plane is formed on the back surface of the adapter plate;

a second step S2: providing a substrate with a substrate groove and an optical chip, and manufacturing an optical chip packaging structure unit, wherein the optical chip is arranged in the substrate groove formed on the upper surface of the substrate, and the upper surface of the substrate is provided with an electric connection contact which is electrically connected with the optical chip and is positioned on the same plane;

third step S3: and mounting the electric chip packaging structure unit on the substrate to form a combined structure of the electric chip packaging structure unit and the optical chip packaging structure unit, wherein the electric chip packaging structure is electrically connected with the electric connection contact of the optical chip packaging structure unit through the electric connection structure.

The utility model can realize high-density integration of the optical chip and the electric chip, wherein the optical chip is embedded into the substrate, and the components of the electric chip arranged on the adapter plate are combined with the substrate, so that the system integration of the photoelectric chip is realized. Wherein, because the electric connection is realized through the electric contact of the electric connection structure in the same plane and the electric connection contact in the same plane, the welding of the bonding pads or welding spots with different heights is not needed to be considered, the electric connection quality is improved, the connection process is simplified, and the chip stability is improved.

Furthermore, the 2.5D technology can be used for high-density I/O integration of the electric chip, so that high operation electrical property is met, powerful performance operation can be achieved, and the obtained structure can be used for large-system integration of a plurality of optical chip modules and electric modules. This structure makes it possible to achieve a minimum line width of 0.4um.

It should be noted that, the descriptions of the terms "first" and "second" are merely used for distinguishing steps, and the like, and are not used for indicating the sequence relationship between the steps, for example, the present utility model is not limited to the sequence between the first step and the second step, and the first step may be performed before the second step, or the second step may be performed before the first step, and the first step and the second step may be performed simultaneously.

Further, as shown in fig. 1, the system-on-chip package manufacturing method according to the preferred embodiment of the present utility model may further include at least one of the following steps:

fourth step S4: providing an optical fiber coupler, and arranging the optical fiber coupler on a combined structure of the electric chip packaging structure unit and the optical chip packaging structure unit;

fifth step S5: a heat sink is provided, and a heat sink is covered on the substrate.

Further specific embodiments of the present utility model are described below with reference to the accompanying drawings.

First, fig. 2 to 6 are views for describing a flow of steps of manufacturing an electrical chip package structure unit according to a chip system package manufacturing method according to a preferred embodiment of the present utility model, as follows.

First, as shown in fig. 2 and 3, a temporary substrate 10 and an interposer 20 are provided, wherein an electrical connection structure 21 on the same plane electrically connected with a conductive wiring in the interposer 20 is disposed on the back surface of the interposer 20, an intermediate dielectric layer 22 is formed on the front surface of the interposer 20, and an electrical contact 23 electrically connected with the interposer 20 is formed on the surface of the intermediate dielectric layer 22; specifically, for example, as shown in the drawing, the electrical connection structures 21 in the same plane have pads of the same height.

Subsequently, as shown in fig. 4, the interposer 20 is disposed on the temporary substrate 10; preferably, a peelable layer 30 for protection and temporary adhesion is arranged between the temporary substrate 10 and the interposer 20. The interposer 20 is temporarily bonded to the temporary substrate 10 through the peelable layer 30. Preferably, the temporary substrate 10 is a glass substrate.

Thereafter, as shown in fig. 5, the electrical chip 40 is arranged on the front side of the interposer 20 through the electrically conductive contacts 24, and the electrically conductive contacts 24 are in electrical contact with the electrical contacts 23.

Thereafter, as shown in fig. 6, an underfill 41 covering the conductive contacts 24 is formed by an underfill process; the underfill 41 fills in between the electrical chip 40 and the interposer 20 by capillary effect. The underfill 41 can protect the junction between the electrical chip 40 and the electrical contact 24 from corrosion or damage, and can improve the mechanical properties of the electrical chip 40, the electrical contact 24 and the interposer 20, and improve the mechanical strength.

Subsequently, as shown in fig. 7, an encapsulation layer 50 is formed to cover the front surface of the interposer 20, exposing the upper surface of the electrical chip 40. Generally, the encapsulation layer 50 is coated on the front surface of the interposer 20 and surrounds the electrical chip 40 located on the front surface of the interposer, and exposes the upper surface of the electrical chip 40 through a polishing process.

Then, as shown in fig. 8, the temporary substrate 10 is removed, exposing the electrical connection structure 21 of the back surface of the interposer 20, wherein the electrical connection structure 21 is on the same plane.

The flow of steps of manufacturing the optical chip package structure unit according to the chip system package manufacturing method of the preferred embodiment of the present utility model is described below with reference to fig. 9 to 11, as follows.

As shown in fig. 9, a substrate 60 having a substrate groove 61 formed in the front surface is provided;

as shown in fig. 10, an adhesive 70 is disposed in the base recess 61;

as shown in fig. 11, the optical chip 80 is disposed on the adhesive 70 of the base recess 61, the optical chip 80 has a first electrical connection contact 91 and a second electrical connection contact 92 on the same plane, and the front surface of the base 60 has a third electrical connection contact 93 coplanar with the first electrical connection contact 91 and the second electrical connection contact 92 of the surface of the optical chip 80, thereby forming an optical chip package structure unit. The second electrical connection contacts 92 are used to connect optical fibers. The first electrical connection contact 91 and the third electrical connection contact 93 are used to connect the electrical chip package structure.

The flow of the subsequent other steps of the system-on-chip package manufacturing method according to the preferred embodiment of the present utility model is described below with reference to fig. 12 to 14, as follows.

As shown in fig. 12, the electrical chip package structure is electrically connected to the first electrical connection contact 91 and the third electrical connection contact 93 of the optical chip package structure unit through the electrical connection structure 21, wherein a gap between the interposer 20 and the optical chip package structure unit is filled with an underfill 100. The underfill 100 filled between the interposer 20 and the optical chip package structure unit is the same as the underfill 41 filled between the electrical chip 40 and the interposer 20. The underfill 100 is filled between the electrical connection structures 21, so that on one hand, the connection between the electrical chip package structure and the first electrical connection contact 91 and the third electrical connection contact 93 can be protected from corrosion or connection damage, and on the other hand, the mechanical properties between the electrical chip package structure, the first electrical connection contact 91 and the third electrical connection contact 93, and the optical chip package structure unit (the optical chip 80 and the substrate 60) can be improved, and the mechanical strength can be improved.

As shown in fig. 13, the second electrical connection contact 92 is optically coupled with a fiber coupler 110 extending to the outside.

As shown in fig. 14, finally, a heat dissipation plate 130 is covered on the substrate 60, and the electric chip package structure is covered between the heat dissipation plate 130 and the substrate 60. Preferably, a heat conductive adhesive layer 140 is disposed between the inside of the heat dissipation plate 130 and the top of the electrical chip package structure to fix the electrical chip package structure. An adhesive (not shown) is provided between the heat dissipation plate 130 and the position where the heat dissipation plate 130 is supported around the substrate 60.

Fig. 15 schematically illustrates a perspective view of the package structure of the chip system in fig. 14, wherein the heat dissipation plate and the heat conductive adhesive layer are not illustrated for clarity of illustration of the optical fiber coupler and the electrical chip package structure unit, etc. The optical fiber couplers 110 are provided in plurality, the corresponding electrical chips 80 are provided in plurality, and the plurality of optical fiber couplers 110 extend outwardly from four sides of the package structure, respectively. The utility model can realize high-density integration of the optical chip and the electric chip, wherein the optical chip is embedded into the substrate, and the components of the electric chip arranged on the adapter plate are combined with the substrate, thereby realizing system integration of the photoelectric chip. Wherein, because the electric connection is realized through the electric connection structure in the same plane and the electric contact of the electric connection contact (the first electric connection contact and the third electric connection contact) in the same plane, the welding of the welding pads or welding spots with different heights is not needed to be considered, the electric connection quality is improved and the connection process is simplified. Furthermore, the 2.5D technology can be used for high-density I/O integration of the electric chip, so that high operation electrical property is met, powerful performance operation can be achieved, and the obtained structure can be used for large-system integration of a plurality of optical chip modules and electric modules. This structure makes it possible to achieve a minimum line width of 0.4um/0.4um.

A chip package structure according to a preferred embodiment of the present utility model is described below with reference to fig. 14. The chip package structure according to the preferred embodiment of the present utility model may be manufactured using the above-described method.

As shown in fig. 14, the system-on-chip package structure according to the preferred embodiment of the present utility model includes:

an electrical chip package structure unit comprising: an interposer 20 and an electrical chip 40 disposed on a front surface of the interposer 20, wherein an electrical connection structure 21 electrically connected to the conductive wiring in the interposer 20 is disposed on a back surface of the interposer 20;

the optical chip package structure comprises a substrate 60 with a substrate groove 61 formed on the front surface, wherein an adhesive 70 is arranged in the substrate groove 61, an optical chip 80 flush with the surface of the substrate 60 is arranged in the substrate groove 61, a first electric connection contact 91 and a second electric connection contact 92 are arranged on the surface of the optical chip 80, and a third electric connection contact 93 which is in the same plane with the first electric connection contact 91 and the second electric connection contact 92 of the optical chip 80 is formed on the surface of the substrate.

Wherein the electrical chip package structure unit is arranged on the optical chip package structure, wherein the electrical connection structure 21 is electrically connected with the first electrical connection contact 91 of the optical chip and the third electrical connection contact 93 of the substrate 60.

Preferably, as shown in fig. 13, the chip system package structure further includes an optical fiber coupler 110 connected to the second electrical connection contact 92 and extending to the outside. For example, the first electrical connection contact 91, the second electrical connection contact 92, and the third electrical connection contact 93, which are in the same plane, have pads of the same height.

In general, the second electrical connection contacts 92 are arranged outside the first electrical connection contacts 91, i.e. the second electrical connection contacts 92 are arranged on the side of the optical chip 80 remote from the center of the substrate 60, i.e. the second electrical connection contacts 92 are arranged on the side of the optical chip 80 adjacent to the periphery of the chip package structure. The second electrical connection contacts 92 are used to connect the fiber optic couplers to facilitate the outwardly extending arrangement of the fiber optic couplers.

Preferably, as shown in fig. 14 and 15, the chip package structure further includes a cover heat dissipation plate 130 covering the substrate 60.

As shown in fig. 14, a heat conductive adhesive layer 140 is preferably disposed between the inside of the heat dissipation plate 130 and the top of the electrical chip package structure to fix the electrical chip package structure.

Preferably, the front surface of the interposer 20 and the periphery of the electrical chip 40 located on the front surface of the interposer are coated with the encapsulation layer 50, and the upper surface of the electrical chip 40 is exposed. The heat conducting adhesive layer 140 is disposed on the upper surface of the electric chip 40, which is favorable for transferring the heat of the electric chip 40 to the heat dissipation plate 130 through the heat conducting adhesive layer 140, reducing the heat transfer path and accelerating the heat dissipation.

Preferably, an underfill 41 is filled between the electrical chip 40 and the front surface of the interposer 20. The underfill 41 can protect the junction between the electrical chip 40 and the electrical contact 24 from corrosion or damage, and can improve the mechanical properties of the electrical chip 40, the electrical contact 24 and the interposer 20, and improve the mechanical strength.

Preferably, the underfill 100 is filled between the electrical chip package structure unit and the optical chip package structure. The underfill 100 is filled between the electrical connection structures 21, so that on one hand, the connection between the electrical chip package structure and the first electrical connection contact 91 and the third electrical connection contact 93 can be protected from corrosion or connection damage, and on the other hand, the mechanical properties between the electrical chip package structure, the first electrical connection contact 91 and the third electrical connection contact 93, and the optical chip package structure unit (the optical chip 80 and the substrate 60) can be improved, and the mechanical strength can be improved.

In this embodiment, for example, for the electric chip 40 and the adhesive 70, the chip may be provided as a bare chip or as a preliminarily packaged chip. Moreover, the specific type of the chip can be selected according to the needs, and the specific manufacturing process of the chip can be selected according to the needs.

Fig. 15 schematically illustrates a perspective view of the package structure of the chip system in fig. 14, wherein the heat dissipation plate and the heat conductive adhesive layer are not illustrated for clarity of illustration of the optical fiber coupler and the electrical chip package structure unit, etc. In this embodiment, a plurality of optical fiber couplers 110 are provided, and a plurality of corresponding electrical chips 80 are provided, and the plurality of optical fiber couplers 110 extend outwardly from four sides of the package structure.

Preferably, the minimum linewidth of the system-on-chip package is 0.4um.

Preferably, the front surface of the adapter plate is provided with an intermediate dielectric layer 22, and the surface of the intermediate dielectric layer 22 is provided with an electric contact 23 electrically connected with the adapter plate; the electrical chip 40 is arranged on the front side of the adapter plate by means of electrically conductive contacts, and the electrically conductive contacts 24 are in electrical contact with the electrical contacts 23.

The utility model can realize high-density integration of the optical chip and the electric chip, wherein the optical chip is embedded into the substrate, and the components of the electric chip arranged on the adapter plate are combined with the substrate, thereby realizing system integration of the photoelectric chip. Wherein, because the electric connection is realized through the electric connection structure in the same plane and the electric contact of the electric connection contact (the first electric connection contact and the third electric connection contact) in the same plane, the welding of the welding pads or welding spots with different heights is not needed to be considered, the electric connection quality is improved and the connection process is simplified. Furthermore, the 2.5D technology can be used for high-density I/O integration of the electric chip, so that high operation electrical property is met, powerful performance operation can be achieved, and the obtained structure can be used for large-system integration of a plurality of optical chip modules and electric modules. This structure makes it possible to achieve a minimum line width of 0.4um/0.4um.

It should be noted that, unless specifically stated otherwise, the terms "first," "second," "third," and the like in the specification are used merely as a distinction between various components, elements, steps, etc. in the specification, and are not used to denote a logical or sequential relationship between various components, elements, steps, etc.

It will be appreciated that although the utility model has been described above in terms of preferred embodiments, the above embodiments are not intended to limit the utility model. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present utility model still fall within the scope of the technical solution of the present utility model.

Claims (10)

1. A system-on-chip package structure, characterized by comprising:

an electrical chip package structure unit comprising: the electric chip is arranged on the front surface of the adapter plate, and an electric connection structure which is electrically connected with the conductive wiring in the adapter plate is arranged on the back surface of the adapter plate; the optical chip packaging structure comprises a substrate with a substrate groove formed on the front surface, wherein adhesive is arranged in the substrate groove, an optical chip flush with the surface of the substrate is arranged in the substrate groove, a first electric connection contact and a second electric connection contact are arranged on the surface of the optical chip, and a third electric connection contact which is in the same plane with the first electric connection contact and the second electric connection contact of the optical chip is formed on the surface of the substrate.

2. The system-on-chip package structure of claim 1, further comprising: the electrical chip packaging structure unit is arranged on the optical chip packaging structure, wherein the electrical connection structure is electrically connected with the first electrical connection contact of the optical chip and the third electrical connection contact of the substrate.

3. The system-on-chip package of claim 1, further comprising a fiber optic coupler optically coupled to the second electrical connection contact and extending to the exterior.

4. A system-on-chip package as claimed in claim 3, wherein the second electrical connection contacts are disposed outside the first electrical connection contacts to facilitate an outwardly extending arrangement of the fiber optic coupler.

5. The system-on-chip package of claim 1 or 2, further comprising a cover heat spreader plate over the substrate.

6. The package structure of claim 5, wherein an adhesive layer is disposed between the inner side of the heat dissipation plate and the top of the electrical chip package structure to secure the electrical chip package structure.

7. The chip system package structure according to claim 1 or 2, wherein an intermediate dielectric layer is formed on the front surface of the interposer, and an electrical contact electrically connected to the interposer is formed on the surface of the intermediate dielectric layer; the electrical chip is arranged on the front side of the adapter plate by means of electrically conductive contacts, and the electrically conductive contacts are in electrical contact with the electrical contacts.

8. The package structure of claim 1, wherein the front surface of the interposer and the periphery of the electrical chip on the front surface of the interposer are coated with a packaging layer, and the upper surface of the electrical chip is exposed.

9. The package structure of claim 1, wherein an underfill is disposed between the electrical chip and the front side of the interposer.

10. The package structure of claim 2, wherein an underfill is disposed between the electrical chip package structure unit and the optical chip package structure.