WO2022041159A1 - Chip packaging structure, electronic device, and method for preparing chip packaging structure - Google Patents

Chip packaging structure, electronic device, and method for preparing chip packaging structure Download PDF

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Publication number
WO2022041159A1
WO2022041159A1 PCT/CN2020/112294 CN2020112294W WO2022041159A1 WO 2022041159 A1 WO2022041159 A1 WO 2022041159A1 CN 2020112294 W CN2020112294 W CN 2020112294W WO 2022041159 A1 WO2022041159 A1 WO 2022041159A1
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WO
WIPO (PCT)
Prior art keywords
chip
substrate
data processing
packaging
layer
Prior art date
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PCT/CN2020/112294
Other languages
French (fr)
Chinese (zh)
Inventor
张童龙
罗立德
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/112294 priority Critical patent/WO2022041159A1/en
Priority to CN202080103465.3A priority patent/CN116057680A/en
Publication of WO2022041159A1 publication Critical patent/WO2022041159A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present application relates to the technical field of chip packaging, and in particular, to a chip packaging structure, an electronic device and a method for preparing the chip packaging structure.
  • the chip light-emitting technology is the future of the development of the communication field, because the optical transmission has the characteristics of high transmission efficiency, low transmission loss, anti-radio frequency interference and anti-electromagnetic interference.
  • the chip light extraction technology is generally used in the chip package structure with super large capacity and large package size. In this way, the advantages of high transmission efficiency and low transmission loss are more prominent.
  • Fig. 1 is a schematic diagram of a chip packaging structure applying the chip light extraction technology, wherein, multiple system-on-a-chip (SOC) 3 and multiple optical engines (Optical Engine, OE) 2 are integrated on the package substrate 1, and the light engine can be connected to a light source outside the chip package structure through an optical fiber.
  • SOC system-on-a-chip
  • OE optical Engine
  • the package substrate 1 includes a substrate 111 , and rewiring structures 112 located on the upper surface and the lower surface of the substrate 111 .
  • FIG. 3 is an assembly diagram of the chip package structure in FIG. 1 .
  • the package substrate 1 is disposed on the printed circuit board 5 and is electrically connected to the printed circuit board 5 , wherein the light engine 2 may include a photonic integrated circuit ((Photonic IC, PIC))
  • the optical chip 21, the optical fiber connection structure (Fiber Attach Unit, FAU) 23 connected to the optical chip 21, may also include an electrical chip 22 that is electrically connected to the optical chip 21 and is formed with an electronic integrated circuit (Electrical IC, EIC).
  • the optical chip 21 and the system-on-chip 3 are arranged on the package substrate 1 using a flip-chip mounting process. As shown in FIG. 3 , the bottoms of the optical chip 21 and the system-on-chip 3 are soldered on the package substrate 1 through bumps 6 , and The optical chip 201 and the system-on-chip 3 are electrically connected through the metal wires 112 .
  • the chip package structure is usually made by flip-chip mounting process or surface mount process (SMT). This will lead to a large warpage phenomenon and a large internal package stress after the entire chip package structure is packaged. In this way, the reliability of the entire chip package structure will be greatly reduced, and the chip package structure cannot meet the service life requirement.
  • SMT surface mount process
  • Embodiments of the present application provide a chip package structure, an electronic device, and a method for preparing the chip package structure, which are mainly used to reduce the warpage degree of the chip and reduce the internal stress of the package.
  • the present application provides a chip packaging structure
  • the chip packaging structure includes: a packaging substrate, a plastic packaging layer, at least one optical engine, and at least one data processing chip
  • the packaging substrate is a rewiring layer
  • the optical engine includes an optical fiber connection structure
  • an optical chip composed of a photonic integrated circuit the optical chip and the data processing chip are integrated on the same surface of the packaging substrate, and are respectively electrically connected to the packaging substrate, and the light-emitting surface of the optical chip is located on the side away from the packaging substrate
  • plastic packaging The layer is located on the surface of the packaging substrate integrated with the optical chip and the data processing chip, and wraps the optical chip and the data processing chip.
  • the rewiring layer has a lower elastic modulus and lower rigidity than a core substrate (Core substrate). reduce.
  • the warpage of the entire chip packaging structure will be effectively reduced, and the packaging internal stress of the chip packaging structure will also be reduced, the performance of the chip packaging structure will be improved, and the service life will be prolonged.
  • the connection between the optical fiber connection structure and the light emitting surface can be ensured by forming a channel through the plastic sealing layer to the light emitting surface of the optical chip.
  • the data processing chip is disposed close to a central area of the package substrate, there are multiple light engines, and the multiple light engines are arranged along the periphery of the package substrate.
  • the chip packaging structure further includes an interconnection substrate;
  • the data processing chip has a plurality of data processing chips, the plurality of data processing chips are integrated on the interconnection substrate, and are electrically connected to the interconnection substrate, and the interconnection substrate is provided with on and in electrical connection with the package substrate.
  • the interconnection substrate is a rewiring layer or an interposer board.
  • the chip packaging structure further includes connection terminals; the connection terminals are arranged on a surface of the packaging substrate opposite to the data processing chip.
  • the application provides a chip packaging structure
  • the chip packaging structure includes: a packaging substrate, a plastic packaging layer, at least one optical engine, and at least one data processing chip, wherein the optical engine and the data processing chip are integrated on opposite sides of the packaging substrate. on the two surfaces and are respectively electrically connected with the packaging substrate, the plastic packaging layer is located on the surface of the packaging substrate with the data processing chip, and wraps the data processing chip.
  • the rewiring layer has a lower elastic modulus and lower rigidity than the Core substrate. In this way, under the premise of ensuring the overall strength of the chip packaging structure, the warpage of the entire chip packaging structure will be effectively reduced, and the packaging internal stress of the chip packaging structure will also be reduced, the performance of the chip packaging structure will be improved, and the service life will be prolonged. .
  • the chip packaging structure further includes a plurality of dummy structures; the plurality of dummy structures and the data processing chips are located on the same surface of the packaging substrate, and the dummy structures are encapsulated in the plastic packaging layer, and the data processing chips are close to A central area of the package substrate is provided, and a plurality of dummy structures are arranged along the periphery of the package substrate.
  • the dummy structure is a bare chip. Using the bare chip as the dummy structure can simplify the manufacturing process and reduce the manufacturing cost.
  • the chip packaging structure further includes an interconnection substrate;
  • the data processing chip has a plurality of data processing chips, the plurality of data processing chips are integrated on the interconnection substrate, and are electrically connected to the interconnection substrate, and the interconnection substrate is provided with on and in electrical connection with the package substrate.
  • the interconnection substrate is a redistribution layer or an interposer board.
  • the chip package structure further includes connection terminals: the connection terminals and the light engine are located on the same surface of the package substrate.
  • the chip packaging structure further includes a power supply chip; the power supply chip and the connection terminals are located on the same surface of the package substrate.
  • an embodiment of the present application further provides a method for preparing a chip package, the method comprising:
  • a package base is formed on the support plate, and the package base is a coreless substrate or a rewiring layer;
  • the layer the light-emitting surface of the optical chip of the light engine is exposed, and the support plate is removed to obtain a chip package structure.
  • the package substrate used to carry the optical engine and the data processing chip adopts a rewiring layer, in this case, when the optical engine and the data processing chip are electrically connected to the package substrate, The degree of warpage can be effectively reduced, and the encapsulation internal stress of the prepared chip package structure can also be finally reduced, and the plastic encapsulation layer can ensure the strength of the finally prepared chip package structure.
  • the optical engine includes at least an optical fiber connection structure, and an optical chip integrated with a photonic integrated circuit; at least one optical engine is integrated on a packaging substrate, and a plastic package is formed on the packaging substrate with the optical engine
  • the layer includes: integrating at least one optical chip on the packaging substrate, and making the light-emitting surface of the optical chip away from the packaging substrate; covering the light-emitting surface with a temporary dummy structure; forming a plastic sealing layer on the packaging substrate so that the plastic packaging layer wraps the optical chip and the packaging substrate.
  • the periphery of the temporary dummy structure, and the surface of the temporary dummy structure is exposed to the outside of the plastic sealing layer; the temporary dummy structure is removed to form a channel through the plastic sealing layer to the light-emitting surface; the optical fiber connecting structure is passed through the channel and is connected with the light-emitting surface connect.
  • a temporary dummy structure can be used to cover the light-emitting surface before the plastic sealing layer is formed, and then the plastic sealing layer is prepared.
  • At least one light engine and at least one data processing chip are integrated on the packaging substrate, and electrically connected to the packaging substrate respectively, and a plastic packaging layer is formed on the packaging substrate, so that the data processing chip and the packaging substrate are electrically connected to each other.
  • the light engine is encapsulated in a plastic encapsulation layer, and the support plate is removed, including: integrating at least one light chip and at least one data processing chip on the same surface of the package substrate; having the light engine and data processing on the package substrate A plastic packaging layer is formed on the surface of the chip, so that the plastic packaging layer wraps the light engine and the data processing chip, and the light emitting surface of the optical chip of the light engine is exposed outside the plastic packaging layer; the support plate is removed to obtain the chip packaging structure.
  • At least one light engine and at least one data processing chip are integrated on the packaging substrate, and electrically connected to the packaging substrate respectively, and a plastic packaging layer is formed on the packaging substrate, so that the data processing chip and the packaging substrate are electrically connected to each other.
  • the light engine is encapsulated in a plastic encapsulation layer, and the support plate is removed, including: integrating at least one data processing chip on the surface of the package substrate; forming a plastic encapsulation layer on the surface of the package substrate with the data processing chip; removing A support plate; at least one light engine is integrated on the other surface of the package substrate, so that the light engine and the data processing chip are located on two opposite surfaces of the package substrate to obtain a chip package structure.
  • integrating the at least one data processing chip on the surface of the packaging substrate includes: integrating the at least one data processing chip and a plurality of dummy structures on the surface of the packaging substrate, and the data processing chip It is disposed close to the central area of the package substrate, and a plurality of dummy structures are arranged along the periphery of the package substrate.
  • the preparation method when there are multiple data processing chips; before integrating the data processing chips on the packaging substrate, the preparation method further includes: integrating the multiple data processing chips on the interconnect substrate, and It is electrically connected with the interconnection substrate, so that the interconnection substrate integrated with a plurality of data processing chips is integrated on the package substrate.
  • the multiple data processing chips can be integrated on the interconnect substrate first, and then the interconnect substrate can be integrated on the package substrate.
  • the present application further provides an electronic device, including a printed circuit board and the chip package structure in any implementation manner of the first aspect or the second aspect, or the chip package in any implementation manner of the third aspect
  • the printed circuit board is electrically connected with the chip package structure.
  • the electronic device provided by the embodiment of the present application includes the chip packaging structure of the first aspect embodiment or the second aspect embodiment, or the chip packaging structure obtained by the third aspect embodiment. Therefore, the electronic device provided by the embodiment of the present application is the same as the above technology.
  • the chip packaging structure of the solution can solve the same technical problem and achieve the same expected effect.
  • FIG. 1 is a schematic diagram of a chip packaging structure in the prior art
  • FIG. 2 is a schematic structural diagram of a package substrate of a chip package structure in the prior art
  • FIG. 3 is a schematic diagram of a connection relationship between a chip packaging structure and a PCB in the prior art
  • FIG. 4 is a partial structural schematic diagram of an electronic device according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a chip packaging structure according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a package substrate according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a chip packaging structure according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a chip packaging structure according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a chip packaging structure according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of an adapter board according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of the connection relationship between a plurality of data processing chips and an interconnection substrate according to an embodiment of the present application;
  • FIG. 12 is a schematic diagram of one direction of a chip packaging structure according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of another direction of the chip packaging structure according to the embodiment of the present application.
  • FIG. 14 is a schematic diagram of a chip packaging structure according to an embodiment of the present application.
  • FIG. 15 is a schematic diagram of one direction of a chip packaging structure according to an embodiment of the present application.
  • 16 is a schematic diagram of another direction of the chip packaging structure according to the embodiment of the present application.
  • FIG. 17 is a flowchart of a method for preparing a chip package structure according to an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram corresponding to each step in the preparation method of the chip packaging structure according to the embodiment of the present application.
  • FIG. 21 is a schematic structural diagram corresponding to each step in a method for fabricating a chip packaging structure according to an embodiment of the present application after completion of each step.
  • Embodiments of the present application provide an electronic device.
  • the electronic device may include a mobile phone (mobile phone), a tablet computer (pad), a smart wearable product (eg, a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR), etc. equipment.
  • the embodiments of the present application do not specifically limit the specific form of the above electronic device.
  • the above-mentioned electronic device 1 may include a chip package structure 10 and a printed circuit board (printed circuit board, PCB) 5 .
  • the chip package structure 10 is electrically connected to the PCB 5 through the electrical connection structure 11 , so that the chip package structure 10 can realize signal transmission with other chips on the PCB 5 .
  • the electrical connection structure 11 may be a ball grid array (BGA). In an alternative embodiment, if the size of the chip package structure is relatively large. In order to ensure the reliability of the electrical connection between the chip package structure 10 and the PCB 5 , the electrical connection structure 11 may also use a connection terminal (socket) with a slot-type fixing structure, and the connection terminal may also be called a connector, a plug, etc. .
  • BGA ball grid array
  • the chip packaging structure 10 includes: a data processing chip 101 and an optical engine (Optical Engine, OE) 2, and a packaging substrate 102 for carrying the data processing chip 101 and the OE2.
  • the data processing chip 101 and the OE2 are both fixed on the package substrate 102 and electrically connected to the metal traces 1021 on the package substrate 102 respectively.
  • the metal traces 1021 on the package substrate 102 form a wiring structure, establish a signal path between the data processing chip 101 and the OE2 , and connect the data processing chip 101 and the OE2 to the electrical connection structure 11 .
  • the OE2 can receive and receive optical signals through optical fibers.
  • the optical signal can be transmitted to the OE2 through the optical fiber, the OE2 converts the input optical signal into an electrical signal, and the electrical signal is then transmitted to the data processing chip 101, and the data processing chip 101 performs arithmetic or logical operations on the electrical signal.
  • the data processing chip 101 can also transmit the electrical signal to the OE2, and the OE2 then converts the input electrical signal into an optical signal, and transmits the optical signal out through an optical fiber.
  • the above-mentioned data processing chip 101 is used to process the electrical signal after the photoelectric conversion of the OE2, or to transmit the processed electrical signal to the OE2.
  • the data processing chip 101 may be a system-on-chip, or may be a central processing unit (central processing unit, CPU) chip or the like.
  • the package substrate involved in the present application may be a redistribution layer (RDL) produced by a redistribution process.
  • RDL redistribution layer
  • 6 is a schematic structural diagram of a package substrate, including multi-layer metal traces 1021 and multi-layer dielectric layers 1023. Every two adjacent layers of metal traces 1021 are separated by a dielectric layer 1023, wherein the dielectric layer 1023 can be made of resin. materials and other insulating materials.
  • a conductive channel 1022 may be formed in the dielectric layer 1023 , so that the metal traces 1021 of different layers are electrically connected through the conductive channel 1022 .
  • a package substrate used for packaging chips is a core substrate (Core substrate).
  • the Core substrate includes a substrate 111 in addition to the rewiring structure 112 .
  • the material of the bottom is usually glass, amorphous silicon (a-Si), or silicon carbide (SiC). Due to the existence of the substrate 111, the entire Core substrate will have a larger elastic modulus, that is, the Core substrate will have a larger stiffness.
  • the SMD process is integrated on the Core substrate, since the size of the chip package structure is larger, and the data processing chip 101 and OE2 are more rigid than the Core substrate, in this case, the more rigid data processing chip 101 and OE2 are integrated
  • the core substrate with relatively low rigidity is placed on the core substrate with relatively low rigidity, it is easy to cause large warpage of the core substrate with low rigidity, and a large internal stress is generated in the packaged structure, which affects the performance of the chip package structure. .
  • the packaging substrate used in the present application does not include substrates made of materials such as glass, a-Si, or SiC, so that the elastic modulus of the entire packaging substrate is reduced, that is, the stiffness is weakened. Therefore, the present application is to further reduce the rigidity of the packaging substrate, so that when the data processing chips 101 and OE2 with greater rigidity are integrated on the packaging substrate with flexibility, the warpage of the packaging substrate can be suppressed, the internal stress can be reduced, and the The performance of the entire chip package structure extends the service life.
  • the packaging substrate of the present application can also be a coreless substrate (Coreless substrate).
  • the Coreless substrate relative to the Core substrate, does not include the above-mentioned glass, amorphous silicon (amorphous silicon, a- The substrate made of Si), or silicon carbide (SiC) and other materials only includes the rewiring structure, and the structure of the Coreless substrate is the same as that shown in FIG. 6 . Therefore, the Coreless substrate is also a rewiring layer structure.
  • the OE2 may include an optical chip 21 formed with a photonic integrated circuit and an optical fiber connection structure 23 connected to the optical chip 21 , and the optical chip 21 is electrically connected to the packaging substrate 102 .
  • further processing eg, transformation, amplification, etc.
  • the OE2 may also include an electronic integrated The electrical chip 22 of the circuit.
  • the optical chip 21 and the electrical chip 22 may adopt a three-dimension (3D) integration method.
  • a two-dimension (2D) integration method can also be used.
  • the optical chip 21 and the electrical chip 22 are integrated on the package substrate 102 using 3D.
  • the optical chip 21 and the electrical chip 22 are arranged in a stacked manner, and the optical chip 21 includes a first substrate 211 on which a photonic integrated circuit 212 is formed.
  • the electrical chip 22 includes a second substrate 221 on which an electronic integrated circuit 222 is formed.
  • a light-emitting surface Q is formed on the surface of the photonic integrated circuit 212 .
  • the first substrate 211 can be arranged close to the packaging substrate 102 , and the photonic integrated circuit 212 is located far from the first substrate 211 .
  • the electronic integrated circuit 222 is close to the photonic integrated circuit 212, the second substrate 221 is located on the side of the electronic integrated circuit 222 away from the photonic integrated circuit 212, and the photonic integrated circuit 212 It is electrically connected with the electronic integrated circuit 222 using a flip-chip technology.
  • a first conductive channel 213 is formed in the first substrate 211 through the first substrate 211.
  • One end of the first conductive channel 213 is electrically connected to the photonic integrated circuit 212, and the other end is
  • the solder bumps 6 are electrically connected, and the bumps 6 are then electrically connected to the metal traces of the package substrate 102.
  • the conductive channels and the package substrate can also be electrically connected through other electrical structures. In this way, interconnection of circuits between the photonic integrated circuit 212, the electronic integrated circuit 222, and the packaging substrate 102 is achieved.
  • the first substrate 211 is a silicon substrate made of a semiconductor material with silicon element
  • the first conductive channel 213 formed on the silicon substrate may be called a through silicon via (STV).
  • the interconnection between the optical chip 21 and the electrical chip 22 is vertical interconnection, and the interconnection path is short, so that the The efficiency of signal transmission between the optical chip 21 and the electrical chip 22 can be improved.
  • the optical chip 21 and the electrical chip 22 are 2D integrated on the package substrate 102
  • the optical chip 21 is integrated on the package substrate 102
  • the electrical chip 22 is also integrated on the package substrate 102
  • the photonic integrated circuit 212 of the optical chip 21 is close to the package
  • the substrate 102, the electronic integrated circuits 222 of the electrical chip 22 are also close to the package substrate 102, and the photonic integrated circuits 212 and the electronic integrated circuits 222 are electrically connected by metal traces on the package substrate.
  • the packaging substrate used in this application is a Coreless substrate or RDL with low rigidity, in order to increase the strength of the entire chip packaging structure after packaging, as shown in FIG. , and the data processing chip 101 or OE2 is encapsulated in the plastic packaging layer 7 , thereby increasing the strength of the chip packaging structure, and the plastic packaging layer 7 can also protect the OE2 and the data processing chip 101 .
  • the multiple data processing chips 101 can be integrated on the interconnect substrate 103 to form a Combo die, and the interconnect substrate 103 can be integrated on the packaging substrate 102 , and is electrically connected to the package substrate 102 , so that the plurality of data processing chips 101 are electrically connected to the package substrate 102 and the data processing chips 101 are electrically connected.
  • the interconnection substrate 103 can use RDL.
  • the structure of the RDL is shown in FIG. 6 , that is, it includes multi-layer metal wirings 1021 and multi-layer dielectric layers 1023 . Every two adjacent layers of metal wirings 1021 are separated by the dielectric layer 1023 .
  • a first conductive channel 1022 is formed in the dielectric layer 1023 , and the metal traces 1021 of different layers are electrically connected through the first conductive channel 1022 .
  • the interconnect substrate 103 may also be an interposer.
  • FIG. 10 shows a structural diagram of an interposer, including a third substrate 1031 integrated on the third substrate 1031 The redistribution layer 1033 , and the second conductive channel 1032 penetrating through the third substrate 1031 , and the second conductive channel 1032 is electrically connected to the metal traces in the redistribution layer 1033 .
  • the third substrate 1031 is a silicon substrate made of a semiconductor material with silicon element
  • the interposer becomes a Si Interposer.
  • the redistribution layer 1033 is close to the combination chip and can be electrically connected with each data processing chip through bumps
  • the third substrate 1031 is close to the package substrate and can pass through the second conductive channel 1032 and The bumps are electrically connected to metal traces in the package substrate.
  • a glue dispensing process may be used to fill underfill 8 between the interconnection substrate 103 and the package substrate 102 .
  • primer can also be filled between the OE2 and the packaging substrate 102 .
  • any data processing chip in the embodiments of the present application includes a substrate and a metal layer.
  • both data processing chips 101 include a fourth substrate 1011 and a metal layer 1012 , and the metal layer 1012 forms a circuit structure.
  • the metal layer 1012 is close to the interconnection substrate 103 and is electrically connected to the interconnection substrate 103 through the bumps 6 , and the fourth substrate 1011 is located on the side of the metal layer 1012 away from the interconnection substrate 103 .
  • the OE2 may also include multiple ones, which are used for processing different kinds of electrical signals in cooperation with the data processing chip.
  • the arrangement positions of the data processing chips 101 and OE2 on the package substrate 102 have various situations. Illustratively, as shown in FIG. 9 , the data processing chip 101 and the OE2 are located on the same surface of the package substrate 102 . As another example, as shown in FIG. 14 , the data processing chip 101 and the OE2 are located on two opposite surfaces of the package substrate 102 .
  • the data processing chip 101 and the OE2 can be integrated on the same surface of the package substrate 102 .
  • the data processing chip 101 and OE2 are integrated on two opposite surfaces of the packaging substrate 102 to make full use of the two opposite surfaces of the packaging substrate. area.
  • FIG. 12 shows the layout on the first surface A1 in one embodiment.
  • Structure diagram FIG. 13 is a layout structure diagram on the second surface A2. It can be seen that both the OE2 and the data processing chip 101 are integrated on the first surface A1.
  • the data processing chip 101 is arranged close to the central area of the first surface A1, and a plurality of OEs are arranged along the periphery of the first surface A1 at intervals.
  • the advantages of multiple OE2 being spaced along the periphery of the first surface A1 are: it is convenient for the optical fiber connecting structure to connect with the external light source through the optical fiber, thereby reducing the processing difficulty and shortening the transmission path from the OE to the light source.
  • connection terminals 13 may also be arranged, and the connection terminals 13 are electrically connected to chips on the PCB or other semiconductor structures.
  • a power supply chip can also be integrated on the second surface A2.
  • other chips can also be integrated on the second surface A2.
  • a plastic sealing layer 7 may be provided on the first surface A1, so that the plastic sealing layer 7 wraps around the OE2 and the data processing chip 101 , and further protect and reinforce the OE2 and the data processing chip 101 .
  • a channel 19 is formed on the plastic sealing layer 7 to penetrate to the light-emitting surface Q.
  • the optical fiber connecting structure 23 passes through the channel 19 and Connect to the light-emitting surface Q.
  • FIG. 15 is a layout structure diagram on the first surface A1 in another embodiment
  • FIG. 16 is a layout structure diagram on the second surface A2.
  • the data processing chip 101 is integrated on the first surface A1, and the data processing chip 101 is arranged close to the central area of the first surface A1.
  • a plurality of dummy structures 12 are also arranged on the first surface A1, and the plurality of dummy structures 12 are arranged along the periphery of the first surface A1.
  • the OE2 is integrated on the second surface A2, and a plurality of OE2 are arranged at intervals along the periphery of the second surface A2.
  • connecting terminals 13 can also be arranged on the second surface A2, and the connecting terminals 13 can be electrically connected to chips on the PCB or other semiconductor structures, and a power supply chip 14 can also be integrated on the second surface A2.
  • the above-mentioned dummy structure 12 may be a dummy die obtained after wafer dicing, or may be other structures made of other materials, such as glass blocks. If a bare chip is used, the process flow is relatively simple, the process flow is relatively mature, and the manufacturing cost is also low.
  • a plastic sealing layer 7 may be provided on the first surface A1, so that the plastic sealing layer 7 is wrapped around the data processing chip 101 and the dummy structure.
  • the periphery of the structure 12 is further protected and strengthened for the data processing chip 101 and the dummy structure 12 .
  • the plastic encapsulation layer 7 has been arranged on the first surface A1, the strength of the entire chip packaging structure can already meet the requirements for use. In this way, the second surface A2 where the OE2 is located may not have a plastic encapsulation layer.
  • the plastic layer can also be arranged.
  • a plastic encapsulation layer is provided on the second surface A2 where the OE2 is located, the same as the structure described above in FIG. 9 , a channel 19 is formed on the plastic encapsulation layer 7 penetrating to the light emitting surface Q, and the optical fiber connecting structure 23 passes through the channel 19 and connect with the light-emitting surface Q.
  • the chip packaging structure may also include a heat sink.
  • a conductive material layer 92 is coated on the surface of the data processing chip 101 away from the packaging substrate 102 ,
  • the heat dissipation plate 91 covers the thermally conductive material layer 92 .
  • the heat generated by the data processing chip 101 can be introduced to the heat dissipation plate 91 to dissipate heat through the heat dissipation plate 91 .
  • a thermally conductive material layer 92 is also coated on the surface of the OE2 away from the package substrate 102, and the heat dissipation plate 91 extends to the thermally conductive material layer 92 on the surface of the OE2.
  • the heat dissipation plate 91 not only plays a role of heat dissipation, but also can improve the strength of the entire chip package structure.
  • the embodiment of the present application also provides a method for preparing a chip packaging structure, as shown in FIG. 17 , the preparation method includes:
  • Step S1 forming an encapsulation substrate on the support plate, and the encapsulation substrate is a rewiring layer.
  • the structure of the formed redistribution layer is shown in FIG. 6 , that is, it includes: multi-layer metal traces 1021 , multi-layer dielectric layers 1023 and conductive channels 1022 , and every two adjacent layers of metal traces 1021 are separated by the dielectric layer 1023 , the conductive channel 1022 passes through the dielectric layer 1023 and is electrically connected to the metal traces 1021 of different layers.
  • the package substrate may also be a Coreless substrate, and the structures of the Coreless substrate and the redistribution layer are the same, but differ in manufacturing processes.
  • the package substrate uses a less rigid Coreless substrate or rewiring layer, if the optical engine and data processing chip are directly integrated on the coreless substrate or rewiring layer, the processing technology is more difficult.
  • the coreless substrate or the rewiring layer is arranged on the support plate, and the integration difficulty of the optical chip and the data processing chip can be reduced by using the support function of the support plate.
  • Step S2 Integrate at least one light engine and at least one data processing chip on the packaging substrate, and are respectively electrically connected to the packaging substrate, and form a plastic packaging layer on the surface of the packaging substrate, so that the data processing chip and/or the light engine are It is wrapped in a plastic packaging layer, and the light-emitting surface of the optical chip of the light engine is exposed, and the support plate is removed to obtain a chip packaging structure.
  • the specific forming process may include:
  • a metal layer is formed on the substrate, and metal wires are etched on the metal layer to form a first layer of metal wires.
  • a first dielectric layer is formed on the substrate on which the first layer of metal traces are formed.
  • Conductive vias are formed in the first dielectric layer.
  • a metal layer is formed on the first dielectric layer, and metal traces are etched on the metal layer to form a second layer of metal traces, and conductive channels are electrically connected to the first layer of metal traces and the second layer Metal traces.
  • step S1 when the package substrate formed is a coreless substrate, the coreless substrate that has been produced can be directly bonded to the support plate.
  • the coreless substrate can be prepared by the semi-additive method (SAP), which specifically includes:
  • a dielectric layer is laminated on the metal layer on which the metal pillars are formed.
  • a metal layer is laminated on the dielectric layer.
  • the metal layers on both sides of the dielectric layer are etched to form metal traces.
  • the package substrate When there are a plurality of data processing chips, before integrating the data processing chips on the package substrate, it also includes:
  • a plurality of data processing chips are integrated on the interconnection substrate and electrically connected with the interconnection substrate.
  • the interconnect substrate may be a redistribution layer or an interposer.
  • the redistribution layer can be prepared by the above method, but the substrate needs to be etched away before being electrically connected with the package substrate.
  • the light engine of the embodiment of the present application includes at least an optical chip and an optical fiber connection structure connected to the light-emitting surface of the optical chip.
  • the light engine is integrated on the packaging substrate, and the following steps may be included when forming the plastic packaging layer:
  • the at least one optical chip is integrated on the packaging substrate, and the light-emitting surface of the optical chip faces away from the packaging substrate.
  • the base side of the optical chip faces the packaging substrate, and the photonic integrated circuit side of the optical chip faces away from the packaging substrate, so that the light emitting surface of the optical chip can be turned away from the packaging substrate.
  • the light engine further includes an electrical chip
  • the optical chip and the electrical chip are three-dimensionally stacked
  • the integrated optical chip and the electrical chip can be integrated on the packaging substrate.
  • the electrical chip is stacked with the optical chip, the light emitting surface of the optical chip cannot be blocked.
  • the optical fiber connection structure In order to avoid covering the light-emitting surface Q when the plastic encapsulation layer is subsequently formed, the optical fiber connection structure cannot be connected.
  • a plastic packaging layer is formed on the packaging substrate, so that the plastic packaging layer wraps the optical chip and the periphery of the temporary dummy block, and the surface of the temporary dummy structure is exposed outside the plastic packaging layer.
  • the temporary dummy structure may be a bare chip, or a structure made of glass or metal materials.
  • the temporary dummy structure is removed to form a channel on the plastic encapsulation layer through to the light emitting surface.
  • the optical interface of the optical fiber connecting structure is joined to the light-emitting surface through transparent glue, and then the optical fiber connecting structure is fixed on the light-emitting surface along the outer edge of the optical interface with reinforcing glue.
  • the present application provides two alternative embodiments of the method for manufacturing the chip package structure, which will be described in detail below.
  • FIG. 18 is a flowchart of this embodiment
  • FIG. 19 is a structural diagram of each step corresponding to FIG. 18 .
  • the preparation method includes the following steps:
  • step S101 in FIG. 18 and 19 b in FIG. 19 the package substrate 102 is formed on the support plate 15 .
  • step S102 in FIG. 18 and 19b in FIG. 19 at least one optical chip 21 and at least one data processing chip 101 are integrated on the surface of the package substrate 102 , and the light emitting surface Q of the optical chip 21 faces away from the package substrate 102 .
  • the chip package structure prepared by the preparation method shown in FIG. 19 includes a plurality of data processing chips. Therefore, as shown in 19a of FIG. 19 , the plurality of data processing chips 101 are first integrated on the interconnection substrate 103 to form a combined chip, The combined chip is then integrated on the package substrate 102 . The combined chip may be disposed near the center area of the package substrate 102 .
  • the multiple optical chips 21 are arranged at intervals along the periphery of the packaging substrate, and it is necessary to make the light-emitting surface of the optical chips close to the outer edge of the packaging substrate.
  • a plastic encapsulation layer 7 can also be formed on the interconnection substrate 103 with the data processing chips 101, and after the plastic encapsulation layer is completed, it is necessary to The plastic sealing layer is ground and polished to expose the surface of the data processing chip 101 .
  • the OE of FIG. 19 includes not only the optical chip 21 , but also the electrical chip 22 three-dimensionally stacked with the optical chip 21 .
  • the electrical chip 22 and the optical chip 21 are stacked as a whole, and then the whole is disposed on the packaging substrate 102 .
  • the data processing chip can be integrated in the central area of the package substrate first, and then the plurality of optical chips can be integrated on the edge of the package substrate.
  • a temporary dummy structure 16 is used to cover the light-emitting surface Q.
  • a plastic packaging layer 7 is formed on the packaging substrate, so that the plastic packaging layer 7 wraps the periphery of the optical chip and the data processing chip.
  • the plastic encapsulation layer 7 also needs to wrap around the periphery of the electrical chip 22 .
  • a plastic encapsulation layer is formed by a deposition process.
  • the surfaces of the data processing chip 101 and the electrical chip 22 and the temporary dummy structure 16 are also covered with a plastic encapsulation layer.
  • the surface of the temporary dummy structure 16 is subjected to chemical mechanical polishing to remove the redundant plastic packaging layer, so as to expose the surface of the data processing chip 101 , the electrical chip 22 , and the temporary dummy structure 16 and make the surface flat.
  • step S105 in FIG. 18 and step 19e in FIG. 19 the temporary dummy structure 16 is removed to form a channel 17 on the plastic sealing layer penetrating to the light-emitting surface.
  • the support plate 15 is removed.
  • the support plate 15 may be removed using a mechanical grinding or laser cutting process.
  • Step S107 in FIG. 18 and 19f in FIG. 19 the heat dissipation plate 92 is provided.
  • the conductive material layer 92 is first coated on the surface of the plastic sealing layer, and then the heat dissipation plate 91 is covered on the conductive material layer 92 . Since the plastic packaging layers on the surfaces of the data processing chip 101 and the electrical chip 22 have been removed, the conductive material layer 92 is directly attached to the surfaces of the two chips, which improves the heat dissipation effect.
  • the optical fiber connection structure 23 is passed through the channel and connected to the light-emitting surface. Finally, a chip package structure in which the data processing chip and the OE are located on the same surface of the package substrate is obtained.
  • the above is to remove the support plate 15 after removing the temporary dummy structure 16 .
  • the temporary dummy structure 16 can also be removed, and after connecting the optical fiber connecting structure 23 to the light-emitting surface, the support plate 15 can be removed.
  • connection terminals may also be provided on the package substrate, or a power supply chip may also be provided. And the connection terminal and the power supply chip are located on the other side of the package substrate opposite to the data processing chip.
  • FIG. 20 is a flowchart of this embodiment
  • FIG. 21 is a structural diagram of each step corresponding to FIG. 20 .
  • the preparation method includes the following steps:
  • the package substrate 102 is formed on the support plate 15 .
  • step S202 in FIG. 20 and 21 b in FIG. 21 at least one data processing chip 101 and at least one dummy structure 12 are integrated on the surface of the package substrate 102 .
  • This embodiment is the same as the method shown in FIG. 19 described above, and may include multiple data processing chips. Therefore, as shown in 21a of FIG. 21 , multiple data processing chips 101 are first integrated on the interconnect substrate 103 to form a combined chip, The combined chip is then integrated on the package substrate 102 .
  • the multiple dummy structures 12 are arranged along the periphery of the package substrate.
  • a plastic packaging layer 7 is formed on the packaging substrate, so that the plastic packaging layer 7 wraps around the dummy structure 12 and the periphery of the data processing chip 101 .
  • the surfaces of the data processing chip 101 and the dummy structure 12 will also be covered with a plastic encapsulation layer. Therefore, it is necessary to perform chemical mechanical polishing on the surfaces of the data processing chip 101 and the dummy structure 12 to remove the redundant plastic encapsulation layer so that the data The surfaces of the handle chip 101 and the dummy structure 12 are exposed.
  • step S204 in FIG. 20 and 21 d in FIG. 21 the support plate 15 is removed.
  • Step S205 in FIG. 20, 21f in FIG. 21, integrate at least one light engine 2 on the other surface of the package substrate 102, so that the light engine and the data processing chip are located on two opposite surfaces of the package substrate.
  • the plurality of light engines 2 may be arranged at intervals along the periphery of the packaging substrate.
  • a plastic encapsulation layer is formed on one surface of the package substrate, that is, the surface with the data processing chip and the dummy structure, the plastic encapsulation layer can reinforce and increase the strength of the final chip encapsulation structure.
  • No plastic encapsulation layer is formed on the other surface, that is, the surface with the light engine. In order to further increase the strength, a plastic encapsulation layer can also be formed.
  • the specific method of disposing the light engine on the other surface is the same as the method mentioned above, and will not be repeated here.
  • the OE of the integrated optical chip, the electrical chip and the optical fiber connection structure can be connected to the packaging substrate, or the integrated optical chip and the electrical chip can be connected to the package first.
  • the substrate is connected, and then the optical fiber connection structure is connected to the light-emitting surface of the optical chip.
  • connection terminals 13 and power supply chips can be arranged in the central area of the package substrate before step S205, 21e in FIG. 21 14, and then execute step S205.
  • the heat dissipation plate 92 is provided.
  • the heat dissipation plate 92 may be installed after the installation of the light engine 2 , the connection terminals 13 and the power supply chip 14 is completed.
  • the package substrate adopts Coreless substrate or RDL, when each chip is integrated on the package substrate, the degree of warpage will be weakened due to the greater flexibility of the package substrate.
  • the rigidity of the package substrate is weakened, by forming a plastic encapsulation layer in the present application, the strength and rigidity of the finally prepared chip package structure can meet the requirements for use.

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Abstract

Embodiments of the present application relate to the technical field of chip packaging and provided therein are a chip packaging structure, an electronic device, and a method for preparing a chip packaging structure. The chip packaging structure comprises: a packaging substrate, a plastic packaging layer, at least one optical engine, and at least one data processing chip. The packaging substrate is a rewiring layer; the optical engines each comprises an optical fiber connection structure and an optical chip constituting a photonic integrated circuit, the optical chip and the data processing chip being integrated on the same surface of the packaging substrate and being respectively electrically connected to the packaging substrate, a light emitting surface of the optical chip being located on a side facing away from the packaging substrate; and the plastic packaging layer is located on the surface of the packaging substrate on which the optical chip and the data processing chip are integrated, and is wrapped around the optical chip and the data processing chip, and the plastic packaging layer has a channel that penetrates to the light emitting surface, and the optical fiber connection structure passes through the channel and is connected to the light emitting surface.

Description

一种芯片封装结构、电子设备及芯片封装结构的制备方法A chip packaging structure, an electronic device, and a preparation method of the chip packaging structure 技术领域technical field
本申请涉及芯片封装技术领域，尤其涉及一种芯片封装结构、电子设备及芯片封装结构的制备方法。The present application relates to the technical field of chip packaging, and in particular, to a chip packaging structure, an electronic device and a method for preparing the chip packaging structure.
背景技术Background technique
芯片出光技术是通信领域发展的未来，因为光传输具有传输效率高、传输损耗小、抗射频干扰和抗电磁干扰等特性。芯片出光技术一般应用在具有超大容量的，且封装尺寸较大的芯片封装结构中，这样，传输效率高、传输损耗小等优点体现的更加突出。The chip light-emitting technology is the future of the development of the communication field, because the optical transmission has the characteristics of high transmission efficiency, low transmission loss, anti-radio frequency interference and anti-electromagnetic interference. The chip light extraction technology is generally used in the chip package structure with super large capacity and large package size. In this way, the advantages of high transmission efficiency and low transmission loss are more prominent.
图1所示的是一种应用了芯片出光技术的芯片封装结构的示意图，其中，多个***级芯片(System-on-a-chip，SOC)3和多个光引擎(Optical Engine，OE)2均集成在封装基板1上，光引擎可以通过光纤与外置在该芯片封装结构外部的光源连接。Fig. 1 is a schematic diagram of a chip packaging structure applying the chip light extraction technology, wherein, multiple system-on-a-chip (SOC) 3 and multiple optical engines (Optical Engine, OE) 2 are integrated on the package substrate 1, and the light engine can be connected to a light source outside the chip package structure through an optical fiber.
如图2所示，该封装基板1包括衬底111、位于衬底111上表面和下表面的重新布线结构112。As shown in FIG. 2 , the package substrate 1 includes a substrate 111 , and rewiring structures 112 located on the upper surface and the lower surface of the substrate 111 .
图3为图1的中的芯片封装结构的装配图。如图3所示，封装基板1被设置在印制电路板5上，并与印制电路板5电连接，其中，光引擎2可以包括构成有光子集成电路((Photonic IC，PIC))的光芯片21、与光芯片21连接的光纤连接结构(Fiber Attach Unit，FAU)23，也可以还包括与光芯片21电连接的且构成有电子集成电路(Electrical IC，EIC)的电芯片22。光芯片21和***级芯片3采用倒装贴装工艺被设置在封装基板1上，如图3所示，光芯片21和***级芯片3的底部通过凸点6焊接在封装基板1上，并通过金属走线112将光芯片201和***级芯片3电连接。FIG. 3 is an assembly diagram of the chip package structure in FIG. 1 . As shown in FIG. 3 , the package substrate 1 is disposed on the printed circuit board 5 and is electrically connected to the printed circuit board 5 , wherein the light engine 2 may include a photonic integrated circuit ((Photonic IC, PIC)) The optical chip 21, the optical fiber connection structure (Fiber Attach Unit, FAU) 23 connected to the optical chip 21, may also include an electrical chip 22 that is electrically connected to the optical chip 21 and is formed with an electronic integrated circuit (Electrical IC, EIC). The optical chip 21 and the system-on-chip 3 are arranged on the package substrate 1 using a flip-chip mounting process. As shown in FIG. 3 , the bottoms of the optical chip 21 and the system-on-chip 3 are soldered on the package substrate 1 through bumps 6 , and The optical chip 201 and the system-on-chip 3 are electrically connected through the metal wires 112 .
该芯片封装结构通常采用倒装芯片贴装工艺或者表面贴装工艺(surface mount，SMT)制得，结合图3，在将各个芯片(包含光芯片和***级芯片)与封装基板1焊接时，会导致整个芯片封装结构在完成封装后，产生较大的翘曲现象，以及产生较大的封装内应力。这样，整个芯片封装结构的可靠性会大幅下降，无法使该芯片封装结构满足寿命要求。The chip package structure is usually made by flip-chip mounting process or surface mount process (SMT). This will lead to a large warpage phenomenon and a large internal package stress after the entire chip package structure is packaged. In this way, the reliability of the entire chip package structure will be greatly reduced, and the chip package structure cannot meet the service life requirement.
发明内容SUMMARY OF THE INVENTION
本申请的实施例提供一种芯片封装结构、电子设备及芯片封装结构的制备方法，主要用于降低芯片翘曲程度、减小封装内应力。Embodiments of the present application provide a chip package structure, an electronic device, and a method for preparing the chip package structure, which are mainly used to reduce the warpage degree of the chip and reduce the internal stress of the package.
为达到上述目的，本申请的实施例采用如下技术方案：To achieve the above object, the embodiments of the present application adopt the following technical solutions:
第一方面，本申请提供了一种芯片封装结构，该芯片封装结构包括：封装基底、塑封层、至少一个光引擎、至少一个数据处理芯片；封装基底为重新布线层，光引擎包括光纤连接结构，以及构成有光子集成电路的光芯片，光芯片和数据处理芯片均集成在封装基底的同一表面上，并分别与封装基底电连接，且光芯片的出光面位于背离封装基底的一侧；塑封层位于封装基底的集成有光芯片和数据处理芯片的表面上，并包裹光芯片和数据处理芯片，塑封层具有贯通至出光面的通道，光纤连接结构穿过通道与出光面连接。In a first aspect, the present application provides a chip packaging structure, the chip packaging structure includes: a packaging substrate, a plastic packaging layer, at least one optical engine, and at least one data processing chip; the packaging substrate is a rewiring layer, and the optical engine includes an optical fiber connection structure , and an optical chip composed of a photonic integrated circuit, the optical chip and the data processing chip are integrated on the same surface of the packaging substrate, and are respectively electrically connected to the packaging substrate, and the light-emitting surface of the optical chip is located on the side away from the packaging substrate; plastic packaging The layer is located on the surface of the packaging substrate integrated with the optical chip and the data processing chip, and wraps the optical chip and the data processing chip.
本申请实施例提供的芯片封装结构，由于用于承载光芯片和数据处理芯片的封装基底采用的是重新布线层，重新布线层相比有芯基板(Core基板)，弹性模量减小，刚度降低。这样的话，在保障芯片封装结构的整体强度的前提下，会有效降低整个芯片封装结构的翘曲程度，以及也会减小芯片封装结构的封装内应力，提高芯片封装结构的性能，延长使用寿命。另外，通过在塑封层形成贯通至光芯片的出光面的通道，可保障光纤连接结构与出光面的连接。In the chip packaging structure provided by the embodiment of the present application, since the packaging substrate used to carry the optical chip and the data processing chip adopts a rewiring layer, the rewiring layer has a lower elastic modulus and lower rigidity than a core substrate (Core substrate). reduce. In this way, under the premise of ensuring the overall strength of the chip packaging structure, the warpage of the entire chip packaging structure will be effectively reduced, and the packaging internal stress of the chip packaging structure will also be reduced, the performance of the chip packaging structure will be improved, and the service life will be prolonged. . In addition, the connection between the optical fiber connection structure and the light emitting surface can be ensured by forming a channel through the plastic sealing layer to the light emitting surface of the optical chip.
在第一方面可能的实现方式中，数据处理芯片靠近封装基底的中心区域设置，光引擎具有多个，多个光引擎沿封装基底的周边布设。In a possible implementation manner of the first aspect, the data processing chip is disposed close to a central area of the package substrate, there are multiple light engines, and the multiple light engines are arranged along the periphery of the package substrate.
在第一方面可能的实现方式中，芯片封装结构还包括互连基底；数据处理芯片具有多个，多个数据处理芯片集成在互连基底上，并与互连基底电连接，互连基底设置在封装基底上并与封装基底电连接。通过将多个数据处理芯片集成在互连基底上，并将互连基底集成在封装基底上，并与封装基底电连接，可以实现数据处理芯片之间的互连。In a possible implementation manner of the first aspect, the chip packaging structure further includes an interconnection substrate; the data processing chip has a plurality of data processing chips, the plurality of data processing chips are integrated on the interconnection substrate, and are electrically connected to the interconnection substrate, and the interconnection substrate is provided with on and in electrical connection with the package substrate. By integrating a plurality of data processing chips on the interconnecting substrate, and integrating the interconnecting substrate on the packaging substrate and electrically connecting with the packaging substrate, the interconnection between the data processing chips can be realized.
在第一方面可能的实现方式中，互连基底为重新布线层或者转接板。In a possible implementation manner of the first aspect, the interconnection substrate is a rewiring layer or an interposer board.
在第一方面可能的实现方式中，芯片封装结构还包括连接端子；连接端子设置在封装基底的与数据处理芯片相对的表面上。In a possible implementation manner of the first aspect, the chip packaging structure further includes connection terminals; the connection terminals are arranged on a surface of the packaging substrate opposite to the data processing chip.
第二方面，本申请提供了一种芯片封装结构，该芯片封装结构包括：封装基底、塑封层、至少一个光引擎、至少一个数据处理芯片，光引擎和数据处理芯片集成在封装基底的相对的两表面上，并分别与封装基底电连接，塑封层位于封装基底的具有数据处理芯片的表面上，并包裹数据处理芯片。In a second aspect, the application provides a chip packaging structure, the chip packaging structure includes: a packaging substrate, a plastic packaging layer, at least one optical engine, and at least one data processing chip, wherein the optical engine and the data processing chip are integrated on opposite sides of the packaging substrate. on the two surfaces and are respectively electrically connected with the packaging substrate, the plastic packaging layer is located on the surface of the packaging substrate with the data processing chip, and wraps the data processing chip.
本申请实施例提供的芯片封装结构，由于用于承载光芯片和数据处理芯片的封装基底采用的是重新布线层，重新布线层相比Core基板，弹性模量减小，刚度降低。这样的话，在保障芯片封装结构的整体强度的前提下，会有效降低整个芯片封装结构的翘曲程度，以及也会减小芯片封装结构的封装内应力，提高芯片封装结构的性能，延长使用寿命。In the chip packaging structure provided by the embodiments of the present application, since the packaging substrate for carrying the optical chip and the data processing chip adopts a rewiring layer, the rewiring layer has a lower elastic modulus and lower rigidity than the Core substrate. In this way, under the premise of ensuring the overall strength of the chip packaging structure, the warpage of the entire chip packaging structure will be effectively reduced, and the packaging internal stress of the chip packaging structure will also be reduced, the performance of the chip packaging structure will be improved, and the service life will be prolonged. .
在第二方面可能的实现方式中，芯片封装结构还包括多个虚设结构；多个虚设结构和数据处理芯片位于封装基底的同一表面上，且虚设结构被包裹在塑封层内，数据处理芯片靠近封装基底的中心区域设置，多个虚设结构沿封装基底的周边布设。通过在封装基底的具有数据处理芯片的侧面设置虚设结构，可以防止在一个侧面仅设置数据处理芯片时，导致发生翘曲现象。In a possible implementation manner of the second aspect, the chip packaging structure further includes a plurality of dummy structures; the plurality of dummy structures and the data processing chips are located on the same surface of the packaging substrate, and the dummy structures are encapsulated in the plastic packaging layer, and the data processing chips are close to A central area of the package substrate is provided, and a plurality of dummy structures are arranged along the periphery of the package substrate. By arranging the dummy structure on the side of the package substrate having the data processing chip, warpage can be prevented when only the data processing chip is arranged on one side.
在第二方面可能的实现方式中，虚设结构为裸芯片。采用裸芯片作为虚设结构，可简化制造工艺，降低制造成本。In a possible implementation manner of the second aspect, the dummy structure is a bare chip. Using the bare chip as the dummy structure can simplify the manufacturing process and reduce the manufacturing cost.
在第二方面可能的实现方式中，芯片封装结构还包括互连基底；数据处理芯片具有多个，多个数据处理芯片集成在互连基底上，并与互连基底电连接，互连基底设置在封装基底上并与封装基底电连接。通过将多个数据处理芯片集成在互连基底上，并将互连基底集成在封装基底上，并与封装基底电连接，可以实现数据处理芯片之间的互连。In a possible implementation manner of the second aspect, the chip packaging structure further includes an interconnection substrate; the data processing chip has a plurality of data processing chips, the plurality of data processing chips are integrated on the interconnection substrate, and are electrically connected to the interconnection substrate, and the interconnection substrate is provided with on and in electrical connection with the package substrate. By integrating a plurality of data processing chips on the interconnecting substrate, and integrating the interconnecting substrate on the packaging substrate and electrically connecting with the packaging substrate, the interconnection between the data processing chips can be realized.
在第二方面可能的实现方式中，互连基底为重新布线层或者转接板。In a possible implementation manner of the second aspect, the interconnection substrate is a redistribution layer or an interposer board.
在第二方面可能的实现方式中，芯片封装结构还包括连接端子：连接端子和光引 擎位于封装基底的同一表面上。In a possible implementation manner of the second aspect, the chip package structure further includes connection terminals: the connection terminals and the light engine are located on the same surface of the package substrate.
在第二方面可能的实现方式中，芯片封装结构还包括供电芯片；供电芯片和连接端子位于封装基底的同一表面上。In a possible implementation manner of the second aspect, the chip packaging structure further includes a power supply chip; the power supply chip and the connection terminals are located on the same surface of the package substrate.
第三方面，本申请实施例还提供了一种芯片封装的制备方法，该制备方法包括：In a third aspect, an embodiment of the present application further provides a method for preparing a chip package, the method comprising:
在支撑板上形成封装基底，封装基底为无芯基板或者重新布线层；A package base is formed on the support plate, and the package base is a coreless substrate or a rewiring layer;
将至少一个光引擎，以及至少一个数据处理芯片集成在封装基底上，且分别与封装基底电连接，在封装基底的表面上形成塑封层，以使数据处理芯片和/或光引擎被包裹在塑封层内，且使光引擎的光芯片的出光面裸露，并移除支撑板，得到芯片封装结构。Integrate at least one light engine and at least one data processing chip on the packaging substrate, and are respectively electrically connected to the packaging substrate, and a plastic sealing layer is formed on the surface of the packaging substrate, so that the data processing chip and/or the light engine are wrapped in the plastic packaging. In the layer, the light-emitting surface of the optical chip of the light engine is exposed, and the support plate is removed to obtain a chip package structure.
本申请实施例提供的芯片封装的制备方法中，由于用于承载光引擎和数据处理芯片的封装基底采用的是重新布线层，这样的话，在将光引擎和数据处理芯片与封装基底电连接，会有效的降低翘曲的程度，最终也会减小制得的芯片封装结构的封装内应力，且塑封层会保障最终制得的芯片封装结构的强度。In the preparation method of the chip package provided by the embodiment of the present application, since the package substrate used to carry the optical engine and the data processing chip adopts a rewiring layer, in this case, when the optical engine and the data processing chip are electrically connected to the package substrate, The degree of warpage can be effectively reduced, and the encapsulation internal stress of the prepared chip package structure can also be finally reduced, and the plastic encapsulation layer can ensure the strength of the finally prepared chip package structure.
在第三方面可能的实现方式中，光引擎至少包括光纤连接结构，以及集成有光子集成电路的光芯片；将至少一个光引擎集成在封装基底上，以及在具有光引擎的封装基底上形成塑封层包括：将至少一个光芯片集成在封装基底上，且使光芯片的出光面背离封装基底；采用临时虚设结构覆盖住出光面；在封装基底上形成塑封层，以使塑封层包裹光芯片和临时虚设结构的周边，并使临时虚设结构的表面外露在塑封层的外部；移除临时虚设结构，以在塑封层上形成贯通至出光面的通道；将光纤连接结构穿过通道并与出光面连接。在形成塑封层时，为了避免塑封层盖住光芯片的出光面，可以在形成塑封层之前，采用临时虚设结构将出光面盖住，再制备塑封层。In a possible implementation manner of the third aspect, the optical engine includes at least an optical fiber connection structure, and an optical chip integrated with a photonic integrated circuit; at least one optical engine is integrated on a packaging substrate, and a plastic package is formed on the packaging substrate with the optical engine The layer includes: integrating at least one optical chip on the packaging substrate, and making the light-emitting surface of the optical chip away from the packaging substrate; covering the light-emitting surface with a temporary dummy structure; forming a plastic sealing layer on the packaging substrate so that the plastic packaging layer wraps the optical chip and the packaging substrate. The periphery of the temporary dummy structure, and the surface of the temporary dummy structure is exposed to the outside of the plastic sealing layer; the temporary dummy structure is removed to form a channel through the plastic sealing layer to the light-emitting surface; the optical fiber connecting structure is passed through the channel and is connected with the light-emitting surface connect. When the plastic sealing layer is formed, in order to prevent the plastic sealing layer from covering the light-emitting surface of the optical chip, a temporary dummy structure can be used to cover the light-emitting surface before the plastic sealing layer is formed, and then the plastic sealing layer is prepared.
在第三方面可能的实现方式中，将至少一个光引擎，以及至少一个数据处理芯片集成在封装基底上，并分别与封装基底电连接，在封装基底上形成塑封层，以使数据处理芯片和/或光引擎被包裹在塑封层内，并移除支撑板，包括：将至少一个光芯片，以及至少一个数据处理芯片集成在封装基底的同一表面上；在封装基底的具有光引擎和数据处理芯片的表面上形成塑封层，以使塑封层包裹光引擎和数据处理芯片，且使光引擎的光芯片的出光面裸露在塑封层的外部；移除支撑板，得到芯片封装结构。In a possible implementation manner of the third aspect, at least one light engine and at least one data processing chip are integrated on the packaging substrate, and electrically connected to the packaging substrate respectively, and a plastic packaging layer is formed on the packaging substrate, so that the data processing chip and the packaging substrate are electrically connected to each other. /or the light engine is encapsulated in a plastic encapsulation layer, and the support plate is removed, including: integrating at least one light chip and at least one data processing chip on the same surface of the package substrate; having the light engine and data processing on the package substrate A plastic packaging layer is formed on the surface of the chip, so that the plastic packaging layer wraps the light engine and the data processing chip, and the light emitting surface of the optical chip of the light engine is exposed outside the plastic packaging layer; the support plate is removed to obtain the chip packaging structure.
在第三方面可能的实现方式中，将至少一个光引擎，以及至少一个数据处理芯片集成在封装基底上，并分别与封装基底电连接，在封装基底上形成塑封层，以使数据处理芯片和/或光引擎被包裹在塑封层内，并移除支撑板，包括：将至少一个数据处理芯片集成在封装基底的表面上；在封装基底的具有数据处理芯片的表面上形成塑封层；移除支撑板；将至少一个光引擎集成在封装基底的另一表面上，以使光引擎和数据处理芯片位于封装基底的相对的两表面上，得到芯片封装结构。In a possible implementation manner of the third aspect, at least one light engine and at least one data processing chip are integrated on the packaging substrate, and electrically connected to the packaging substrate respectively, and a plastic packaging layer is formed on the packaging substrate, so that the data processing chip and the packaging substrate are electrically connected to each other. /or the light engine is encapsulated in a plastic encapsulation layer, and the support plate is removed, including: integrating at least one data processing chip on the surface of the package substrate; forming a plastic encapsulation layer on the surface of the package substrate with the data processing chip; removing A support plate; at least one light engine is integrated on the other surface of the package substrate, so that the light engine and the data processing chip are located on two opposite surfaces of the package substrate to obtain a chip package structure.
在第三方面可能的实现方式中，将至少一个数据处理芯片集成在封装基底的表面上时包括：将至少一个数据处理芯片和多个虚设结构均集成在封装基底的表面上，且数据处理芯片靠近封装基底的中心区域设置，多个虚设结构沿封装基底的周边布设。通过在封装基底的集成数据处理芯片的表面上也集成多个虚设结构，可降低在集成数据处理芯片时，导致翘曲现象。In a possible implementation manner of the third aspect, integrating the at least one data processing chip on the surface of the packaging substrate includes: integrating the at least one data processing chip and a plurality of dummy structures on the surface of the packaging substrate, and the data processing chip It is disposed close to the central area of the package substrate, and a plurality of dummy structures are arranged along the periphery of the package substrate. By also integrating a plurality of dummy structures on the surface of the integrated data processing chip of the package substrate, the warpage phenomenon caused when the data processing chip is integrated can be reduced.
在第三方面可能的实现方式中，在数据处理芯片包括多个时；在将数据处理芯片 集成在封装基底上之前，制备方法还包括：将多个数据处理芯片集成在互连基底上，并与互连基底电连接，以使集成有多个数据处理芯片的互连基底集成在封装基底上。当数据处理芯片具有多个时，可以将多个数据处理芯片先集成在互连基底上，再将互连基底集成在封装基底上。In a possible implementation manner of the third aspect, when there are multiple data processing chips; before integrating the data processing chips on the packaging substrate, the preparation method further includes: integrating the multiple data processing chips on the interconnect substrate, and It is electrically connected with the interconnection substrate, so that the interconnection substrate integrated with a plurality of data processing chips is integrated on the package substrate. When there are multiple data processing chips, the multiple data processing chips can be integrated on the interconnect substrate first, and then the interconnect substrate can be integrated on the package substrate.
第四方面，本申请还提供了一种电子设备，包括印制电路板和上述第一方面或者第二方面任一实现方式中的芯片封装结构，或者第三方面任一实现方式中的芯片封装结构制备方法制得的芯片封装结构，印制电路板与芯片封装结构电连接。In a fourth aspect, the present application further provides an electronic device, including a printed circuit board and the chip package structure in any implementation manner of the first aspect or the second aspect, or the chip package in any implementation manner of the third aspect In the chip package structure prepared by the structure preparation method, the printed circuit board is electrically connected with the chip package structure.
本申请实施例提供的电子设备包括第一方面实施例或者第二方面实施例的芯片封装结构，或者第三方面实施例制得的芯片封装结构，因此本申请实施例提供的电子设备与上述技术方案的芯片封装结构能够解决相同的技术问题，并达到相同的预期效果。The electronic device provided by the embodiment of the present application includes the chip packaging structure of the first aspect embodiment or the second aspect embodiment, or the chip packaging structure obtained by the third aspect embodiment. Therefore, the electronic device provided by the embodiment of the present application is the same as the above technology. The chip packaging structure of the solution can solve the same technical problem and achieve the same expected effect.
附图说明Description of drawings
图1为现有技术中芯片封装结构的示意图；1 is a schematic diagram of a chip packaging structure in the prior art;
图2为现有技术中芯片封装结构的封装基板的结构示意图；2 is a schematic structural diagram of a package substrate of a chip package structure in the prior art;
图3为现有技术中芯片封装结构与PCB的连接关系示意图；3 is a schematic diagram of a connection relationship between a chip packaging structure and a PCB in the prior art;
图4为本申请实施例电子设备的部分结构示意图；4 is a partial structural schematic diagram of an electronic device according to an embodiment of the present application;
图5为本申请实施例芯片封装结构的示意图；5 is a schematic diagram of a chip packaging structure according to an embodiment of the present application;
图6为本申请实施例封装基底的示意图；6 is a schematic diagram of a package substrate according to an embodiment of the present application;
图7为本申请实施例芯片封装结构的示意图；7 is a schematic diagram of a chip packaging structure according to an embodiment of the present application;
图8为本申请实施例芯片封装结构的示意图；FIG. 8 is a schematic diagram of a chip packaging structure according to an embodiment of the present application;
图9为本申请实施例芯片封装结构的示意图；9 is a schematic diagram of a chip packaging structure according to an embodiment of the present application;
图10为本申请实施例转接板的结构示意图；10 is a schematic structural diagram of an adapter board according to an embodiment of the present application;
图11为本申请实施例多个数据处理芯片与互连基底的连接关系示意图；11 is a schematic diagram of the connection relationship between a plurality of data processing chips and an interconnection substrate according to an embodiment of the present application;
图12为本申请实施例芯片封装结构的一个方向的示意图；FIG. 12 is a schematic diagram of one direction of a chip packaging structure according to an embodiment of the present application;
图13为本申请实施例芯片封装结构的另一个方向的示意图；13 is a schematic diagram of another direction of the chip packaging structure according to the embodiment of the present application;
图14为本申请实施例芯片封装结构的示意图；14 is a schematic diagram of a chip packaging structure according to an embodiment of the present application;
图15为本申请实施例芯片封装结构的一个方向的示意图；FIG. 15 is a schematic diagram of one direction of a chip packaging structure according to an embodiment of the present application;
图16为本申请实施例芯片封装结构的另一个方向的示意图；16 is a schematic diagram of another direction of the chip packaging structure according to the embodiment of the present application;
图17为本申请实施例制得芯片封装结构的方法的流程框图；17 is a flowchart of a method for preparing a chip package structure according to an embodiment of the present application;
图18为本申请实施例制得芯片封装结构的方法的流程框图；18 is a flowchart of a method for preparing a chip package structure according to an embodiment of the present application;
图19为本申请实施例芯片封装结构的制备方法中各步骤完成后相对应的结构示意图；FIG. 19 is a schematic structural diagram corresponding to each step in the preparation method of the chip packaging structure according to the embodiment of the present application;
图20为本申请实施例制得芯片封装结构的方法的流程框图；20 is a flowchart of a method for preparing a chip package structure according to an embodiment of the present application;
图21为本申请实施例芯片封装结构的制备方法中各步骤完成后相对应的结构示意图。FIG. 21 is a schematic structural diagram corresponding to each step in a method for fabricating a chip packaging structure according to an embodiment of the present application after completion of each step.
附图标记：Reference number:
1-封装基板；111-衬底；112-重新布线结构；2-光引擎；21-光芯片；211-第一基底；212-光子集成电路；213-第一导电通道；22-电芯片；221-第二基底；222-电子集成电路；23-光纤连接结构；3-***级芯片；4-金属走线；5-印制电路板；6-凸点；01-电子设备；10-芯片封装结构；11-电连接结构；101-数据处理芯片；1011-第四基底；1012- 金属层；102-封装基底；1021-金属走线层；1022-导电通道；1023-介电层；103-互连基底；1031-第三基底；1032-第二导电通道；1033-重新布线层；7-塑封层；8-底胶；91-散热板；92-导电材料层；12-虚设结构；13-连接端子；14-供电芯片；15-支撑板；16-临时虚设结构；17-通道。1-package substrate; 111-substrate; 112-rewiring structure; 2-light engine; 21-optical chip; 211-first substrate; 212-photonic integrated circuit; 213-first conductive channel; 22-electrical chip; 221-second substrate; 222-electronic integrated circuit; 23-fiber connection structure; 3-system-on-chip; 4-metal wiring; 5-printed circuit board; 6-bump; 01-electronic equipment; 10-chip 11-electrical connection structure; 101-data processing chip; 1011-fourth substrate; 1012-metal layer; 102-package substrate; 1021-metal wiring layer; 1022-conductive channel; 1023-dielectric layer; 103 - interconnect substrate; 1031 - third substrate; 1032 - second conductive channel; 1033 - redistribution layer; 7 - plastic sealing layer; 8 - primer; 91 - heat sink; 92 - conductive material layer; 13-connection terminal; 14-power supply chip; 15-support plate; 16-temporary dummy structure; 17-channel.
具体实施方式detailed description
本申请实施例提供一种电子设备。该电子设备可以包括手机(mobile phone)、平板电脑(pad)、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)等设备。本申请实施例对上述电子设备的具体形式不做特殊限制。Embodiments of the present application provide an electronic device. The electronic device may include a mobile phone (mobile phone), a tablet computer (pad), a smart wearable product (eg, a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR), etc. equipment. The embodiments of the present application do not specifically limit the specific form of the above electronic device.
如图4所示，上述电子设备1可以包括芯片封装结构10以及印制电路板(printed circuit board，PCB)5。芯片封装结构10通过电连接结构11与PCB5电连接，从而使得芯片封装结构10能够与PCB5上的其他芯片实现信号传输。As shown in FIG. 4 , the above-mentioned electronic device 1 may include a chip package structure 10 and a printed circuit board (printed circuit board, PCB) 5 . The chip package structure 10 is electrically connected to the PCB 5 through the electrical connection structure 11 , so that the chip package structure 10 can realize signal transmission with other chips on the PCB 5 .
该电连接结构11可以是焊球阵列(ball grid array，BGA)。在可选择的实施方式中，如果芯片封装结构的尺寸比较大。为了保障该芯片封装结构10与PCB5电连接的可靠性，电连接结构11也可以采用带有插槽式固定结构的连接端子(socket)，该连接端子也可以称为连接器、插接器等。The electrical connection structure 11 may be a ball grid array (BGA). In an alternative embodiment, if the size of the chip package structure is relatively large. In order to ensure the reliability of the electrical connection between the chip package structure 10 and the PCB 5 , the electrical connection structure 11 may also use a connection terminal (socket) with a slot-type fixing structure, and the connection terminal may also be called a connector, a plug, etc. .
以下对上述芯片封装结构10的结构进行详细的说明。The structure of the above-mentioned chip package structure 10 will be described in detail below.
如图5所示，该芯片封装结构10包括：数据处理芯片101和光引擎(Optical Engine，OE)2，以及用于承载数据处理芯片101和OE2的封装基底102。其中，数据处理芯片101和OE2均被固定在封装基底102上，且分别与封装基底102上的金属走线1021电连接。封装基底102上的金属走线1021形成布线结构，在所述数据处理芯片101和所述OE2间建立信号通路，以及将所述数据处理芯片101和所述OE2连接至所述电连接结构11。As shown in FIG. 5 , the chip packaging structure 10 includes: a data processing chip 101 and an optical engine (Optical Engine, OE) 2, and a packaging substrate 102 for carrying the data processing chip 101 and the OE2. The data processing chip 101 and the OE2 are both fixed on the package substrate 102 and electrically connected to the metal traces 1021 on the package substrate 102 respectively. The metal traces 1021 on the package substrate 102 form a wiring structure, establish a signal path between the data processing chip 101 and the OE2 , and connect the data processing chip 101 and the OE2 to the electrical connection structure 11 .
OE2可以通过光纤收发光信号。从而，光信号就可以通过光纤传输至OE2，OE2将输入的光信号转换为电信号，电信号再传输至数据处理芯片101，通过数据处理芯片101对电信号进行算术运算或者逻辑运算。相反，数据处理芯片101也可以将电信号传输至OE2，OE2再将输入的电信号转换为光信号，并通过光纤将光信号传输出去。OE2 can receive and receive optical signals through optical fibers. Thus, the optical signal can be transmitted to the OE2 through the optical fiber, the OE2 converts the input optical signal into an electrical signal, and the electrical signal is then transmitted to the data processing chip 101, and the data processing chip 101 performs arithmetic or logical operations on the electrical signal. On the contrary, the data processing chip 101 can also transmit the electrical signal to the OE2, and the OE2 then converts the input electrical signal into an optical signal, and transmits the optical signal out through an optical fiber.
上述的数据处理芯片101是用于对OE2光电转后的电信号进行处理，或者将处理后的电信号传输至OE2。例如，该数据处理芯片101可以是***级芯片，也可以是中央处理单元(central processing unit，CPU)芯片等。The above-mentioned data processing chip 101 is used to process the electrical signal after the photoelectric conversion of the OE2, or to transmit the processed electrical signal to the OE2. For example, the data processing chip 101 may be a system-on-chip, or may be a central processing unit (central processing unit, CPU) chip or the like.
在可选择的实施例中，本申请涉及的封装基底可以是通过重布线工艺制得的重新布线层(redistribution layer，RDL)。图6为封装基底的结构示意图，包括多层金属走线1021、多层介电层1023，每相邻两层金属走线1021通过介电层1023间隔开，其中，介电层1023可以采用树脂材料等绝缘材料制得。为了使不同层上的金属走线1021实现电连接，可以在介电层1023内制作导电通道1022，以使不同层的金属走线1021通过该导电通道1022电连接。在现有技术中，用于封装芯片的封装基板采用的是有芯基板(Core基板)，结合图2，该Core基板除过包括重新布线结构112之外，还包括了衬底111，该衬底的材料通常为玻璃、非晶硅(amorphous silicon，a-Si)、或者碳化硅(SiC)等。由于衬底111的存在，会使整个Core基板具有较大的弹性模量，即 该Core基板具有较大的刚度，这样的话，当芯片通过表面贴装工艺(surface mount，SMT)或者倒装芯片贴片工艺集成在该Core基板上时，由于该芯片封装结构的尺寸较大，且数据处理芯片101和OE2相比Core基板刚性更大，这样的话，刚性较大的数据处理芯片101和OE2集成在刚性相对较小的Core基板上时，很容易使刚性较小的Core基板发生较大的翘曲现象，并在封装后的结构内产生较大的内应力，影响该芯片封装结构的使用性能。In an alternative embodiment, the package substrate involved in the present application may be a redistribution layer (RDL) produced by a redistribution process. 6 is a schematic structural diagram of a package substrate, including multi-layer metal traces 1021 and multi-layer dielectric layers 1023. Every two adjacent layers of metal traces 1021 are separated by a dielectric layer 1023, wherein the dielectric layer 1023 can be made of resin. materials and other insulating materials. In order to realize electrical connection between the metal traces 1021 on different layers, a conductive channel 1022 may be formed in the dielectric layer 1023 , so that the metal traces 1021 of different layers are electrically connected through the conductive channel 1022 . In the prior art, a package substrate used for packaging chips is a core substrate (Core substrate). Referring to FIG. 2 , the Core substrate includes a substrate 111 in addition to the rewiring structure 112 . The material of the bottom is usually glass, amorphous silicon (a-Si), or silicon carbide (SiC). Due to the existence of the substrate 111, the entire Core substrate will have a larger elastic modulus, that is, the Core substrate will have a larger stiffness. When the SMD process is integrated on the Core substrate, since the size of the chip package structure is larger, and the data processing chip 101 and OE2 are more rigid than the Core substrate, in this case, the more rigid data processing chip 101 and OE2 are integrated When the core substrate with relatively low rigidity is placed on the core substrate with relatively low rigidity, it is easy to cause large warpage of the core substrate with low rigidity, and a large internal stress is generated in the packaged structure, which affects the performance of the chip package structure. .
但是，本申请采用的封装基底不包括由玻璃、a-Si、或者SiC等材料制得的衬底，这样，整个封装基底的弹性模量会减小，即刚度减弱。所以，本申请是通过进一步缩小封装基底的刚性，以使刚性较大的数据处理芯片101和OE2集成在具有柔性的封装基底上时，抑制封装基底的翘曲程度，减小内应力，进而提高整个芯片封装结构的性能，延长使用寿命。However, the packaging substrate used in the present application does not include substrates made of materials such as glass, a-Si, or SiC, so that the elastic modulus of the entire packaging substrate is reduced, that is, the stiffness is weakened. Therefore, the present application is to further reduce the rigidity of the packaging substrate, so that when the data processing chips 101 and OE2 with greater rigidity are integrated on the packaging substrate with flexibility, the warpage of the packaging substrate can be suppressed, the internal stress can be reduced, and the The performance of the entire chip package structure extends the service life.
在可选择的实施例中，本申请的封装基底也可以为无芯基板(Coreless基板)，这里的Coreless基板相对Core基板，不包括上述所示的由玻璃、非晶硅(amorphous silicon，a-Si)、或者碳化硅(SiC)等材料制得的衬底，仅包括重新布线结构，Coreless基板的结构和如图6所示的结构是相同的。因此，Coreless基板也是一种重新布线层结构。In an optional embodiment, the packaging substrate of the present application can also be a coreless substrate (Coreless substrate). Here, the Coreless substrate, relative to the Core substrate, does not include the above-mentioned glass, amorphous silicon (amorphous silicon, a- The substrate made of Si), or silicon carbide (SiC) and other materials only includes the rewiring structure, and the structure of the Coreless substrate is the same as that shown in FIG. 6 . Therefore, the Coreless substrate is also a rewiring layer structure.
OE2可以包括构成有光子集成电路的光芯片21和与光芯片21连接的光纤连接结构23，光芯片21与封装基底102电连接。在可选择的实施方式中，可能需要对光芯片转换后的电信号进行进一步的处理(例如，变换、放大等)，这样一来，如图7所示，该OE2还可以包括构成有电子集成电路的电芯片22。The OE2 may include an optical chip 21 formed with a photonic integrated circuit and an optical fiber connection structure 23 connected to the optical chip 21 , and the optical chip 21 is electrically connected to the packaging substrate 102 . In an alternative embodiment, further processing (eg, transformation, amplification, etc.) may be required on the electrical signal converted by the optical chip, so that, as shown in FIG. 7 , the OE2 may also include an electronic integrated The electrical chip 22 of the circuit.
光芯片21和电芯片22可以采用三维(three dimension，3D)集成方式。也可以采用二维(two dimension，2D)集成方式。The optical chip 21 and the electrical chip 22 may adopt a three-dimension (3D) integration method. A two-dimension (2D) integration method can also be used.
在图8所示的结构中，光芯片21和电芯片22采用3D集成在封装基底102上。具体的，光芯片21和电芯片22呈堆叠布设，光芯片21包括第一基底211，第一基底211上形成有光子集成电路212。电芯片22包括第二基底221，第二基底221上形成有电子集成电路222。在光子集成电路212的表面形成有出光面Q，为了便于将光纤连接结构23与出光面Q耦合连接，可以将第一基底211靠近封装基底102设置，光子集成电路212位于第一基底211的远离封装基底102的一侧。为了缩短光子集成电路212和电子集成电路222的互连路径，电子集成电路222靠近光子集成电路212，第二基底221位于电子集成电路222的远离光子集成电路212的一侧，并且光子集成电路212和电子集成电路222采用倒装芯片贴片工艺电连接。In the structure shown in FIG. 8 , the optical chip 21 and the electrical chip 22 are integrated on the package substrate 102 using 3D. Specifically, the optical chip 21 and the electrical chip 22 are arranged in a stacked manner, and the optical chip 21 includes a first substrate 211 on which a photonic integrated circuit 212 is formed. The electrical chip 22 includes a second substrate 221 on which an electronic integrated circuit 222 is formed. A light-emitting surface Q is formed on the surface of the photonic integrated circuit 212 . In order to facilitate the coupling and connection of the optical fiber connection structure 23 and the light-emitting surface Q, the first substrate 211 can be arranged close to the packaging substrate 102 , and the photonic integrated circuit 212 is located far from the first substrate 211 . One side of the package substrate 102 . In order to shorten the interconnection path of the photonic integrated circuit 212 and the electronic integrated circuit 222, the electronic integrated circuit 222 is close to the photonic integrated circuit 212, the second substrate 221 is located on the side of the electronic integrated circuit 222 away from the photonic integrated circuit 212, and the photonic integrated circuit 212 It is electrically connected with the electronic integrated circuit 222 using a flip-chip technology.
为了实现光子集成电路212与封装基底102电连接，在第一基底211内形成有贯通第一基底211的第一导电通道213，第一导电通道213的一端与光子集成电路212电连接，另一端电连接凸点(solder bump)6，凸点6再与封装基底102的金属走线电连接，也可以通过其他电结构电连接导电通道和封装基底。这样的话，就实现了光子集成电路212、电子集成电路222以及封装基底102之间的电路的互连。示例的，在第一基底211为采用具有硅元素的半导体材料构成的硅基底时，形成于该硅基底上的第一导电通道213可以称为硅通孔(through silicon via，STV)。In order to realize the electrical connection between the photonic integrated circuit 212 and the package substrate 102, a first conductive channel 213 is formed in the first substrate 211 through the first substrate 211. One end of the first conductive channel 213 is electrically connected to the photonic integrated circuit 212, and the other end is The solder bumps 6 are electrically connected, and the bumps 6 are then electrically connected to the metal traces of the package substrate 102. The conductive channels and the package substrate can also be electrically connected through other electrical structures. In this way, interconnection of circuits between the photonic integrated circuit 212, the electronic integrated circuit 222, and the packaging substrate 102 is achieved. For example, when the first substrate 211 is a silicon substrate made of a semiconductor material with silicon element, the first conductive channel 213 formed on the silicon substrate may be called a through silicon via (STV).
当光芯片21和电芯片22采用如图8所示的3D集成方式设置在封装基底102上 时，光芯片21和电芯片22之间的互连方式为垂直互连，互连路径短，从而可以提高光芯片21和电芯片22之间信号传输的效率。When the optical chip 21 and the electrical chip 22 are arranged on the package substrate 102 in the 3D integrated manner as shown in FIG. 8 , the interconnection between the optical chip 21 and the electrical chip 22 is vertical interconnection, and the interconnection path is short, so that the The efficiency of signal transmission between the optical chip 21 and the electrical chip 22 can be improved.
为了便于使光纤连接结构23通过光纤与外置的光源连接，如图8所示，光芯片21的出光面Q所处的一侧靠近封装基底102的外缘。In order to facilitate the connection of the optical fiber connection structure 23 to an external light source through an optical fiber, as shown in FIG.
当光芯片21和电芯片22采用2D集成在封装基底102上时，光芯片21集成在封装基底102上，电芯片22也集成在封装基底102上，且光芯片21的光子集成电路212靠近封装基底102，电芯片22的电子集成电路222也靠近封装基底102，光子集成电路212和电子集成电路222通过封装基底上的金属走线电连接。When the optical chip 21 and the electrical chip 22 are 2D integrated on the package substrate 102, the optical chip 21 is integrated on the package substrate 102, the electrical chip 22 is also integrated on the package substrate 102, and the photonic integrated circuit 212 of the optical chip 21 is close to the package The substrate 102, the electronic integrated circuits 222 of the electrical chip 22 are also close to the package substrate 102, and the photonic integrated circuits 212 and the electronic integrated circuits 222 are electrically connected by metal traces on the package substrate.
由于本申请采用的封装基底是刚度较小的Coreless基板或者RDL，为了增加封装后的整个芯片封装结构的强度，如图5所示，可以在封装基底102的表面上设置塑封层(molding)7，并使数据处理芯片101或者OE2被包裹在塑封层7内，进而可以增加该芯片封装结构的强度，塑封层7也可以对OE2和数据处理芯片101进行保护。Since the packaging substrate used in this application is a Coreless substrate or RDL with low rigidity, in order to increase the strength of the entire chip packaging structure after packaging, as shown in FIG. , and the data processing chip 101 or OE2 is encapsulated in the plastic packaging layer 7 , thereby increasing the strength of the chip packaging structure, and the plastic packaging layer 7 can also protect the OE2 and the data processing chip 101 .
本申请实施例中的数据处理芯片101可以为一个，也可以为多个。当一个数据处理芯片101满足不了数据处理能力时，就可以采用多个数据处理芯片101。图9所示的芯片封装结构中就是采用了多个数据处理芯片101。There may be one data processing chip 101 in this embodiment of the present application, and may also be multiple. When one data processing chip 101 cannot satisfy the data processing capability, multiple data processing chips 101 may be used. In the chip package structure shown in FIG. 9 , a plurality of data processing chips 101 are used.
如图9所示，当具有多个数据处理芯片101时，可以将多个数据处理芯片101集成在互连基底103上，以形成组合芯片(Combo die)，互连基底103再集成在封装基底102上，并与封装基底102电连接，从而使得多个数据处理芯片101与封装基底102电连接，以及数据处理芯片101之间实现电连接。As shown in FIG. 9, when there are multiple data processing chips 101, the multiple data processing chips 101 can be integrated on the interconnect substrate 103 to form a Combo die, and the interconnect substrate 103 can be integrated on the packaging substrate 102 , and is electrically connected to the package substrate 102 , so that the plurality of data processing chips 101 are electrically connected to the package substrate 102 and the data processing chips 101 are electrically connected.
互连基底103可以采用RDL，RDL的结构如图6所示，即包括多层金属走线1021、多层介电层1023，每相邻两层金属走线1021通过介电层1023间隔开，在介电层1023内制作第一导电通道1022，不同层的金属走线1021通过该第一导电通道1022电连接。The interconnection substrate 103 can use RDL. The structure of the RDL is shown in FIG. 6 , that is, it includes multi-layer metal wirings 1021 and multi-layer dielectric layers 1023 . Every two adjacent layers of metal wirings 1021 are separated by the dielectric layer 1023 . A first conductive channel 1022 is formed in the dielectric layer 1023 , and the metal traces 1021 of different layers are electrically connected through the first conductive channel 1022 .
在可选择的实施方式中，互连基底103也可以为转接板(Interposer)，图10所示的为一种转接板的结构图，包括第三基底1031，集成在第三基底1031上的重新布线层1033，以及贯通第三基底1031的第二导电通道1032，第二导电通道1032与重新布线层1033中的金属走线电连接。示例的，在第三基底1031为采用具有硅元素的半导体材料构成的硅基底时，该转接板成为Si Interposer。In an alternative embodiment, the interconnect substrate 103 may also be an interposer. FIG. 10 shows a structural diagram of an interposer, including a third substrate 1031 integrated on the third substrate 1031 The redistribution layer 1033 , and the second conductive channel 1032 penetrating through the third substrate 1031 , and the second conductive channel 1032 is electrically connected to the metal traces in the redistribution layer 1033 . For example, when the third substrate 1031 is a silicon substrate made of a semiconductor material with silicon element, the interposer becomes a Si Interposer.
当采用转接板作为互连基底时，重新布线层1033靠近组合芯片，并可以通过凸点与每一个数据处理芯片电连接，第三基底1031靠近封装基底，并可以通过第二导电通道1032和凸点与封装基底中的金属走线电连接。When the interposer board is used as the interconnection substrate, the redistribution layer 1033 is close to the combination chip and can be electrically connected with each data processing chip through bumps, and the third substrate 1031 is close to the package substrate and can pass through the second conductive channel 1032 and The bumps are electrically connected to metal traces in the package substrate.
为了提升互连基底与封装基底之间连接的可靠性，如图9，可以采用点胶工艺，在互连基底103与封装基底102之间填充底胶(Underfill)8。当然，也可以在OE2与封装基底102之间填充底胶。In order to improve the reliability of the connection between the interconnection substrate and the package substrate, as shown in FIG. 9 , a glue dispensing process may be used to fill underfill 8 between the interconnection substrate 103 and the package substrate 102 . Of course, primer can also be filled between the OE2 and the packaging substrate 102 .
本申请实施例中的任一个数据处理芯片包括基底和金属层。比如，如图11所示，两个数据处理芯片101均包括第四基底1011和金属层1012，金属层1012构成有电路结构。金属层1012靠近互连基底103，并通过凸点6与互连基底103电连接，第四基底1011位于金属层1012的远离互连基底103的一侧。Any data processing chip in the embodiments of the present application includes a substrate and a metal layer. For example, as shown in FIG. 11 , both data processing chips 101 include a fourth substrate 1011 and a metal layer 1012 , and the metal layer 1012 forms a circuit structure. The metal layer 1012 is close to the interconnection substrate 103 and is electrically connected to the interconnection substrate 103 through the bumps 6 , and the fourth substrate 1011 is located on the side of the metal layer 1012 away from the interconnection substrate 103 .
在可选择的实施方式中，OE2也可以包括多个，用于和数据处理芯片相配合，对不同种的电信号进行处理。In an optional implementation manner, the OE2 may also include multiple ones, which are used for processing different kinds of electrical signals in cooperation with the data processing chip.
数据处理芯片101和OE2在封装基底102上的布设位置具有多种情况。示例的，如图9所示，数据处理芯片101和OE2位于封装基底102的同一表面上。再示例的，如图14所示，数据处理芯片101和OE2位于封装基底102的相对的两表面上。The arrangement positions of the data processing chips 101 and OE2 on the package substrate 102 have various situations. Illustratively, as shown in FIG. 9 , the data processing chip 101 and the OE2 are located on the same surface of the package substrate 102 . As another example, as shown in FIG. 14 , the data processing chip 101 and the OE2 are located on two opposite surfaces of the package substrate 102 .
当OE2和数据处理芯片101的数量较少，所占据的面积较小时，就可以将数据处理芯片101和OE2集成在封装基底102的同一表面上。当OE2和数据处理芯片101的数量较多，所占据的面积较大时，将数据处理芯片101和OE2集成在封装基底102的相对的两表面上，以充分利用封装基底的相对两表面上的面积。When the number of the OE2 and the data processing chip 101 is small and the area occupied is small, the data processing chip 101 and the OE2 can be integrated on the same surface of the package substrate 102 . When the number of OE2 and the data processing chip 101 is large and the area occupied is large, the data processing chip 101 and OE2 are integrated on two opposite surfaces of the packaging substrate 102 to make full use of the two opposite surfaces of the packaging substrate. area.
封装基底102的用于搭载数据处理芯片101和OE2，以及其他电子结构的两个相对的面可以称为第一表面和第二表面，图12为一种实施方式中第一表面A1上的布设结构图，图13为第二表面A2上的布设结构图。可以看出，OE2和数据处理芯片101均集成在第一表面A1上。在可选择的实施方式中，数据处理芯片101靠近第一表面A1的中心区域布设，多个OE2沿第一表面A1的周边间隔布设。The two opposite surfaces of the package substrate 102 for mounting the data processing chips 101 and OE2 and other electronic structures may be referred to as the first surface and the second surface. FIG. 12 shows the layout on the first surface A1 in one embodiment. Structure diagram, FIG. 13 is a layout structure diagram on the second surface A2. It can be seen that both the OE2 and the data processing chip 101 are integrated on the first surface A1. In an alternative embodiment, the data processing chip 101 is arranged close to the central area of the first surface A1, and a plurality of OEs are arranged along the periphery of the first surface A1 at intervals.
多个OE2沿第一表面A1的周边间隔布设的好处是：便于光纤连接结构通过光纤与外置的光源连接，进而降低加工难度，且可以缩短OE至光源的传输路径。The advantages of multiple OE2 being spaced along the periphery of the first surface A1 are: it is convenient for the optical fiber connecting structure to connect with the external light source through the optical fiber, thereby reducing the processing difficulty and shortening the transmission path from the OE to the light source.
另外，在封装基底102的第二表面A2上，也可以布设连接端子13，通过该连接端子13与PCB上的芯片或者其他半导体结构电连接。也可以在第二表面A2上集成供电芯片。当然如果安装空间允许的话，也可以在第二表面A2上集成其他芯片。In addition, on the second surface A2 of the package substrate 102 , connection terminals 13 may also be arranged, and the connection terminals 13 are electrically connected to chips on the PCB or other semiconductor structures. A power supply chip can also be integrated on the second surface A2. Of course, if the installation space allows, other chips can also be integrated on the second surface A2.
当OE2和数据处理芯片101均集成在第一表面A1上时，如图9所示，可以在第一表面A1上设置塑封层7，以使塑封层7包裹在OE2和数据处理芯片101的周边，进而对OE2和数据处理芯片101进行保护和加固。When both the OE2 and the data processing chip 101 are integrated on the first surface A1, as shown in FIG. 9 , a plastic sealing layer 7 may be provided on the first surface A1, so that the plastic sealing layer 7 wraps around the OE2 and the data processing chip 101 , and further protect and reinforce the OE2 and the data processing chip 101 .
另外，为了能够将光纤连接结构23与光芯片21的出光面连接，结合图9，在塑封层7上形成有贯通至出光面Q的通道19，这样的话，光纤连接结构23穿过通道19并与出光面Q连接。In addition, in order to connect the optical fiber connecting structure 23 to the light-emitting surface of the optical chip 21, referring to FIG. 9, a channel 19 is formed on the plastic sealing layer 7 to penetrate to the light-emitting surface Q. In this case, the optical fiber connecting structure 23 passes through the channel 19 and Connect to the light-emitting surface Q.
图15为另一种实施方式中第一表面A1上的布设结构图，图16为第二表面A2上的布设结构图。可以看出，数据处理芯片101集成在第一表面A1上，数据处理芯片101靠近第一表面A1的中心区域布设。为了防止仅在第一表面A1上集成数据处理芯片101而造成翘曲现象，在第一表面A1上还布设有多个虚设结构12，多个虚设结构12沿第一表面A1的周边布设。OE2集成在第二表面A2上，且多个OE2沿第二表面A2的周边间隔布设。另外，也可以在第二表面A2上布设连接端子13，通过该连接端子13与PCB上的芯片或者其他半导体结构电连接，也可以在第二表面A2上集成供电芯片14。FIG. 15 is a layout structure diagram on the first surface A1 in another embodiment, and FIG. 16 is a layout structure diagram on the second surface A2. It can be seen that the data processing chip 101 is integrated on the first surface A1, and the data processing chip 101 is arranged close to the central area of the first surface A1. In order to prevent warpage caused by integrating the data processing chip 101 only on the first surface A1, a plurality of dummy structures 12 are also arranged on the first surface A1, and the plurality of dummy structures 12 are arranged along the periphery of the first surface A1. The OE2 is integrated on the second surface A2, and a plurality of OE2 are arranged at intervals along the periphery of the second surface A2. In addition, connecting terminals 13 can also be arranged on the second surface A2, and the connecting terminals 13 can be electrically connected to chips on the PCB or other semiconductor structures, and a power supply chip 14 can also be integrated on the second surface A2.
上述虚设结构12可以是晶圆切割后得到的裸芯片(dummy die)，也可以是其他材料构成的其他结构，例如，玻璃块。使用裸芯片的话，在工艺流程上较为简单，工艺流程也较为成熟，且制造成本也低。The above-mentioned dummy structure 12 may be a dummy die obtained after wafer dicing, or may be other structures made of other materials, such as glass blocks. If a bare chip is used, the process flow is relatively simple, the process flow is relatively mature, and the manufacturing cost is also low.
如图14所示，当数据处理芯片101和虚设结构12均集成在第一表面A1上时，可以在第一表面A1上设置塑封层7，以使塑封层7包裹在数据处理芯片101和虚设结构12的周边，进而对数据处理芯片101和虚设结构12进行保护和加固。因为通过在第一表面A1上已经布设有塑封层7，整个芯片封装结构的强度已经能够满足使用要求，这样一来，OE2所处的第二表面A2上可以不布设塑封层，当然，为了进一步增加强 度，也可以布设塑封层。As shown in FIG. 14 , when both the data processing chip 101 and the dummy structure 12 are integrated on the first surface A1, a plastic sealing layer 7 may be provided on the first surface A1, so that the plastic sealing layer 7 is wrapped around the data processing chip 101 and the dummy structure. The periphery of the structure 12 is further protected and strengthened for the data processing chip 101 and the dummy structure 12 . Because the plastic encapsulation layer 7 has been arranged on the first surface A1, the strength of the entire chip packaging structure can already meet the requirements for use. In this way, the second surface A2 where the OE2 is located may not have a plastic encapsulation layer. Of course, in order to further To increase the strength, the plastic layer can also be arranged.
若在OE2所处的第二表面A2上设置塑封层时，和上述的图9所述的结构一样，在塑封层7上形成有贯通至出光面Q的通道19，光纤连接结构23穿过通道19并与出光面Q连接。If a plastic encapsulation layer is provided on the second surface A2 where the OE2 is located, the same as the structure described above in FIG. 9 , a channel 19 is formed on the plastic encapsulation layer 7 penetrating to the light emitting surface Q, and the optical fiber connecting structure 23 passes through the channel 19 and connect with the light-emitting surface Q.
数据处理芯片101在工作时，会散发出较多的热量，则该芯片封装结构还可以包括散热板，参照图9，在数据处理芯片101的远离封装基底102的表面涂覆导电材料层92，上述散热板91覆盖导热材料层92。在导热材料层92的导热作用下，可以将数据处理芯片101产生的热量导入至散热板91，以通过散热板91进行散热。同时，为了也对和数据处理芯片101位于同一侧的OE2进行散热，在OE2的远离封装基底102的表面上也涂覆导热材料层92，散热板91延伸至OE2表面的导热材料层92上。When the data processing chip 101 is working, it will emit a lot of heat, and the chip packaging structure may also include a heat sink. Referring to FIG. 9 , a conductive material layer 92 is coated on the surface of the data processing chip 101 away from the packaging substrate 102 , The heat dissipation plate 91 covers the thermally conductive material layer 92 . Under the thermal conductivity of the thermally conductive material layer 92 , the heat generated by the data processing chip 101 can be introduced to the heat dissipation plate 91 to dissipate heat through the heat dissipation plate 91 . At the same time, in order to dissipate heat to the OE2 located on the same side as the data processing chip 101, a thermally conductive material layer 92 is also coated on the surface of the OE2 away from the package substrate 102, and the heat dissipation plate 91 extends to the thermally conductive material layer 92 on the surface of the OE2.
散热板91不仅起到散热作用，也可以提高整个芯片封装结构的强度。The heat dissipation plate 91 not only plays a role of heat dissipation, but also can improve the strength of the entire chip package structure.
本申请实施例还提供一种芯片封装结构的制备方法，如图17所示，该制备方法包括：The embodiment of the present application also provides a method for preparing a chip packaging structure, as shown in FIG. 17 , the preparation method includes:
步骤S1：在支撑板上形成封装基底，封装基底为重新布线层。Step S1: forming an encapsulation substrate on the support plate, and the encapsulation substrate is a rewiring layer.
形成的重新布线层的结构如图6所示，即包括：多层金属走线1021、多层介电层1023和导电通道1022，每相邻两层金属走线1021通过介电层1023间隔开，导电通道1022贯通介电层1023，并电连接不同层的金属走线1021。The structure of the formed redistribution layer is shown in FIG. 6 , that is, it includes: multi-layer metal traces 1021 , multi-layer dielectric layers 1023 and conductive channels 1022 , and every two adjacent layers of metal traces 1021 are separated by the dielectric layer 1023 , the conductive channel 1022 passes through the dielectric layer 1023 and is electrically connected to the metal traces 1021 of different layers.
在可选择的实施方式中，封装基底也可以是Coreless基板，Coreless基板和重新布线层的结构是相同的，在制造工艺上不同。In an alternative embodiment, the package substrate may also be a Coreless substrate, and the structures of the Coreless substrate and the redistribution layer are the same, but differ in manufacturing processes.
由于封装基底采用的是刚性较弱的Coreless基板或者重新布线层，如果直接在无芯基板或者重新布线层上集成光引擎和数据处理芯片，加工工艺难度较大。本申请是将无芯基板或者重新布线层设置在支撑板上，利用该支撑板的支撑作用，可以降低光芯片和数据处理芯片的集成难度。Since the package substrate uses a less rigid Coreless substrate or rewiring layer, if the optical engine and data processing chip are directly integrated on the coreless substrate or rewiring layer, the processing technology is more difficult. In the present application, the coreless substrate or the rewiring layer is arranged on the support plate, and the integration difficulty of the optical chip and the data processing chip can be reduced by using the support function of the support plate.
步骤S2：将至少一个光引擎，以及至少一个数据处理芯片集成在封装基底上，且分别与封装基底电连接，在封装基底的表面上形成塑封层，以使数据处理芯片和/或光引擎被包裹在塑封层内，且使光引擎的光芯片的出光面裸露，并移除支撑板，得到芯片封装结构。Step S2: Integrate at least one light engine and at least one data processing chip on the packaging substrate, and are respectively electrically connected to the packaging substrate, and form a plastic packaging layer on the surface of the packaging substrate, so that the data processing chip and/or the light engine are It is wrapped in a plastic packaging layer, and the light-emitting surface of the optical chip of the light engine is exposed, and the support plate is removed to obtain a chip packaging structure.
在上述的步骤S1中，当形成的封装基底为重新布线层时，具体的形成过程可以包括：In the above-mentioned step S1, when the formed packaging substrate is a rewiring layer, the specific forming process may include:
以上述的支撑板为基板，在基板上形成一层金属层，在该金属层上刻蚀出金属走线，以形成第一层金属走线。Using the above-mentioned support plate as a substrate, a metal layer is formed on the substrate, and metal wires are etched on the metal layer to form a first layer of metal wires.
在形成有第一层金属走线的基板上形成第一层介电层。A first dielectric layer is formed on the substrate on which the first layer of metal traces are formed.
在该第一层介电层形成导电通道。Conductive vias are formed in the first dielectric layer.
在第一介电层上形成一层金属层，在该金属层上刻蚀出金属走线，以形成第二层金属走线，并使导电通道电连接第一层金属走线和第二层金属走线。A metal layer is formed on the first dielectric layer, and metal traces are etched on the metal layer to form a second layer of metal traces, and conductive channels are electrically connected to the first layer of metal traces and the second layer Metal traces.
重复上述步骤，进而制得重新布线层。The above steps are repeated to obtain a redistribution layer.
另外，在上述的步骤S1中，当形成的封装基底为无芯基板时，可以将已经制得的无芯基板直接键合在支撑板上。In addition, in the above-mentioned step S1, when the package substrate formed is a coreless substrate, the coreless substrate that has been produced can be directly bonded to the support plate.
其中，无芯基板可以采用半加成法(SAP)制得，具体的包括：Among them, the coreless substrate can be prepared by the semi-additive method (SAP), which specifically includes:
层压两层金属层，对其中一个金属层刻蚀，形成金属柱。Laminate two metal layers and etch one of the metal layers to form metal pillars.
在形成有金属柱的金属层上层压介电层。A dielectric layer is laminated on the metal layer on which the metal pillars are formed.
在介电层上层压一层金属层。A metal layer is laminated on the dielectric layer.
对位于介电层两侧面上的金属层刻蚀，形成金属走线。The metal layers on both sides of the dielectric layer are etched to form metal traces.
重新上述步骤，从而制得无芯基板。The above steps are repeated to obtain a coreless substrate.
当数据处理芯片具有多个时，在将数据处理芯片集成在封装基底上之前，还包括：When there are a plurality of data processing chips, before integrating the data processing chips on the package substrate, it also includes:
将多个数据处理芯片集成在互连基底上，并与互连基底电连接。互连基底可以是重新布线层或者转接板。A plurality of data processing chips are integrated on the interconnection substrate and electrically connected with the interconnection substrate. The interconnect substrate may be a redistribution layer or an interposer.
该重新布线层可以采用上述方法制得，只是在与封装基底电连接前，需要将基板刻蚀掉。The redistribution layer can be prepared by the above method, but the substrate needs to be etched away before being electrically connected with the package substrate.
本申请实施例的光引擎至少包括光芯片和与光芯片的出光面连接的光纤连接结构，这样，在封装基底上集成光引擎，以及在形成塑封层时，可以包括下述步骤：The light engine of the embodiment of the present application includes at least an optical chip and an optical fiber connection structure connected to the light-emitting surface of the optical chip. In this way, the light engine is integrated on the packaging substrate, and the following steps may be included when forming the plastic packaging layer:
将至少一个光芯片集成在封装基底上，且使光芯片的出光面背离封装基底。The at least one optical chip is integrated on the packaging substrate, and the light-emitting surface of the optical chip faces away from the packaging substrate.
可以这样理解，将光芯片的基底一侧朝向封装基底，光芯片的光子集成电路一侧背离封装基底，这样的话，就可以使光芯片的出光面背离封装基底。It can be understood in this way that the base side of the optical chip faces the packaging substrate, and the photonic integrated circuit side of the optical chip faces away from the packaging substrate, so that the light emitting surface of the optical chip can be turned away from the packaging substrate.
若光引擎还包括电芯片，且光芯片和电芯片呈三维堆叠时，可以将集成为一体的光芯片和电芯片集成在封装基底上。另外，电芯片在与光芯片堆叠时，不能遮挡住光芯片的出光面。If the light engine further includes an electrical chip, and the optical chip and the electrical chip are three-dimensionally stacked, the integrated optical chip and the electrical chip can be integrated on the packaging substrate. In addition, when the electrical chip is stacked with the optical chip, the light emitting surface of the optical chip cannot be blocked.
采用临时虚设结构覆盖住出光面。以免在后续形成塑封层时将出光面Q盖住，无法再连接光纤连接结构。Use a temporary dummy structure to cover the light-emitting surface. In order to avoid covering the light-emitting surface Q when the plastic encapsulation layer is subsequently formed, the optical fiber connection structure cannot be connected.
在封装基底上形成塑封层，以使塑封层包裹光芯片和临时虚设结构(dummy block)的周边，并使临时虚设结构的表面外露在塑封层的外部。A plastic packaging layer is formed on the packaging substrate, so that the plastic packaging layer wraps the optical chip and the periphery of the temporary dummy block, and the surface of the temporary dummy structure is exposed outside the plastic packaging layer.
临时虚设结构可以是裸芯片，或者玻璃，或者金属材料制得的结构。The temporary dummy structure may be a bare chip, or a structure made of glass or metal materials.
移除临时虚设结构，以在塑封层上形成贯通至出光面的通道。The temporary dummy structure is removed to form a channel on the plastic encapsulation layer through to the light emitting surface.
将光纤连接结构穿过通道并与出光面连接。这样，就完成了光引擎和塑封层的设置。Pass the optical fiber connecting structure through the channel and connect with the light-emitting surface. In this way, the settings of the light engine and the plastic encapsulation layer are completed.
在将光纤连接结构与出光面连接时，将光纤连接结构的光接口通过透明胶与出光面接合，再采用加固胶沿光接口的外缘将光纤连接结构固定在出光面上。When connecting the optical fiber connecting structure to the light-emitting surface, the optical interface of the optical fiber connecting structure is joined to the light-emitting surface through transparent glue, and then the optical fiber connecting structure is fixed on the light-emitting surface along the outer edge of the optical interface with reinforcing glue.
本申请给出了芯片封装结构的制备方法的其中两种可选择的实施方式，下述进行详细说明。The present application provides two alternative embodiments of the method for manufacturing the chip package structure, which will be described in detail below.
OE2和数据处理芯片101集成在封装基底的同一表面上时，图18是该实施方式的流程框图，图19是图18对应的各步骤的结构图。When the OE2 and the data processing chip 101 are integrated on the same surface of the package substrate, FIG. 18 is a flowchart of this embodiment, and FIG. 19 is a structural diagram of each step corresponding to FIG. 18 .
制备方法包括下述步骤：The preparation method includes the following steps:
如图18的步骤S101、图19中的19b，在支撑板15上形成封装基底102。In step S101 in FIG. 18 and 19 b in FIG. 19 , the package substrate 102 is formed on the support plate 15 .
如图18的步骤S102、图19中的19b，将至少一个光芯片21，以及至少一个数据处理芯片101集成在封装基底102表面上，且使光芯片21的出光面Q背离封装基底102。In step S102 in FIG. 18 and 19b in FIG. 19 , at least one optical chip 21 and at least one data processing chip 101 are integrated on the surface of the package substrate 102 , and the light emitting surface Q of the optical chip 21 faces away from the package substrate 102 .
图19所示的制备方法制得的芯片封装结构中，包括多个数据处理芯片，所以，如图19的19a，先将多个数据处理芯片101集成在互连基底103上，形成组合芯片，再 将组合芯片集成在封装基底102上。组合芯片可以设置在靠近封装基底102的中心区域。The chip package structure prepared by the preparation method shown in FIG. 19 includes a plurality of data processing chips. Therefore, as shown in 19a of FIG. 19 , the plurality of data processing chips 101 are first integrated on the interconnection substrate 103 to form a combined chip, The combined chip is then integrated on the package substrate 102 . The combined chip may be disposed near the center area of the package substrate 102 .
当光芯片21具有多个时，多个光芯片沿封装基底的周边间隔布设，且需要使光芯片的出光面靠近封装基底的外缘。When there are multiple optical chips 21 , the multiple optical chips are arranged at intervals along the periphery of the packaging substrate, and it is necessary to make the light-emitting surface of the optical chips close to the outer edge of the packaging substrate.
在将多个数据处理芯片101集成在互连基底103上后，如图19的19a，也可以在具有数据处理芯片101的互连基底103上形成塑封层7，并且在完成塑封层后，需要对塑封层进行研磨抛光，露出数据处理芯片101的表面。After a plurality of data processing chips 101 are integrated on the interconnection substrate 103, as shown in 19a of FIG. 19, a plastic encapsulation layer 7 can also be formed on the interconnection substrate 103 with the data processing chips 101, and after the plastic encapsulation layer is completed, it is necessary to The plastic sealing layer is ground and polished to expose the surface of the data processing chip 101 .
图19的OE不仅包括了光芯片21，也包括与光芯片21呈三维堆叠的电芯片22。The OE of FIG. 19 includes not only the optical chip 21 , but also the electrical chip 22 three-dimensionally stacked with the optical chip 21 .
在将光芯片21集成在封装基底102上之前，就将电芯片22和光芯片21堆叠成为一个整体，再将该整体设置在封装基底102上。Before integrating the optical chip 21 on the packaging substrate 102 , the electrical chip 22 and the optical chip 21 are stacked as a whole, and then the whole is disposed on the packaging substrate 102 .
在该步骤中，可以先将数据处理芯片集成在封装基底的中心区域后，再将多个光芯片集成在封装基底的边缘。In this step, the data processing chip can be integrated in the central area of the package substrate first, and then the plurality of optical chips can be integrated on the edge of the package substrate.
如图18的步骤S103、图19中的19c，采用临时虚设结构16覆盖住出光面Q。As shown in step S103 in FIG. 18 and 19c in FIG. 19 , a temporary dummy structure 16 is used to cover the light-emitting surface Q.
如图18的步骤S104、图19中的19d，在封装基底上形成塑封层7，以使塑封层7包裹光芯片和数据处理芯片的周边。As shown in step S104 in FIG. 18 and 19d in FIG. 19 , a plastic packaging layer 7 is formed on the packaging substrate, so that the plastic packaging layer 7 wraps the periphery of the optical chip and the data processing chip.
当然，当包括与光芯片21呈三维堆叠的电芯片22时，塑封层7也是需要包裹住电芯片22的周边。Of course, when the electrical chip 22 is three-dimensionally stacked with the optical chip 21 , the plastic encapsulation layer 7 also needs to wrap around the periphery of the electrical chip 22 .
通常，采用沉积工艺形成塑封层，这样的话，数据处理芯片101和电芯片22，以及临时虚设结构16的表面也会覆盖有塑封层，所以，需要对数据处理芯片101和电芯片22的表面，以及临时虚设结构16的表面进行化学机械抛光处理，去除多余的塑封层，以使数据处理芯片101和电芯片22，以及临时虚设结构16的表面露出，且使表面平坦化。Usually, a plastic encapsulation layer is formed by a deposition process. In this case, the surfaces of the data processing chip 101 and the electrical chip 22 and the temporary dummy structure 16 are also covered with a plastic encapsulation layer. And the surface of the temporary dummy structure 16 is subjected to chemical mechanical polishing to remove the redundant plastic packaging layer, so as to expose the surface of the data processing chip 101 , the electrical chip 22 , and the temporary dummy structure 16 and make the surface flat.
如图18的步骤S105、图19中的19e，移除临时虚设结构16，以在塑封层上形成贯通至出光面的通道17。As shown in step S105 in FIG. 18 and step 19e in FIG. 19 , the temporary dummy structure 16 is removed to form a channel 17 on the plastic sealing layer penetrating to the light-emitting surface.
如图18的步骤S106、图19中的19e，移除支撑板15。可以采用机械研磨或者激光切割工艺移除支撑板15。As shown in step S106 in FIG. 18 and 19e in FIG. 19 , the support plate 15 is removed. The support plate 15 may be removed using a mechanical grinding or laser cutting process.
如图18的步骤S107、图19中的19f，设置散热板92。Step S107 in FIG. 18 and 19f in FIG. 19 , the heat dissipation plate 92 is provided.
具体的，先在塑封层的表面上涂覆导电材料层92，再将散热板91盖在导电材料层92上。由于上述已经对数据处理芯片101和电芯片22的表面上的塑封层已经被去掉，这样一来，导电材料层92直接与两种芯片的表面贴合，会提高散热效果。Specifically, the conductive material layer 92 is first coated on the surface of the plastic sealing layer, and then the heat dissipation plate 91 is covered on the conductive material layer 92 . Since the plastic packaging layers on the surfaces of the data processing chip 101 and the electrical chip 22 have been removed, the conductive material layer 92 is directly attached to the surfaces of the two chips, which improves the heat dissipation effect.
如图18的步骤S108、图19中的19g，将光纤连接结构23穿过通道并与出光面连接。最终制得数据处理芯片和OE处于封装基底同一表面上的芯片封装结构。As shown in step S108 in FIG. 18 and 19g in FIG. 19 , the optical fiber connection structure 23 is passed through the channel and connected to the light-emitting surface. Finally, a chip package structure in which the data processing chip and the OE are located on the same surface of the package substrate is obtained.
上述是在移除临时虚设结构16后，移除支撑板15。在可选择的实施方式中，也可以是移除临时虚设结构16，再将光纤连接结构23连接在出光面上之后，移除支撑板15。The above is to remove the support plate 15 after removing the temporary dummy structure 16 . In an alternative embodiment, the temporary dummy structure 16 can also be removed, and after connecting the optical fiber connecting structure 23 to the light-emitting surface, the support plate 15 can be removed.
在设置散热板91之后，也可以在封装基底上设置连接端子，或者也可以设置供电芯片。且连接端子和供电芯片位于封装基底的与数据处理芯片相对的另一侧。After the heat dissipation plate 91 is provided, connection terminals may also be provided on the package substrate, or a power supply chip may also be provided. And the connection terminal and the power supply chip are located on the other side of the package substrate opposite to the data processing chip.
OE2和数据处理芯片101集成在封装基底的相对的两表面时，图20是该实施方式的流程框图，图21是图20对应的各步骤的结构图。When the OE2 and the data processing chip 101 are integrated on two opposite surfaces of the package substrate, FIG. 20 is a flowchart of this embodiment, and FIG. 21 is a structural diagram of each step corresponding to FIG. 20 .
制备方法包括下述步骤：The preparation method includes the following steps:
如图20的步骤S201、图21中的21b，在支撑板15上形成封装基底102。As shown in step S201 in FIG. 20 and 21 b in FIG. 21 , the package substrate 102 is formed on the support plate 15 .
如图20的步骤S202、图21中的21b，将至少一个数据处理芯片101，以及至少一个虚设结构12集成在封装基底102的表面上。In step S202 in FIG. 20 and 21 b in FIG. 21 , at least one data processing chip 101 and at least one dummy structure 12 are integrated on the surface of the package substrate 102 .
该实施方式和上述的图19所示的方法一样，可以包括多个数据处理芯片，所以，如图21的21a，先将多个数据处理芯片101集成在互连基底103上，形成组合芯片，再将组合芯片集成在封装基底102上。This embodiment is the same as the method shown in FIG. 19 described above, and may include multiple data processing chips. Therefore, as shown in 21a of FIG. 21 , multiple data processing chips 101 are first integrated on the interconnect substrate 103 to form a combined chip, The combined chip is then integrated on the package substrate 102 .
当虚设结构12的数量具有多个时，将多个虚设结构12沿封装基底的周边布设。When there are multiple dummy structures 12 , the multiple dummy structures 12 are arranged along the periphery of the package substrate.
如图20的步骤S203、图21中的21c，在封装基底上形成塑封层7，以使塑封层7包裹虚设结构12和数据处理芯片101的周边。As shown in step S203 in FIG. 20 and 21 c in FIG. 21 , a plastic packaging layer 7 is formed on the packaging substrate, so that the plastic packaging layer 7 wraps around the dummy structure 12 and the periphery of the data processing chip 101 .
在实施时，数据处理芯片101和虚设结构12的表面也会覆盖有塑封层，所以，需要对数据处理芯片101和虚设结构12的表面进行化学机械抛光处理，去除多余的塑封层，以使数据处理芯片101和虚设结构12的表面露出。During implementation, the surfaces of the data processing chip 101 and the dummy structure 12 will also be covered with a plastic encapsulation layer. Therefore, it is necessary to perform chemical mechanical polishing on the surfaces of the data processing chip 101 and the dummy structure 12 to remove the redundant plastic encapsulation layer so that the data The surfaces of the handle chip 101 and the dummy structure 12 are exposed.
如图20的步骤S204、图21中的21d，移除支撑板15。As shown in step S204 in FIG. 20 and 21 d in FIG. 21 , the support plate 15 is removed.
如图20的步骤S205、图21中的21f，将至少一个光引擎2集成在封装基底102的另一表面上，以使光引擎和数据处理芯片位于封装基底的相对的两表面。Step S205 in FIG. 20, 21f in FIG. 21, integrate at least one light engine 2 on the other surface of the package substrate 102, so that the light engine and the data processing chip are located on two opposite surfaces of the package substrate.
当光引擎2具有多个时，可以将多个光引擎2沿封装基底的周边间隔布设。When there are a plurality of light engines 2, the plurality of light engines 2 may be arranged at intervals along the periphery of the packaging substrate.
由于在封装基底的一个表面上，即具有数据处理芯片和虚设结构的表面上形成有塑封层，该塑封层对最终的芯片封装结构起到加固、增加强度的作用，那么，可以在封装基底的另一表面，即具有光引擎的表面上不形成塑封层。若为了进一步增加强度，也可以形成塑封层，具体的在另一表面上设置光引擎的方法和前面涉及的方法相同，在此不再赘述。Since a plastic encapsulation layer is formed on one surface of the package substrate, that is, the surface with the data processing chip and the dummy structure, the plastic encapsulation layer can reinforce and increase the strength of the final chip encapsulation structure. No plastic encapsulation layer is formed on the other surface, that is, the surface with the light engine. In order to further increase the strength, a plastic encapsulation layer can also be formed. The specific method of disposing the light engine on the other surface is the same as the method mentioned above, and will not be repeated here.
若不在具有光引擎的表面上形成塑封层时，可以将集成在一起的光芯片、电芯片和光纤连接结构的OE与封装基底连接，也可以先将集成在一起的光芯片和电芯片与封装基底连接，再将光纤连接结构连接在光芯片的出光面上。If the plastic encapsulation layer is not formed on the surface with the optical engine, the OE of the integrated optical chip, the electrical chip and the optical fiber connection structure can be connected to the packaging substrate, or the integrated optical chip and the electrical chip can be connected to the package first. The substrate is connected, and then the optical fiber connection structure is connected to the light-emitting surface of the optical chip.
如果需要在具有光引擎的表面上集成其他结构时，例如，包括连接端子或者供电芯片时，可以在步骤S205之前，图21中的21e，可以在封装基底的中心区域设置连接端子13和供电芯片14，然后在执行步骤S205。If other structures need to be integrated on the surface with the light engine, for example, including connection terminals or power supply chips, the connection terminals 13 and power supply chips can be arranged in the central area of the package substrate before step S205, 21e in FIG. 21 14, and then execute step S205.
如图20的步骤S206、图21中的21e，设置散热板92。As shown in step S206 in FIG. 20 and 21e in FIG. 21 , the heat dissipation plate 92 is provided.
在可选择的实施方式中，可以在完成光引擎2、连接端子13和供电芯片14的设置后，再设置散热板92。In an alternative embodiment, the heat dissipation plate 92 may be installed after the installation of the light engine 2 , the connection terminals 13 and the power supply chip 14 is completed.
上述的两种制备方法中，由于封装基底采用的是Coreless基板或者RDL，这样在将各芯片集成在封装基底上时，会因为封装基底的较大的柔性减弱翘曲的程度。In the above two preparation methods, since the package substrate adopts Coreless substrate or RDL, when each chip is integrated on the package substrate, the degree of warpage will be weakened due to the greater flexibility of the package substrate.
尽管封装基底刚性减弱，本申请再通过形成塑封层，可以使最终制得的芯片封装结构的强度、刚性满足使用要求。Although the rigidity of the package substrate is weakened, by forming a plastic encapsulation layer in the present application, the strength and rigidity of the finally prepared chip package structure can meet the requirements for use.
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。In the description of this specification, the particular features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换， 都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。The above descriptions are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed in the present application can easily think of changes or substitutions. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims (18)

  1. 一种芯片封装结构，其特征在于，包括：A chip packaging structure, characterized in that it includes:
    封装基底，为重新布线层；The package substrate is the rewiring layer;
    至少一个光引擎，所述光引擎包括光纤连接结构，以及构成有光子集成电路的光芯片；at least one optical engine, the optical engine includes an optical fiber connection structure, and an optical chip formed with a photonic integrated circuit;
    至少一个数据处理芯片；at least one data processing chip;
    所述光芯片和所述数据处理芯片均集成在所述封装基底的同一表面上，并分别与所述封装基底电连接，且所述光芯片的出光面位于背离所述封装基底的一侧；Both the optical chip and the data processing chip are integrated on the same surface of the packaging substrate, and are respectively electrically connected to the packaging substrate, and the light emitting surface of the optical chip is located on the side away from the packaging substrate;
    塑封层，位于所述封装基底的集成有所述光芯片和所述数据处理芯片的表面上，并包裹所述光芯片和所述数据处理芯片，所述塑封层具有贯通至所述出光面的通道，所述光纤连接结构穿过所述通道与所述出光面连接。A plastic sealing layer is located on the surface of the packaging substrate on which the optical chip and the data processing chip are integrated, and wraps the optical chip and the data processing chip, and the plastic sealing layer has a surface extending through to the light emitting surface. A channel, the optical fiber connecting structure is connected to the light emitting surface through the channel.
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述数据处理芯片靠近所述封装基底的中心区域设置，所述光引擎具有多个，多个所述光引擎沿所述封装基底的周边布设。The chip packaging structure according to claim 1, wherein the data processing chip is disposed near a central area of the packaging substrate, the light engine has a plurality of light engines, and the plurality of light engines are located along the center of the packaging substrate. Layout around.
  3. 根据权利要求1或2所述的芯片封装结构，其特征在于，所述芯片封装结构还包括互连基底；The chip package structure according to claim 1 or 2, wherein the chip package structure further comprises an interconnection substrate;
    所述数据处理芯片具有多个，多个所述数据处理芯片均集成在所述互连基底上，并与所述互连基底电连接，所述互连基底设置在所述封装基底上并与所述封装基底电连接。There are a plurality of the data processing chips, the plurality of the data processing chips are all integrated on the interconnection substrate, and are electrically connected with the interconnection substrate, and the interconnection substrate is arranged on the packaging substrate and is connected with the interconnection substrate. The package substrate is electrically connected.
  4. 根据权利要求3所述的芯片封装结构，其特征在于，所述互连基底为重新布线层或者转接板。The chip package structure according to claim 3, wherein the interconnection substrate is a rewiring layer or an interposer.
  5. 根据权利要求1-4中任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括连接端子：The chip package structure according to any one of claims 1-4, wherein the chip package structure further comprises a connection terminal:
    所述连接端子设置在所述封装基底的与所述数据处理芯片相对的表面上。The connection terminal is provided on a surface of the package substrate opposite to the data processing chip.
  6. 一种芯片封装结构，其特征在于，包括：A chip packaging structure, characterized in that it includes:
    封装基底，为重新布线层；The package substrate is the rewiring layer;
    至少一个光引擎；at least one light engine;
    至少一个数据处理芯片；at least one data processing chip;
    所述光引擎和所述数据处理芯片集成在所述封装基底的相对的两表面上，并分别与所述封装基底电连接；The light engine and the data processing chip are integrated on two opposite surfaces of the packaging substrate, and are respectively electrically connected to the packaging substrate;
    塑封层，位于所述封装基底的具有所述数据处理芯片的表面上，并包裹所述数据处理芯片。A plastic packaging layer is located on the surface of the packaging substrate with the data processing chip, and wraps the data processing chip.
  7. 根据权利要求6所述的芯片封装结构，其特征在于，所述芯片封装结构还包括多个虚设结构；The chip packaging structure according to claim 6, wherein the chip packaging structure further comprises a plurality of dummy structures;
    所述多个虚设结构和所述数据处理芯片位于所述封装基底的同一表面上，且所述虚设结构被包裹在所述塑封层内，所述数据处理芯片靠近所述封装基底的中心区域设置，所述多个虚设结构沿所述封装基底的周边布设。The plurality of dummy structures and the data processing chips are located on the same surface of the packaging substrate, and the dummy structures are encapsulated in the plastic packaging layer, and the data processing chips are arranged close to the central area of the packaging substrate , the plurality of dummy structures are arranged along the periphery of the package substrate.
  8. 根据权利要求7所述的芯片封装结构，其特征在于，所述虚设结构为裸芯片。The chip packaging structure according to claim 7, wherein the dummy structure is a bare chip.
  9. 根据权利要求6-8中任一项所述的芯片封装结构，其特征在于，所述芯片封装 结构还包括互连基底；The chip package structure according to any one of claims 6-8, wherein the chip package structure further comprises an interconnection substrate;
    所述数据处理芯片具有多个，多个所述数据处理芯片均集成在所述互连基底上，并与所述互连基底电连接，所述互连基底设置在所述封装基底上并与所述封装基底电连接。There are a plurality of the data processing chips, the plurality of the data processing chips are all integrated on the interconnection substrate, and are electrically connected with the interconnection substrate, and the interconnection substrate is arranged on the packaging substrate and is connected with the interconnection substrate. The package substrate is electrically connected.
  10. 根据权利要求9所述的芯片封装结构，其特征在于，所述互连基底为重新布线层或者转接板。The chip package structure according to claim 9, wherein the interconnection substrate is a rewiring layer or an interposer.
  11. 根据权利要求6-10中任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括连接端子：The chip package structure according to any one of claims 6-10, wherein the chip package structure further comprises connection terminals:
    所述连接端子和所述光引擎位于所述封装基底的同一表面上。The connection terminals and the light engine are located on the same surface of the package substrate.
  12. 一种芯片封装结构的制备方法，其特征在于，包括：A method for preparing a chip packaging structure, comprising:
    在支撑板上形成封装基底，所述封装基底为重新布线层；forming an encapsulation substrate on the support plate, the encapsulation substrate is a rewiring layer;
    将至少一个光引擎，以及至少一个数据处理芯片集成在所述封装基底上，且分别与所述封装基底电连接，在所述封装基底的表面上形成塑封层，以使所述数据处理芯片和/或所述光引擎被包裹在所述塑封层内，且使所述光引擎的光芯片的出光面裸露，并移除所述支撑板，得到芯片封装结构。At least one light engine and at least one data processing chip are integrated on the packaging substrate, and are respectively electrically connected to the packaging substrate, and a plastic sealing layer is formed on the surface of the packaging substrate, so that the data processing chip and the packaging substrate are electrically connected. /or the light engine is encapsulated in the plastic encapsulation layer, and the light emitting surface of the light chip of the light engine is exposed, and the support plate is removed to obtain a chip package structure.
  13. 根据权利要求12所述的芯片封装结构的制备方法，其特征在于，所述光引擎至少包括光纤连接结构，以及集成有光子集成电路的所述光芯片；The method for preparing a chip packaging structure according to claim 12, wherein the optical engine comprises at least an optical fiber connection structure, and the optical chip integrated with a photonic integrated circuit;
    将至少一个光引擎集成在所述封装基底上，以及在具有所述光引擎的所述封装基底上形成塑封层包括：Integrating at least one light engine on the package substrate, and forming a plastic encapsulation layer on the package substrate with the light engine includes:
    将至少一个所述光芯片集成在所述封装基底上，且使所述光芯片的出光面背离所述封装基底；Integrating at least one of the optical chips on the packaging substrate, and making the light-emitting surface of the optical chip away from the packaging substrate;
    采用临时虚设结构覆盖住所述出光面；Cover the light-emitting surface with a temporary dummy structure;
    在所述封装基底上形成塑封层，以使所述塑封层包裹所述光芯片和所述临时虚设结构的周边，并使所述临时虚设结构的表面外露在所述塑封层的外部；forming a plastic packaging layer on the packaging substrate, so that the plastic packaging layer wraps the optical chip and the periphery of the temporary dummy structure, and the surface of the temporary dummy structure is exposed outside the plastic packaging layer;
    移除所述临时虚设结构，以在所述塑封层上形成贯通至所述出光面的通道；removing the temporary dummy structure to form a channel through the light-emitting surface on the plastic sealing layer;
    将所述光纤连接结构穿过所述通道并与所述出光面连接。The optical fiber connecting structure is passed through the channel and connected with the light-emitting surface.
  14. 根据权利要求12或13所述的芯片封装结构的制备方法，其特征在于，The method for preparing a chip package structure according to claim 12 or 13, wherein,
    将至少一个光引擎，以及至少一个数据处理芯片集成在所述封装基底上，并分别与所述封装基底电连接，在所述封装基底上形成塑封层，以使所述数据处理芯片和/或所述光引擎被包裹在所述塑封层内，并移除所述支撑板，包括：Integrating at least one light engine and at least one data processing chip on the packaging substrate and electrically connecting with the packaging substrate respectively, and forming a plastic packaging layer on the packaging substrate, so that the data processing chip and/or The light engine is wrapped in the plastic layer, and the support plate is removed, including:
    将至少一个所述光引擎，以及至少一个所述数据处理芯片集成在所述封装基底的同一表面上；Integrating at least one of the light engines and at least one of the data processing chips on the same surface of the package substrate;
    在所述封装基底的具有所述光引擎和所述数据处理芯片的表面上形成所述塑封层，以使所述塑封层包裹所述光引擎和所述数据处理芯片，且使所述光引擎的光芯片的出光面裸露在所述塑封层的外部；The plastic sealing layer is formed on the surface of the packaging substrate having the light engine and the data processing chip, so that the plastic sealing layer wraps the light engine and the data processing chip, and makes the light engine The light-emitting surface of the optical chip is exposed outside the plastic sealing layer;
    移除所述支撑板，得到芯片封装结构。The support plate is removed to obtain a chip package structure.
  15. 根据权利要求12或13所述的芯片封装结构的制备方法，其特征在于，The method for preparing a chip package structure according to claim 12 or 13, wherein,
    将至少一个光引擎，以及至少一个数据处理芯片集成在所述封装基底上，并分别与所述封装基底电连接，在所述封装基底上形成塑封层，以使所述数据处理芯片和/ 或所述光引擎被包裹在所述塑封层内，并移除所述支撑板，包括：Integrate at least one light engine and at least one data processing chip on the packaging substrate, and are respectively electrically connected to the packaging substrate, and form a plastic packaging layer on the packaging substrate, so that the data processing chip and/or The light engine is wrapped in the plastic layer, and the support plate is removed, including:
    将至少一个所述数据处理芯片集成在所述封装基底的表面上；integrating at least one of the data processing chips on the surface of the package substrate;
    在所述封装基底的具有所述数据处理芯片的表面上形成所述塑封层；移除所述支撑板；forming the plastic packaging layer on the surface of the packaging substrate with the data processing chip; removing the support plate;
    将至少一个光引擎集成在所述封装基底的另一表面上，以使所述光引擎和所述数据处理芯片位于所述封装基底的相对的两表面上，得到芯片封装结构。At least one light engine is integrated on the other surface of the package substrate, so that the light engine and the data processing chip are located on two opposite surfaces of the package substrate to obtain a chip package structure.
  16. 根据权利要求15所述的芯片封装结构的制备方法，其特征在于，将至少一个所述数据处理芯片集成在所述封装基底的表面上时，包括：The method for manufacturing a chip package structure according to claim 15, wherein when integrating at least one of the data processing chips on the surface of the package substrate, the method comprises:
    将至少一个所述数据处理芯片和多个虚设结构均集成在所述封装基底的表面上，且所述数据处理芯片靠近所述封装基底的中心区域设置，所述多个虚设结构沿所述封装基底的周边布设。At least one of the data processing chips and a plurality of dummy structures are integrated on the surface of the package substrate, and the data processing chip is arranged close to the central area of the package substrate, and the plurality of dummy structures are along the package. The perimeter of the base is arranged.
  17. 根据权利要求12-16中任一项所述的芯片封装结构的制备方法，其特征在于，在所述数据处理芯片包括多个时；The method for preparing a chip package structure according to any one of claims 12-16, wherein when the data processing chip includes a plurality of chips;
    在将所述数据处理芯片集成在所述封装基底上之前，所述制备方法还包括：Before integrating the data processing chip on the packaging substrate, the preparation method further includes:
    将多个所述数据处理芯片集成在互连基底上，并与所述互连基底电连接。A plurality of the data processing chips are integrated on the interconnection substrate and electrically connected with the interconnection substrate.
  18. 一种电子设备，其特征在于，包括：An electronic device, comprising:
    印制电路板；printed circuit boards;
    如权利要求1～11中任一项所述的芯片封装结构，或者如权利要求12～17中任一项所述的芯片封装结构的制备方法制得的芯片封装结构；The chip package structure according to any one of claims 1 to 11, or the chip package structure obtained by the preparation method of the chip package structure according to any one of claims 12 to 17;
    其中，所述印制电路板与所述芯片封装结构电连接。Wherein, the printed circuit board is electrically connected with the chip packaging structure.
PCT/CN2020/112294 2020-08-28 2020-08-28 Chip packaging structure, electronic device, and method for preparing chip packaging structure WO2022041159A1 (en)

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