CN219611734U

CN219611734U - Amplifying circuit, chip and electronic equipment

Info

Publication number: CN219611734U
Application number: CN202320402487.0U
Authority: CN
Inventors: 王涛涛; 张启帆
Original assignee: Shanghai Awinic Technology Co Ltd
Current assignee: Shanghai Awinic Technology Co Ltd
Priority date: 2023-03-03
Filing date: 2023-03-03
Publication date: 2023-08-29
Anticipated expiration: 2033-03-03

Abstract

The utility model discloses an amplifying circuit, a chip and electronic equipment, wherein a first input end of a first chopper switch is connected with a first input signal, a second input end of the first chopper switch is connected with a second input signal, a first output end of the first chopper switch is connected with a first input end of a second chopper switch through a first resistor, a second output end of the second chopper switch is connected with a first input end of an operational amplifier, a second output end of the second chopper switch is connected with a second input end of the operational amplifier, a first output end of the operational amplifier is connected with a first input end of a PWM modulator, a second output end of the operational amplifier is connected with a second input end of the PWM modulator, a third resistor is connected between the first input end of the operational amplifier and the first output end of the PWM modulator, and a fourth resistor is connected between the second input end of the operational amplifier and the second output end of the PWM modulator. The utility model can improve the power supply rejection ratio performance on the premise of not increasing the chip area.

Description

Amplifying circuit, chip and electronic equipment

Technical Field

The present utility model relates to the field of circuit technologies, and in particular, to an amplifying circuit, a chip, and an electronic device.

Background

In an amplifying circuit adopted by an audio power amplifier, when an output power tube is directly powered by a charge pump or a power supply, analysis is performed for an example of the amplifying circuit shown in fig. 1, wherein in fig. 1, RF1 and RF2 can be collectively referred to as RFx, and are input resistors of the amplifying circuit, and RIN1 and RIN2 can be collectively referred to as RINx, and are feedback resistors of the amplifying circuit; because the alternating current signal on the power supply can be directly fed back to the input end of the large circuit through RFx and RINx, under ideal conditions, RF1 = RF2, RIN1 = RIN2, and the fed back differential mode signal is zero at the moment, so that the output of the amplifying circuit is not influenced; however, in practice, because of the mismatch between RF1 and RF2 and the mismatch between RIN1 and RIN2, the signal at the input end of the feedback playback large circuit has a differential mode signal, so that the output of the amplifying circuit has an ac component on the power supply, and the power supply of the power amplifier is poorly inhibited. The power supply suppression expression of the amplifying circuit shown in fig. 1 is:

wherein PSR represents a power supply rejection ratio, RF represents a resistance value of a feedback resistor, RIN represents a resistance value of an input resistor, and mis (RF/RIN) represents a mismatch of RF/RIN; sigma (RF/RIN) represents the mismatch coefficient per unit area of RF/RIN; σ (RF) denotes a mismatch coefficient of RF, and σ (RIN) denotes a mismatch coefficient of RIN.

The inventor researches and discovers that in the amplifying circuit, the mismatch of the resistor and the corresponding chip area are in inverse relation, and the power supply inhibition performance is difficult to improve under the condition that the chip area is not increased.

Disclosure of Invention

In view of the above, the present utility model provides an amplifying circuit, a chip and an electronic device, so as to solve the problem that in the conventional power amplifier, it is difficult to improve the power supply suppression performance without increasing the chip area.

The utility model provides an amplifying circuit which comprises a first chopping switch, a second chopping switch, an operational amplifier, a PWM modulator, a first resistor, a second resistor, a third resistor and a fourth resistor, wherein the first chopping switch is connected with the first resistor;

the first input end of the first chopper switch is used for being connected with a first input signal, the second input end is used for being connected with a second input signal, the first output end is connected with the first input end of the second chopper switch through the first resistor, the second output end is connected with the second input end of the second chopper switch through the second resistor, the first output end of the second chopper switch is connected with the first input end of the operational amplifier, the second output end is connected with the second input end of the operational amplifier, the first output end of the operational amplifier is connected with the first input end of the PWM modulator, the second output end is connected with the second input end of the PWM modulator, the third resistor is connected between the first input end of the operational amplifier and the first output end of the PWM modulator, and the fourth resistor is connected between the second input end of the operational amplifier and the second output end of the PWM modulator.

Optionally, the first chopper switch and the second chopper switch each include 4 transmission gates; each transmission gate is connected between one input end and one output end of the corresponding chopping switch, so that each input end of the chopping switch is connected with each output end through one transmission gate.

Optionally, the transmission gate includes a first MOS transistor and a second MOS transistor; the drain electrode of the first MOS tube is respectively connected with one input end of the chopping switch and the source electrode of the second MOS tube, the grid electrode is used for being connected with a first driving signal, the source electrode is respectively connected with one output end of the chopping switch and the drain electrode of the second MOS tube, and the grid electrode of the second MOS tube is used for being connected with a second driving signal.

Optionally, the chopper switch further comprises a driving switch corresponding to each transmission gate; the driving switch is used for accessing a clock signal and outputting the first driving signal and the second driving signal.

Optionally, the driving switch includes a first inverter, a second inverter, a third inverter, and a fourth inverter; the input end of the first inverter is used for being connected with a clock signal, the output end of the first inverter is connected with the input end of the second inverter and the input end of the third inverter respectively, the output end of the second inverter is used for outputting the first driving signal, the output end of the third inverter is connected with the input end of the fourth inverter, and the output end of the fourth inverter is used for outputting the second driving signal.

Optionally, the amplifying circuit further comprises a clock generating module; the clock generation module is used for accessing an external clock to generate a first clock and a second clock corresponding to the first chopping switch, and a second clock and a third clock corresponding to the second chopping switch.

Optionally, the clock generating module includes a fifth inverter, a first and gate, a second and gate, a sixth inverter, a seventh inverter, and two delay units; the input end of the fifth inverter is connected with the first input end of the first AND gate and is used for being connected with the external clock, the output end of the fifth inverter is connected with the first input end of the second AND gate, the second input end of the second AND gate is connected with the first clock end of the first chopping switch, the output end of the fifth inverter is connected with the second clock end of the first chopping switch through the seventh inverter, the output end of the fifth inverter is connected with the first clock end of the first chopping switch through the sixth inverter, the output end of the seventh inverter is also connected with the first clock end of the second chopping switch through a delay unit, and the output end of the sixth inverter is also connected with the second clock end of the second chopping switch through a delay unit.

Optionally, the delay unit includes an eighth inverter, a fifth resistor, a third MOS transistor, a fourth MOS transistor, a ninth inverter and a tenth inverter; the input end of the eighth inverter is connected with one clock end of the first chopper switch, the output end of the eighth inverter is connected with the first end of the fifth resistor, the second end of the fifth resistor is respectively connected with the grid electrode of the third MOS tube, the grid electrode of the fourth MOS tube and the input end of the ninth inverter, the source electrode of the third MOS tube is respectively connected with an external power supply and the drain electrode of the third MOS tube, the source electrode of the fourth MOS tube is respectively connected with the ground end and the drain electrode of the fourth MOS tube, and the output end of the ninth inverter is connected with one clock end of the second chopper switch through the tenth inverter.

Optionally, the resistance values of the fifth resistor, the first resistor and the second resistor are equal.

Optionally, the amplifying circuit further includes a first capacitor and a second capacitor; the first capacitor is connected between the first input of the operational amplifier and the first output of the PWM modulator, and the second capacitor is connected between the second input of the operational amplifier and the second output of the PWM modulator.

The utility model also provides a chip comprising any one of the amplifying circuits.

The utility model also provides electronic equipment comprising any one of the amplifying circuits or any one of the chips.

According to the amplifying circuit, the chip and the electronic equipment, the first chopping switch and the second chopping switch are respectively arranged at the two ends of the input resistor, so that the impedance of the whole input resistor is the average value of all the input resistors involved, mismatch among all the input resistors can be eliminated, the power supply rejection ratio performance can be improved on the premise of not increasing the area of the chip, the amplifying circuit has a relatively small area, no special requirements are imposed on the process by the amplifying circuit, and the corresponding manufacturing cost can be reduced.

Further, in each chopper switch, each input end is connected with each output end through a transmission gate respectively, so that the linearity of the corresponding chopper switch can be improved, and the influence on THD is prevented.

Further, the branch circuit for processing the first input signal and the branch circuit for processing the second input signal are symmetrical to each other, so that offset voltage in the amplifying circuit can be effectively reduced.

It can be seen that the above-described amplifying circuit can optimize its performance from various aspects.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an amplifying circuit in the course of the inventors' study;

FIG. 2 is a schematic diagram of an amplifying circuit according to an embodiment of the present utility model;

FIG. 3 is a schematic diagram of an amplifying circuit according to another embodiment of the present utility model;

FIGS. 4a, 4b, 4c and 4d are schematic diagrams of chopper switch related structures according to an embodiment of the present utility model;

FIGS. 5a and 5b are schematic diagrams illustrating clock generation modules according to an embodiment of the present utility model;

FIG. 6 is a timing diagram of clock signals according to an embodiment of the utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to fall within the scope of the utility model. The various embodiments described below and their technical features can be combined with each other without conflict.

The first aspect of the present utility model provides an amplifying circuit which can be used for performing power amplification processing on an audio signal. Referring to fig. 2, the amplifying circuit includes a first chopping switch 100, a second chopping switch 200, an operational amplifier 310, a PWM modulator 320, a first resistor RIN1, a second resistor RIN2, a third resistor RF1, and a fourth resistor RF2. The amplifying circuit is a fully differential amplifying circuit, is connected with two paths of input signals (Vin shown in fig. 2), and comprises a first input signal and a second input signal, and outputs two paths of output signals (Vout shown in fig. 2) after the two paths of input signals are amplified.

The first input end of the first chopper switch 100 is used for accessing a first input signal, the second input end is used for accessing a second input signal, the first output end is connected with the first input end of the second chopper switch 200 through a first resistor RIN1, and the second output end is connected with the second input end of the second chopper switch 200 through a second resistor RIN 2. The first output end of the second chopper switch 200 is connected to the first input end of the operational amplifier 310, and the second output end is connected to the second input end of the operational amplifier 310. The first output terminal of the operational amplifier 310 is connected to the first input terminal of the PWM modulator 320, and the second output terminal is connected to the second input terminal of the PWM modulator 320. The third resistor RF1 is connected between the first input of the operational amplifier 310 and the first output of the PWM modulator 320, and the fourth resistor RF2 is connected between the second input of the operational amplifier 310 and the second output of the PWM modulator 320.

The first resistor RIN1 and the second resistor RIN2 are input resistors of the power amplifier circuit, and may be collectively referred to as RINx. The third resistor RF1 and the fourth resistor RF2 are feedback resistors of the power amplifier circuit, and may be collectively referred to as RFx. Specifically, the first resistor RIN1 may be used to access the first input signal, and the second resistor RIN2 may be used to access the second input signal. The third resistor RF1 may be used for feedback regulation of the first output signal and the fourth resistor RF2 may be used for feedback regulation of the second output signal.

The first chopping switch 100 and the second chopping switch 200 described above are used to eliminate mismatch between the input resistances (the first resistance RIN1 and the second resistance RIN 2). Specifically, the first chopper switch 100 and the second chopper switch 200 are respectively disposed at two ends of the input resistor, so that in the amplifying circuit shown in fig. 2, the impedance seen from Vin end and N1 end is the average value of the first resistor RIN1 and the second resistor RIN2, and mismatch between RIN1 and RIN2 is eliminated. In the actual circuit, since the operational amplifier 310 has a certain gain, RFx is generally greater than RINx, and since the mismatch of the resistor and the area are in inverse relation, the mismatch of RINx in the actual circuit occupies a relatively large area, and the mismatch of RINx is eliminated by the first chopping switch 100 and the second chopping switch 200, so that the power supply rejection ratio performance can be effectively improved, the amplifying circuit has a relatively small area, and the amplifying circuit has no special requirement on the process, and can reduce the corresponding manufacturing cost.

The first operational amplifier 310 includes a fully differential operational amplifier for performing operational amplification processing on the signal output from the second chopper switch 200. In the first operational amplifier 310 shown in fig. 2, the first input terminal is a positive input terminal, the second input terminal is a negative input terminal, the first output terminal is a negative input terminal, and the second output terminal is a positive output terminal.

The PWM modulator 320 is configured to perform PWM modulation corresponding to the signal output by the first operational amplifier 310, so as to output a PWM signal; the PWM signal includes a first output signal output from a first output terminal of the PWM modulator 320 and a second output signal output from a second output terminal of the PWM modulator 320.

Optionally, referring to fig. 3, the amplifying circuit further includes a first capacitor C1 and a second capacitor C2; the first capacitor C1 is connected between the first input terminal of the operational amplifier 310 and the first output terminal of the PWM modulator 320, and the second capacitor C2 is connected between the second input terminal of the operational amplifier 310 and the second output terminal of the PWM modulator 320.

In the amplifying circuit, the first chopping switch 100 and the second chopping switch 200 are respectively arranged at two ends of the input resistor, so that the impedance of the whole input resistor is the average value of the related input resistors, mismatch among the input resistors can be eliminated, the power supply rejection ratio performance can be improved on the premise of not increasing the area of a chip, the amplifying circuit has a relatively small area, the amplifying circuit has no special requirement on the process, and the corresponding manufacturing cost can be reduced.

In one embodiment, the first chopping switch 100 and the second chopping switch 200 each include 4 transmission gates; each of the transmission gates is connected between one input terminal and one output terminal of a corresponding chopper switch (e.g., the first chopper switch 100 or the second chopper switch 200), respectively, such that each input terminal of the chopper switch is connected to each output terminal through one of the transmission gates, respectively. In this embodiment, each input end of the chopper switch is connected to each output end through a transmission gate, so that linearity of the corresponding chopper switch can be improved, and an influence on THD (total harmonic distortion) is prevented.

Specifically, referring to fig. 4a, the 4 transmission gates include a first transmission gate K1, a second transmission gate K2, a third transmission gate K3, and a fourth transmission gate K4; the first input end A1 of the chopper switch is connected with the first output end B1 through the second transmission gate K2, the first input end A1 is connected with the second output end B2 through the fourth transmission gate K4, the second input end A2 is connected with the first output end B1 through the first transmission gate K1, and the second input end A2 is connected with the second output end B2 through the third transmission gate K3.

In one example, referring to fig. 4b, the transmission gate includes a first MOS transistor NM1 and a second MOS transistor PM1. The drain electrode of the first MOS tube NM1 is respectively connected with one input end of the chopping switch and the source electrode of the second MOS tube PM1, the grid electrode is used for being connected with a first driving signal, and the source electrode is respectively connected with one output end of the chopping switch and the drain electrode of the second MOS tube PM1. The gate of the second MOS transistor PM1 is used for accessing a second driving signal. Optionally, the first MOS tube NM1 is an NMOS tube, and the second MOS tube PM1 is a PMOS tube.

Specifically, in the first transmission gate K1, the drain electrode of the first MOS transistor NM1 is connected to the second input terminal A2 of the chopper switch, and the source electrode is connected to the first output terminal B1 of the chopper switch; in the second transmission gate K2, the drain electrode of the first MOS tube NM1 is connected with the second input end A2 of the chopping switch, and the source electrode is connected with the first output end B1 of the chopping switch; in the third transmission gate K3, the drain electrode of the first MOS transistor NM1 is connected to the second input terminal A2 of the chopper switch, and the source electrode is connected to the second input terminal B2 of the chopper switch; in the fourth transmission gate K4, the drain electrode of the first MOS transistor NM1 is connected to the first input terminal A1 of the chopper switch, and the source electrode is connected to the second input terminal B2 of the chopper switch.

In one example, referring to fig. 4c, the chopper switch further includes a driving switch 110 corresponding to each of the transmission gates; the driving switch 110 is used for accessing a clock signal and outputting the first driving signal and the second driving signal to improve the driving capability of the chopper switch.

In one example, as shown in fig. 4c, the driving switch includes a first inverter 111, a second inverter 112, a third inverter 113, and a fourth inverter 114. The input end of the first inverter 111 is used for accessing a clock signal, and the output end of the first inverter 111 is respectively connected with the input end of the second inverter 112 and the input end of the third inverter 113; the output end of the second inverter 112 is used for outputting the first driving signal; the output end of the third inverter 113 is connected to the input end of the fourth inverter 114, and the output end of the fourth inverter 114 is used for outputting the second driving signal. In each transmission gate shown in fig. 4a, S1 (e.g., the gate of the first MOS transistor NM1 in K2) and S3 (e.g., the gate of the first MOS transistor NM1 in K1) represent ports for accessing the first driving signal; s2 (e.g. the gate of the second MOS transistor PM1 in K2), S4 (e.g. the gate of the second MOS transistor PM1 in K1) represent ports for accessing the second driving signal.

Alternatively, in the chopper switch, the correspondence between the transmission gate and the driving switch 110 may be set according to the related driving requirement. For example, referring to fig. 4d, the second and third transfer gates K2 and K3 may correspond to the driving switch 110a, and the first and fourth transfer gates K1 and K4 may correspond to the driving switch 110a and may correspond to the driving switch 110b. At this time, the driving switch 110a includes a first inverter 111a, a second inverter 112a, a third inverter 113a and a fourth inverter 114a, the first driving signal output by the third inverter 113a is respectively provided to the gates of the first MOS transistor NM1 in the second transmission gate K2 and the third transmission gate K3, and the second driving signal output by the fourth inverter 114a is respectively provided to the gates of the second MOS transistor PM1 in the second transmission gate K2 and the third transmission gate K3. The driving switch 110b includes a first inverter 111b, a second inverter 112b, a third inverter 113b and a fourth inverter 114b, wherein the first driving signal output by the third inverter 113b is respectively provided to the gates of the first MOS transistor NM1 in the first transmission gate K1 and the fourth transmission gate K4, and the second driving signal output by the fourth inverter 114a is respectively provided to the gates of the second MOS transistor PM1 in the first transmission gate K1 and the fourth transmission gate K4. SW1 in fig. 4d represents a first clock terminal of a chopper switch, the first clock terminal SW1 of which chopper switch comprises a first clock terminal SW11 of a first chopper switch 100 and a first clock terminal SW21 of a second chopper switch 200; SW2 denotes a second clock terminal of the chopping switch, and the first clock terminal SW2 of the chopping switch includes the second clock terminal SW12 of the first chopping switch 100 and the second clock terminal SW22 of the second chopping switch 200.

In one embodiment, the amplifying circuit further comprises a clock generation module; the clock generation module is configured to access an external clock CLK to generate a first clock and a second clock corresponding to the first chopper switch 100, and a second clock and a third clock corresponding to the second chopper switch 200. The clock generation module provided by the embodiment can provide an effective clock for the corresponding chopper switch, particularly for the transmission gate with larger size, and the transmission gate has a certain parasitic capacitance.

Accordingly, the first chopper switch 100 is disposed on the first clock terminal SW11 and the second clock terminal SW12, the first clock terminal SW11 of the first chopper switch 100 is used for accessing the first clock, and the second clock terminal SW12 is used for accessing the second clock. The second chopper switch 200 is disposed on a first clock end SW21 and a second clock end SW22, the first clock end SW21 of the second chopper switch 200 is used for accessing a third clock, and the second clock end SW22 is used for accessing a fourth clock.

In one example, referring to fig. 5a and 5b, the clock generation module includes a fifth inverter 331, a first and gate 332, a second and gate 333, a sixth inverter 334, a seventh inverter 335, and two delay units 340; as shown in fig. 5b, the delay unit 340 may include a first delay unit 340a connected to the second clock terminal SW22 of the second chopping switch 200 and a second delay unit 340b connected to the first clock terminal SW21 of the second chopping switch 200.

The input end of the fifth inverter 331 is connected to the first input end of the first and gate 332, and is used for accessing the external clock CLK, and the output end is connected to the first input end of the second and gate 333. A second input terminal of the second and gate 333 is connected to the first clock terminal SW11 of the first chopper switch 100, and an output terminal thereof is connected to the second clock terminal SW12 of the first chopper switch 100 through the seventh inverter 335. A second input terminal of the first and gate 332 is connected to the second clock terminal SW12 of the first chopper switch 100, and an output terminal thereof is connected to the first clock terminal SW11 of the first chopper switch 100 through the sixth inverter 334. The output end of the seventh inverter 335 is further connected to the first clock end SW21 of the second chopper switch 200 through a delay unit 340; the output terminal of the sixth inverter 334 is further connected to the second clock terminal SW22 of the second chopper switch 200 through a delay unit 340.

The clock generation module provided in this example is configured to input a first clock to the first clock terminal SW11 of the first chopper switch 100, input a second clock to the second clock terminal SW12 of the first chopper switch 100, input a third clock to the first clock terminal SW21 of the second chopper switch 200, and input a fourth clock to the second clock terminal SW22 of the second chopper switch 200. The clock generation module adopts a non-overlapping clock, so that the two sides of the first chopping switch 100 and the second chopping switch 200 can be prevented from being conducted simultaneously; there is a certain transmission delay for the signal transmitted from the first chopper switch 100 to the second chopper switch 200, so that a corresponding delay unit 340 is added between the clock terminal SW2x of the second chopper switch 200 and the clock terminal SW1x of the first chopper switch 100, so that the input clock signal can be more accurate.

Alternatively, the delay unit 340 may adopt an RC delay structure.

In one example, as shown in fig. 5b, the delay unit 340 (the first delay unit 340a and the second delay unit 340 b) includes an eighth inverter 341, a fifth resistor R5, a third MOS transistor PM2, a fourth MOS transistor NM2, a ninth inverter 342, and a tenth inverter 343.

An input end of the eighth inverter 341 is connected to a clock end of the first chopper switch 100, and an output end of the eighth inverter is connected to a first end of the fifth resistor R5; for example, in the first delay unit 340a, an input terminal of the eighth inverter 341 is connected to the first clock terminal SW11 of the first chopper switch 100, and in the second delay unit 340b, an input terminal of the eighth inverter 341 is connected to the second clock terminal SW12 of the first chopper switch 100. The second end of the fifth resistor R5 is connected to the gate of the third MOS transistor PM2, the gate of the fourth MOS transistor NM2, and the input end of the ninth inverter 342, respectively. The source electrode of the third MOS tube PM2 is respectively connected with an external power supply and the drain electrode of the third MOS tube PM 2. The source electrode of the fourth MOS tube NM2 is respectively connected with the ground terminal and the drain electrode of the fourth MOS tube NM 2. An output terminal of the ninth inverter 342 is connected to a clock terminal of the second chopper switch 200 through the tenth inverter 343; specifically, as shown in fig. 5b, in the first delay unit 340a, the output terminal of the tenth inverter 343 is connected to the second clock terminal SW22 of the second chopper switch 200, and in the second delay unit 340b, the output terminal of the tenth inverter 343 is connected to the first clock terminal SW21 of the second chopper switch 200.

Optionally, the resistance of the fifth resistor R5 is equal to the resistance of the input resistor. Namely, the resistance values of the fifth resistor R5, the first resistor RN1 and the second resistor RN1 are equal. Optionally, the third MOS tube PM2 and the fourth MOS tube NM2 are respectively consistent with the size of the transmission gate in the chopper switch, so that the branch for processing the first input signal and the branch for processing the second input signal in the amplifying circuit are symmetrical to each other, and offset voltage in the amplifying circuit can be effectively reduced.

Further, the first clock connected to the first clock terminal SW11 of the first chopper switch 100 and the second clock connected to the second clock terminal SW12 of the second chopper switch 100, the third clock connected to the first clock terminal SW21 of the second chopper switch 200 and the fourth clock connected to the second clock terminal SW22 of the second chopper switch 200 may be as shown in fig. 6, and the characteristics of fig. 6 are characterized in that the fourth clock connected to the second clock terminal SW22 of the second chopper switch 200 has an inverted and delayed characteristic with respect to the first clock connected to the first clock terminal SW11 of the first chopper switch 100, and the third clock connected to the first clock terminal SW21 of the second chopper switch 200 has an inverted and delayed characteristic with respect to the second clock connected to the second clock terminal SW12 of the first chopper switch 100, so that both sides of the corresponding chopper switch can be prevented from being turned on simultaneously.

According to the amplifying circuit, the first chopping switch 100 and the second chopping switch 200 are respectively arranged at the two ends of the input resistor, so that the impedance of the whole input resistor is the average value of all the input resistors involved, mismatch among all the input resistors can be eliminated, the power supply rejection ratio performance can be improved on the premise of not increasing the chip area, the amplifying circuit has a relatively small area, the amplifying circuit has no special requirement on the process, and the corresponding manufacturing cost can be reduced. Wherein each input of chopper switch connects each output through a transmission gate respectively, can improve the linearity of corresponding chopper switch, prevents to produce the influence to THD. And the branch circuit for processing the first input signal and the branch circuit for processing the second input signal are symmetrical, so that offset voltage in the amplifying circuit can be effectively reduced. It can be seen that the above-described amplifying circuit can optimize its performance from various aspects.

The utility model provides a chip in a second aspect, which comprises the amplifying circuit in any embodiment, and can improve the power supply rejection ratio performance on the premise of not increasing the area of the chip, so that the amplifying circuit has a relatively small area, and the amplifying circuit has no special requirements on the process, and can reduce the corresponding manufacturing cost. Specifically, the chip may be an audio power amplifier chip to perform power amplification processing on an input audio signal.

In a fourth aspect, the present utility model provides an electronic device, including an amplifying circuit according to any one of the foregoing embodiments or a chip according to any one of the foregoing embodiments, which may improve power supply rejection ratio performance without increasing a chip area.

Although the utility model has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present utility model includes all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.

That is, the foregoing embodiments of the present utility model are merely examples, and are not intended to limit the scope of the present utility model, and all equivalent structures or equivalent processes using the descriptions of the present utility model and the accompanying drawings, such as the combination of technical features of the embodiments, or direct or indirect application in other related technical fields, are included in the scope of the present utility model.

In addition, the present utility model may be identified by the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present utility model, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described as "exemplary" in this disclosure is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present utility model. In the above description, various details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present utility model may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the utility model. Thus, the present utility model is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims

1. An amplifying circuit is characterized by comprising a first chopping switch, a second chopping switch, an operational amplifier, a PWM modulator, a first resistor, a second resistor, a third resistor and a fourth resistor;

2. The amplifying circuit according to claim 1, wherein the first chopper switch and the second chopper switch each include 4 transmission gates; each transmission gate is connected between one input end and one output end of the corresponding chopping switch, so that each input end of the chopping switch is connected with each output end through one transmission gate.

3. The amplifying circuit according to claim 2, wherein the transmission gate comprises a first MOS transistor and a second MOS transistor; the drain electrode of the first MOS tube is respectively connected with one input end of the chopping switch and the source electrode of the second MOS tube, the grid electrode is used for being connected with a first driving signal, the source electrode is respectively connected with one output end of the chopping switch and the drain electrode of the second MOS tube, and the grid electrode of the second MOS tube is used for being connected with a second driving signal.

4. The amplifying circuit according to claim 3, wherein the chopper switches further comprise drive switches corresponding to the respective transmission gates; the driving switch is used for accessing a clock signal and outputting the first driving signal and the second driving signal.

5. The amplifier circuit of claim 4, wherein the drive switch comprises a first inverter, a second inverter, a third inverter, and a fourth inverter; the input end of the first inverter is used for being connected with a clock signal, the output end of the first inverter is connected with the input end of the second inverter and the input end of the third inverter respectively, the output end of the second inverter is used for outputting the first driving signal, the output end of the third inverter is connected with the input end of the fourth inverter, and the output end of the fourth inverter is used for outputting the second driving signal.

6. The amplifying circuit according to claim 1, further comprising a clock generation module; the clock generation module is used for accessing an external clock to generate a first clock and a second clock corresponding to the first chopping switch, and a second clock and a third clock corresponding to the second chopping switch.

7. The amplifying circuit according to claim 6, wherein the clock generating module comprises a fifth inverter, a first and gate, a second and gate, a sixth inverter, a seventh inverter, and two delay units;

the input end of the fifth inverter is connected with the first input end of the first AND gate and is used for being connected with the external clock, the output end of the fifth inverter is connected with the first input end of the second AND gate, the second input end of the second AND gate is connected with the first clock end of the first chopping switch, the output end of the fifth inverter is connected with the second clock end of the first chopping switch through the seventh inverter, the output end of the fifth inverter is connected with the first clock end of the first chopping switch through the sixth inverter, the output end of the seventh inverter is also connected with the first clock end of the second chopping switch through a delay unit, and the output end of the sixth inverter is also connected with the second clock end of the second chopping switch through a delay unit.

8. The amplifying circuit according to claim 7, wherein the delay unit comprises an eighth inverter, a fifth resistor, a third MOS transistor, a fourth MOS transistor, a ninth inverter, and a tenth inverter;

the input end of the eighth inverter is connected with one clock end of the first chopper switch, the output end of the eighth inverter is connected with the first end of the fifth resistor, the second end of the fifth resistor is respectively connected with the grid electrode of the third MOS tube, the grid electrode of the fourth MOS tube and the input end of the ninth inverter, the source electrode of the third MOS tube is respectively connected with an external power supply and the drain electrode of the third MOS tube, the source electrode of the fourth MOS tube is respectively connected with the ground end and the drain electrode of the fourth MOS tube, and the output end of the ninth inverter is connected with one clock end of the second chopper switch through the tenth inverter.

9. The amplifier circuit of claim 8, wherein the fifth resistor, the first resistor, and the second resistor have equal resistance values.

10. The amplifying circuit according to claim 1, further comprising a first capacitor and a second capacitor; the first capacitor is connected between the first input of the operational amplifier and the first output of the PWM modulator, and the second capacitor is connected between the second input of the operational amplifier and the second output of the PWM modulator.

11. A chip comprising the amplifying circuit of any one of claims 1 to 10.

12. An electronic device comprising an amplifying circuit according to any one of claims 1 to 10 or a chip according to claim 11.