CN103825567A - Operational amplifier circuit - Google Patents
Operational amplifier circuit Download PDFInfo
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- CN103825567A CN103825567A CN201210464966.1A CN201210464966A CN103825567A CN 103825567 A CN103825567 A CN 103825567A CN 201210464966 A CN201210464966 A CN 201210464966A CN 103825567 A CN103825567 A CN 103825567A
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Abstract
The invention discloses an operational amplifier circuit which comprises an output-stage circuit. The output-stage circuit comprises an output transistor pair, a capacitance unit and a switch unit. A drain electrode of a first output transistor of the output transistor pair is coupled to a drain electrode of a second output transistor of the output transistor pair by an output end of the output-stage circuit. The switch unit is coupled between a gate electrode of the first output transistor and a gate electrode of the second output transistor and is coupled to a first end of the capacitance unit. A second end of the capacitance unit is coupled to the output end of the output-stage circuit. Whether a signal transmission path between the grate electrode of the first output transistor and the first end of the capacitance unit is conducted or not or whether a signal transmission path between the gate electrode of the second output transistor and the first end of the capacitance unit is conducted or not can be determined by the switch unit according to control signals.
Description
Technical field
The invention relates to a kind of load driving circuits, and relate to especially a kind of operation amplifier circuit.
Background technology
Operational amplifier is being played the part of considerable role in integrated circuit (IC) design, and it is widely used in stereo system equipment (high-fidelity stereo equipment), microcomputer and other electronic equipment of high-facsimile.One of them driving force for enhancing output signal of the function of operational amplifier, to drive load or next stage circuit.
Fig. 1 illustrates the schematic diagram of known digital control analog voltage drive circuit.Please refer to Fig. 1, this drive circuit 100 comprises digital analog converter 110 (digital to analog converter, DAC) and operational amplifier 120.Digital analog converter 110 is in order to receiving digital signals SD, and by after receiving digital signals SD converting analogue signals SA, then export analog signal SA to operational amplifier 120.In this example, operational amplifier 120, for negative feedback configuration, has single gain (unity gain).In the time that operational amplifier 120 receives different input voltages, its output just can produce different change in voltage, this pace of change is called revolution rate (slew rate), and its value depends on the input stage electric current of operational amplifier 120 and the size of building-out capacitor.
Particularly, in the application of digital control analog voltage drive circuit, the output-stage circuit of operational amplifier 120 can comprise that multiple building-out capacitors strengthen the stability of operational amplifier 120 conventionally.Take the digital signal SD of 8 as example, according to the difference of the highest significant position of digital signal SD (most significant bits, MSB), the output area of digital analog converter 110 can roughly be divided into two parts.Fig. 2 illustrates the contrast schematic diagram of the output area of the corresponding digital analog converter 110 of digital signal.Please refer to Fig. 2, is in the scope of 1 (MSB=1) at the highest significant position of digital signal SD, and corresponding voltage range is roughly high potential output V2 to V3.Be in the scope of 0 (MSB=0) at the highest significant position of digital signal SD, corresponding voltage range is roughly electronegative potential output V1 to V2.Therefore, in response to this kind of digital control approach, the output-stage circuit inside of operational amplifier 120 conventionally can be designed two electric capacity and compensate its stability.One of them electric capacity is responsible for the high potential output of compensating digits analog converter 110, and another electric capacity is wherein responsible for the electronegative potential output of compensating digits analog converter 110.
In this kind of design, building-out capacitor can occupy excessive area conventionally in chip.But, if increase revolution rate and take to reduce the mode of building-out capacitor, can cause again operational amplifier vibration.Therefore how to be, one of important problem in fact in suitable capacitance compensation structure of output-stage circuit design of operational amplifier.
Summary of the invention
The invention provides a kind of operation amplifier circuit, utilize a control signal to switch the extremely different output transistor of building-out capacitor of its output-stage circuit.
The invention provides a kind of operation amplifier circuit, comprise input stage circuit, bias circuit and output-stage circuit.Input stage circuit has input, in order to receive input signal.Bias circuit is coupled to input stage circuit, in order to provide bias current to input stage circuit.Output-stage circuit is coupled to bias circuit.Output-stage circuit has output.Output-stage circuit comprises that output transistor is to, capacitor cell and switch element.Output transistor is to comprising the first output transistor and the second output transistor.First source/drain electrode of the first output transistor is coupled to the first source/drain electrode of the second output transistor via output.Capacitor cell has first end and the second end.The second end of capacitor cell is coupled to the output of output-stage circuit.Switch element is coupled between the grid of first and second output transistor, and is coupled to the first end of capacitor cell.Switch element decides the signaling path between grid and the first end of capacitor cell of conducting the first output transistor according to control signal, or signaling path between grid and the first end of capacitor cell of conducting the second output transistor.
In one embodiment of this invention, above-mentioned capacitor cell comprises the first capacitor.The first capacitor has first end and the second end.The first end of the first capacitor is coupled to the first end of capacitor cell, and the second end of the first capacitor is coupled to the second end of capacitor cell.
In one embodiment of this invention, above-mentioned switch element comprises the first switch and second switch.The first switch has first end, the second end and control end.The first end of the first switch is coupled to the grid of the first output transistor, and the second end of the first switch is coupled to the first end of the first capacitor, and the control end of the first switch is controlled by anti-phase control signal.Second switch has first end, the second end and control end.The second end of second switch is coupled to the grid of the second output transistor, and the first end of second switch is coupled to the first end of the first capacitor, and the control end of second switch is controlled by control signal.
In one embodiment of this invention, in the time of signaling path between first grid of switch conduction the first output transistor and the first end of the first capacitor, second switch disconnects the signaling path between the grid of the second output transistor and the first end of the first capacitor.In the time of signaling path between the grid of second switch conducting the second output transistor and the first end of the first capacitor, the first switch disconnects the signaling path between the grid of the first output transistor and the first end of the first capacitor.
In one embodiment of this invention, above-mentioned capacitor cell comprises multiple the second capacitors.Each the second capacitor has first end and the second end.The first end of each the second capacitor is coupled to the first end of capacitor cell, and the second end of each the second capacitor is coupled to the second end of capacitor cell.
In one embodiment of this invention, above-mentioned switch element comprises multiple the 3rd switches and multiple the 4th switch.Each the 3rd switch has first end, the second end and control end.The first end of each the 3rd switch is coupled to the grid of the first output transistor, and the second end of each the 3rd switch is coupled to the first end of the second different capacitors, and the control end of each the 3rd switch is controlled by anti-phase control signal.Each the 4th switch has first end, the second end and control end.The second end of each the 4th switch is coupled to the grid of the second output transistor, and the first end of each the 4th switch is coupled to the first end of the second different capacitors, and the control end of each the 4th switch is controlled by control signal.
In one embodiment of this invention, in the time of signaling path between each the 3rd grid of switch conduction the first output transistor and the first end of each the second capacitor, each the 4th switch disconnects the signaling path between the grid of the second output transistor and the first end of each the second capacitor.In the time of signaling path between each the 4th grid of switch conduction the second output transistor and the first end of each the second capacitor, each the 3rd switch disconnects the signaling path between the grid of the first output transistor and the first end of each the second capacitor.
In one embodiment of this invention, in the time of signaling path between one of them the 3rd grid of switch conduction the first output transistor and the first end of one of them the second capacitor, other the 3rd switch disconnects the signaling path between the grid of the first output transistor and the first end of other the second capacitor.
In one embodiment of this invention, in the time of signaling path between the grid of Part I the 3rd switch conduction the first output transistor of the 3rd switch and the first end of Part I second capacitor of the second capacitor, the Part II of the 3rd switch the 3rd switch disconnects the signaling path between the grid of the first output transistor and the first end of Part II second capacitor of the second capacitor.
In one embodiment of this invention, in the time of signaling path between one of them the 4th grid of switch conduction the second output transistor and the first end of one of them the second capacitor, other the 4th switch disconnects the signaling path between the grid of the second output transistor and the first end of other the second capacitor.
In one embodiment of this invention, in the time of signaling path between the grid of Part I the 4th switch conduction the second output transistor of the 4th switch and the first end of Part I second capacitor of the second capacitor, the Part II of the 4th switch the 4th switch disconnects the signaling path between the grid of the second output transistor and the first end of Part II second capacitor of the second capacitor.
In one embodiment of this invention, above-mentioned capacitor cell also has the 3rd end and the 4th end.The 3rd end of capacitor cell is coupled to the grid of the first output transistor, and the 4th end of capacitor cell is coupled to the grid of the second output transistor.
In one embodiment of this invention, above-mentioned capacitor cell comprises the 3rd capacitor and the 4th capacitor.The 3rd capacitor has first end and the second end.The first end of the 3rd capacitor is coupled to the grid of the first output transistor, and the second end of the 3rd capacitor is coupled to the output of output-stage circuit.The 4th capacitor has first end and the second end.The second end of the 4th capacitor is coupled to the grid of the second output transistor, and the first end of the 4th capacitor is coupled to the output of output-stage circuit.
In one embodiment of this invention, the output of above-mentioned output-stage circuit is coupled to the input of input stage circuit, forms feedback circuit configuration.
In one embodiment of this invention, second source/drain electrode of the first above-mentioned output transistor is coupled to the first system voltage, and second source/drain electrode of the second output transistor is coupled to second system voltage.
In one embodiment of this invention, above-mentioned control signal is the highest significant position of the digital signal that input signal is corresponding.
Based on above-mentioned, in exemplary embodiment of the present invention, output-stage circuit comprises capacitor cell and switch element.Operation amplifier circuit utilizes control signal to come diverter switch unit, so that capacitor cell can be compensated operation amplifier circuit according to different voltage ranges.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended graphic being described in detail below.
Accompanying drawing explanation
Fig. 1 illustrates the schematic diagram of known digital control analog voltage drive circuit.
Fig. 2 illustrates the contrast schematic diagram of the output area of the corresponding digital analog converter 110 of digital signal.
Fig. 3 illustrates the schematic diagram of the operation amplifier circuit of one embodiment of the invention.
Fig. 4 illustrates the schematic diagram of the operation amplifier circuit of another embodiment of the present invention.
Fig. 5 illustrates the schematic diagram of the operation amplifier circuit of another embodiment of the present invention.
[main element label declaration]
100: digital control analog voltage drive circuit 110: digital analog converter
120: operational amplifier 300,400,500: operation amplifier circuit
310,410,510: input stage circuit 320,420,520: bias circuit
330,430,530: output-stage circuit 332,432,532: capacitor cell
334,434,534: switch element A, B, C, D: each end points of capacitor cell
MN1, MN2, MN3:N type field effect transistor M P1, MP2, MP3:P type field-effect transistor
AVO: output signal AVO, AVP: differential input signal
INV: the reverse input end IN of input stage circuit: the non-inverting input of input stage circuit
SD: digital signal SA: analog signal
IP5, IP6, I7, I8: bias current VDD: the first system voltage
VSS: second system voltage Va, Vb: bias point
OUT: the output CM1 of output-stage circuit: the first capacitor
CM2: the second capacitor CM3: the 3rd capacitor
CM4: the 4th capacitor S: control signal
SB: anti-phase control signal SW1: the first switch
SW2: second switch SW1_1, SW1_2: the 3rd switch
SW2_1, SW2_2: the 4th switch
Embodiment
Fig. 3 illustrates the schematic diagram of the operation amplifier circuit of one embodiment of the invention.Please refer to Fig. 3, the operation amplifier circuit 300 of the present embodiment comprises input stage circuit 310, bias circuit 320 and output-stage circuit 330.Input stage circuit 310 has reverse input end INV and non-inverting input IN, respectively in order to receive differential input signal AVO, AVP.Particularly, in the present embodiment, input stage circuit 310 comprises n type field effect transistor MN1, MN2, MN3, p type field effect transistor MP1, MP2, MP3.N type field effect transistor MN1, MN2 and the differential input of the each self-forming of p type field effect transistor MP1, MP2 are right.In the present embodiment, the reverse input end INV of operation amplifier circuit 300 for example couples with the output OUT of output-stage circuit 330.Therefore, aforementioned two differential inputs, to except receiving differential input signal AVP, also receive the output signal AVO that output-stage circuit 330 is exported, and to form the feedback circuit configuration with single gain, but the present invention is not limited to this.In other embodiments, the reverse input end of input stage circuit 310 also can receive the differential input signal AVN (not illustrating) corresponding to differential input signal AVP.
In the present embodiment, bias circuit 320 is coupled to input stage circuit 320, in order to provide bias current IP5, IP6 to input stage circuit 310.In practice, bias current IP5, IP6 implement with the transistor circuit of current mirror configuration, therefore, n type field effect transistor MN3 in input stage circuit 310 is right in order to coordinate bias current IP5, IP6 to carry out the differential input of bias voltage with p type field effect transistor MP3, as current source.
In the present embodiment, output-stage circuit 330 comprises that complementary output transistor is to MP9, MN9, capacitor cell 332 and switch element 334.Output transistor comprises the first output transistor MP9 and the second output transistor MN9 to MP9, MN9.In this example, both implement with p type field effect transistor and n type field effect transistor respectively.The drain electrode of the first output transistor MP9 is coupled to the drain electrode of the second output transistor MN9 via output OUT.The source electrode of the first output transistor MP9 is coupled to the first system voltage VDD, and the source electrode of the second output transistor MN9 is coupled to second system voltage VSS.
In the time that output-stage circuit 330 need to provide large electric current to driven load or next stage circuit, this operation amplifier circuit 300 can utilize the bias point Va in bias circuit 320, make to there is larger pressure reduction between the source electrode of the first output transistor MP9 and grid, and then provide larger electric current to driven load or next stage circuit.When the load that oneself drive when output-stage circuit 330 needs or next stage circuit are drawn back larger electric current, this operation amplifier circuit 300 can utilize the bias point Vb in bias circuit 320, make to there is larger pressure reduction between the source electrode of the second output transistor MN9 and grid, and then draw back larger electric current from the load or the next stage circuit that drive.
In the present embodiment, capacitor cell 332 is in order to operation amplifier circuit 330 is compensated, to improve its stability.Capacitor cell 332 has first end A and the second end B.The first end A of capacitor cell 332 is coupled to switch element 334.The second end B of capacitor cell 332 is coupled to the output OUT of output-stage circuit 330.Particularly, the capacitor cell 332 of the present embodiment comprises the first capacitor CM1.The first capacitor CM1 has first end and the second end.The first end of the first capacitor CM1 is coupled to the first end A of capacitor cell 332, and the second end of the first capacitor CM1 is coupled to the second end B of capacitor cell 332.
In the present embodiment, switch element 334 is coupled between the grid of the first output transistor MP9 and the second output transistor MN9, and is coupled to the first end A of capacitor cell 332.Switch element 334 decides the signaling path between the grid of conducting the first output transistor MP9 and the first end A of capacitor cell 332 according to control signal S, or signaling path between the grid of conducting the second output transistor MN9 and the first end A of capacitor cell 332.Particularly, the switch element 334 of the present embodiment comprises the first switch SW 1 and second switch SW2.The first switch SW 1 has first end, the second end and control end.The first end of the first switch SW 1 is coupled to the grid of the first output transistor MP9, and the second end of the first switch SW 1 is coupled to the first end A of the first capacitor CM1, and the control end of the first switch SW 1 is controlled by anti-phase control signal SB.Second switch SW2 has first end, the second end and control end.The second end of second switch SW2 is coupled to the grid of the second output transistor MN9, and the first end of second switch SW2 is coupled to the first end A of the first capacitor CM1, and the control end of second switch SW2 is controlled by control signal S.
In the present embodiment, in the time of signaling path between the first grid of switch SW 1 conducting the first output transistor MP9 and the first end A of the first capacitor CM1, second switch SW2 disconnects the signaling path between the grid of the second output transistor MN9 and the first end A of the first capacitor CM1.On the contrary, in the time of signaling path between the grid of second switch SW2 conducting the second output transistor MN9 and the first end A of the first capacitor CM1, the first switch SW 1 disconnects the signaling path between the grid of the first output transistor MP9 and the first end A of the first capacitor CM1.
When the operation amplifier circuit 300 of the present embodiment is applied in digital control analog voltage drive circuit 100, control signal S is for example the highest significant position of digital signal SD.In the time that the highest significant position of digital signal SD is 1 (MSB=1), control signal S=1, anti-phase control signal SB=0, signaling path between both grids of conducting the first output transistor MP9 and the first end A of capacitor cell 332, and disconnect the signaling path between the grid of the second output transistor MN9 and the first end A of the first capacitor CM1.In other words, when operation amplifier circuit 330 operates in the voltage range of high potential output V2 to V3, switch element 334 switches to the signaling path between the grid of the first output transistor MP9 and the first end A of capacitor cell 332, by the first capacitor CM1, operation amplifier circuit 330 is compensated, to improve its stability.
On the other hand, in the time that the highest significant position of digital signal SD is 0 (MSB=0), control signal S=0, anti-phase control signal SB=1, signaling path between first end A the first output transistor of the grid of both conducting the second output transistor MN9 and the first capacitor CM1, and disconnect the signaling path between the grid of MP9 and the first end A of capacitor cell 332.In other words, when operation amplifier circuit 330 operates in the voltage range of electronegative potential output V1 to V2, switch element 334 switches to the signaling path between the grid of the second output transistor MN9 and first end A the first output transistor of the first capacitor CM1, by the first capacitor CM1, operation amplifier circuit 330 is compensated, to improve its stability.
Therefore,, in the application of digital control analog voltage drive circuit, for the compensation of operation amplifier circuit 330 stability, inner single the electric capacity of design that only needs of the output-stage circuit 330 of the present embodiment can compensate its stability.By the switching of switch element 334, this single electric capacity can compensate operation amplifier circuit 330 in different current potential output areas.Therefore,, in the design architecture of the present embodiment, building-out capacitor can not occupy excessive area in chip.In addition, if will increase revolution rate, can reach by the capacitance size of adjusting building-out capacitor.
It should be noted, the control signal of the present embodiment is not limited to the highest significant position of the digital signal of 8.The enforcement aspect of control signal can be arbitrary position of the digital signal of any figure place, or other control signal being set according to the actual requirements by designer.In addition, the range of application of the operation amplifier circuit of the present embodiment is also not limited to digital control analog voltage drive circuit.
Fig. 4 illustrates the schematic diagram of the operation amplifier circuit of another embodiment of the present invention.Please refer to Fig. 3 and Fig. 4, the operation amplifier circuit 400 of the present embodiment is similar to the operation amplifier circuit 300 of Fig. 3, and main difference is for example the circuit structure of capacitor cell 432 and switch element 434 between the two, is described as follows.
The capacitor cell 432 of the present embodiment comprises multiple the second capacitors.In this example, for the purpose of brief description, Fig. 4 only illustrates two the second capacitor CM2_1, CM2_2 in order to illustrate, and its quantity is not in order to limit the present invention.Each the second capacitor has first end and the second end.The first end of the second capacitor CM2_1, CM2_2 is coupled to the first end A of capacitor cell 432, and the second end of the second capacitor CM2_1, CM2_2 is coupled to the second end B of capacitor cell 432.
In the present embodiment, switch element 434 comprises multiple the 3rd switches and multiple the 4th switch.In this example, for the purpose of brief description, Fig. 4 only illustrates two the 3rd switch SW 1_1, SW1_2 and two the 4th switch SW 2_1, SW2_2 in order to illustrate, and the quantity of indivedual switches is not in order to limit the present invention.In the present embodiment, each the 3rd switch has first end, the second end and control end.Take the 3rd switch SW 1_1 as example, the first end of the 3rd switch SW 1_1 is coupled to the grid of the first output transistor MP9, the second end of the 3rd switch SW 1_1 is coupled to the first end A of the second capacitor CM2_1, and the control end of the 3rd switch SW 1_1 is controlled by anti-phase control signal SB.The relation that couples of the 3rd switch SW 1_2 and other circuit element can be analogized by Fig. 4, does not repeat them here.It is worth mentioning that, the second end of the 3rd switch SW 1_1, SW1_2 is to be coupled to the second different capacitor CM2_1, the first end A of CM2_2.
In the present embodiment, each the 4th switch has first end, the second end and control end.Take the 4th switch SW 2_1 as example, the first end of the 4th switch SW 2_1 is coupled to the first end A of the second capacitor CM2_1, the second end of the 4th switch SW 2_1 is coupled to the grid of the second output transistor MN9, and the control end of the 4th switch SW 2_1 is controlled by control signal S.The relation that couples of the 4th switch SW 2_2 and other circuit element can be analogized by Fig. 4, does not repeat them here.It is worth mentioning that, the first end of the 4th switch SW 2_1, SW2_2 is to be coupled to the second different capacitor CM2_1, the first end A of CM2_2.
From another viewpoint, if the second capacitor CM2_1, the 3rd switch SW 1_1 and the 4th switch SW 2_1 are considered as to a compensating module, this compensating module can be carried out as the compensate function of the capacitor cell 332 of Fig. 3 and switch element 334.Therefore, a from then on viewpoint, the capacitor cell 432 of the present embodiment and switch element 434 can be considered the coupled in parallel of multiple above-mentioned compensating modules.
In the present embodiment, in the time of signaling path between each the 3rd grid of switch conduction the first output transistor MP9 and the first end A of each the second capacitor, each the 4th switch disconnects the signaling path between the grid of the second output transistor MN9 and the first end A of each the second capacitor.On the contrary, in the time of signaling path between each the 4th grid of switch conduction the second output transistor MN9 and the first end A of each the second capacitor, each the 3rd switch disconnects the signaling path between the grid of the first output transistor MP9 and the first end A of each the second capacitor.
In the enforcement aspect of multiple the second electric capacity, in the time of signaling path between one of them the 3rd grid of switch conduction the first output transistor MP9 and the first end A of one of them the second capacitor, other the 3rd switch disconnects the signaling path between the grid of the first output transistor MP9 and the first end A of other the second capacitor.For example, in the present embodiment, in the time of signaling path between the 3rd grid of switch SW 1_1 conducting the first output transistor MP9 and the first end A of the second capacitor CM2_1, the 3rd switch SW 1_2 disconnects the signaling path between the grid of the first output transistor MP9 and the first end A of the second capacitor CM2_2.
Similarly, in the enforcement aspect of multiple the second electric capacity, in the time of signaling path between one of them the 4th grid of switch conduction the second output transistor MN9 and the first end of one of them the second capacitor, other the 4th switch disconnects the signaling path between the grid of the second output transistor MN9 and the first end of other the second capacitor.For example, in the present embodiment, in the time of signaling path between the 4th grid of switch SW 2_1 conducting the second output transistor MN9 and the first end A of the second capacitor CM2_1, the 4th switch SW 2_2 disconnects the signaling path between the grid of the second output transistor MN9 and the first end A of the second capacitor CM2_2.
In other words, in the present embodiment, multiple the 3rd switches only have one to be switched on the time, and multiple the 4th switches also only have one to be switched on the time, but the present invention is not limited to this.In another embodiment, in multiple the 3rd switches, likely part is switched on simultaneously, and another part is disconnected simultaneously.And also likely part is switched in multiple the 4th switches simultaneously, another part is disconnected simultaneously.
For example, in the enforcement aspect of the second capacitor more than three, when Part I the 3rd switch of multiple the 3rd switches, for example specific several the 3rd switch wherein, when signaling path between the first end A of the grid of conducting the first output transistor MP9 and part the second capacitor, the Part II of the 3rd switch the 3rd switch, for example other remaining the 3rd switch, disconnects the signaling path between the grid of the first output transistor MP9 and the first end A of another part the second capacitor.Similarly, when Part I the 4th switch of multiple the 4th switches, for example specific several the 4th switch wherein, when signaling path between the first end A of the grid of conducting the second output transistor MN9 and part the second capacitor, the Part II of the 4th switch the 4th switch, for example other remaining the 4th switch, disconnects the signaling path between the grid of the second output transistor MN9 and the first end A of another part the second capacitor.
Fig. 5 illustrates the schematic diagram of the operation amplifier circuit of another embodiment of the present invention.Please refer to Fig. 3 and Fig. 5, the operation amplifier circuit 500 of the present embodiment is similar to the operation amplifier circuit 300 of Fig. 3, and main difference is for example the circuit structure of capacitor cell 532 between the two, is described as follows.
The capacitor cell 532 of the present embodiment also has the 3rd end C and the 4th end D.The 3rd end C of capacitor cell 532 is coupled to the grid of the first output transistor MP9, and the 4th end D of capacitor cell 532 is coupled to the grid of the second output transistor MN9.Particularly, in the present embodiment, capacitor cell 532 also comprises the 3rd capacitor CM3 and the 4th capacitor CM4.The 3rd capacitor CM3 has first end and the second end.The first end of the 3rd capacitor CM3 is coupled to the grid of the first output transistor MP9, and the second end of the 3rd capacitor CM3 is coupled to the output OUT of output-stage circuit 530.The 4th capacitor CM4 has first end and the second end.The second end of the 4th capacitor CM4 is coupled to the grid of the second output transistor MN9, and the first end of the 4th capacitor CM4 is coupled to the output OUT of output-stage circuit 530.
From the viewpoint of circuit operation, when the first switch SW 1 conducting, when second switch SW2 disconnects, the first capacitor CM1 forms configuration in parallel with the 3rd capacitor CM3, is equivalent to a building-out capacitor, so that operation amplifier circuit 500 is compensated.On the contrary, when second switch SW2 conducting, when the first switch SW 1 disconnects, the first capacitor CM1 forms configuration in parallel with the 4th capacitor CM4, is equivalent to another building-out capacitor, also can compensate operation amplifier circuit 500.
In sum, in exemplary embodiment of the present invention, output-stage circuit comprises capacitor cell and switch element.Operation amplifier circuit utilizes control signal to come diverter switch unit, so that capacitor cell can be compensated operation amplifier circuit according to different voltage ranges.This kind of project organization, except can saving chip area, more can improve the driving force of operation amplifier circuit.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention; under any, in technical field, have and conventionally know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the appended claim scope person of defining.
Claims (16)
1. an operation amplifier circuit, comprising:
Input stage circuit, has input, in order to receive input signal;
Bias circuit, is coupled to described input stage circuit, in order to provide bias current to described input stage circuit; And
Output-stage circuit, is coupled to described bias circuit, has output, and described output-stage circuit comprises:
Output transistor pair, comprises the first output transistor and the second output transistor, and first source/drain electrode of described the first output transistor is coupled to the first source/drain electrode of described the second output transistor via described output;
Capacitor cell, has first end and the second end, and the second end of described capacitor cell is coupled to the output of described output-stage circuit; And
Switch element, is coupled between the grid of described first and second output transistor, and is coupled to the first end of described capacitor cell,
Wherein said switch element decides the signaling path between the grid of the first output transistor and the first end of described capacitor cell described in conducting according to control signal, or the signaling path between the grid of the second output transistor and the first end of described capacitor cell described in conducting.
2. operation amplifier circuit according to claim 1, wherein said capacitor cell comprises:
The first capacitor, has first end and the second end, and the first end of described the first capacitor is coupled to the first end of described capacitor cell, and the second end of described the first capacitor is coupled to the second end of described capacitor cell.
3. operation amplifier circuit according to claim 2, wherein said switch element comprises:
The first switch, there is first end, the second end and control end, the first end of described the first switch is coupled to the grid of described the first output transistor, the second end of described the first switch is coupled to the first end of described the first capacitor, and the control end of described the first switch is controlled by anti-phase described control signal; And
Second switch, there is first end, the second end and control end, the second end of described second switch is coupled to the grid of described the second output transistor, and the first end of described second switch is coupled to the first end of described the first capacitor, and the control end of described second switch is controlled by described control signal.
4. operation amplifier circuit according to claim 3, wherein in the time of signaling path between the grid of the first output transistor described in described the first switch conduction and the first end of described the first capacitor, described second switch disconnects the signaling path between the grid of described the second output transistor and the first end of described the first capacitor, and in the time of signaling path between the grid of the second output transistor described in described second switch conducting and the first end of described the first capacitor, described the first switch disconnects the signaling path between the grid of described the first output transistor and the first end of described the first capacitor.
5. operation amplifier circuit according to claim 1, wherein said capacitor cell comprises:
Multiple the second capacitors, described each the second capacitor has first end and the second end, and the first end of described each the second capacitor is coupled to the first end of described capacitor cell, and the second end of described each the second capacitor is coupled to the second end of described capacitor cell.
6. operation amplifier circuit according to claim 5, wherein said switch element comprises:
Multiple the 3rd switches, described each the 3rd switch has first end, the second end and control end, the first end of described each the 3rd switch is coupled to the grid of described the first output transistor, the second end of described each the 3rd switch is coupled to the first end of different described the second capacitors, and the control end of described each the 3rd switch is controlled by anti-phase described control signal; And
Multiple the 4th switches, described each the 4th switch has first end, the second end and control end, the second end of described each the 4th switch is coupled to the grid of described the second output transistor, the first end of described each the 4th switch is coupled to the first end of different described the second capacitors, and the control end of described each the 4th switch is controlled by described control signal.
7. operation amplifier circuit according to claim 6, wherein when described in described each the 3rd switch conduction when the signaling path between the grid of the first output transistor and the first end of described each the second capacitor, described each the 4th switch disconnects the signaling path between the grid of described the second output transistor and the first end of described each the second capacitor, and when described in described each the 4th switch conduction when the signaling path between the grid of the second output transistor and the first end of described each the second capacitor, described each the 3rd switch disconnects the signaling path between the grid of described the first output transistor and the first end of described each the second capacitor.
8. operation amplifier circuit according to claim 6, wherein, when described in one of them the 3rd switch conduction of described the 3rd switch when the signaling path between the grid of the first output transistor and the first end of one of them the second capacitor of described the second capacitor, described other the 3rd switch disconnects the signaling path between the grid of described the first output transistor and the first end of described other the second capacitor.
9. operation amplifier circuit according to claim 6, wherein, in the time of signaling path between the grid of the first output transistor described in Part I the 3rd switch conduction of described the 3rd switch and the first end of Part I second capacitor of described the second capacitor, the Part II of described the 3rd switch the 3rd switch disconnects the signaling path between the grid of described the first output transistor and the first end of Part II second capacitor of described the second capacitor.
10. operation amplifier circuit according to claim 6, wherein, when described in one of them the 4th switch conduction of described the 4th switch when the signaling path between the grid of the second output transistor and the first end of one of them the second capacitor of described the second capacitor, described other the 4th switch disconnects the signaling path between the grid of described the second output transistor and the first end of described other the second capacitor.
11. operation amplifier circuits according to claim 6, wherein, in the time of signaling path between the grid of the second output transistor described in Part I the 4th switch conduction of described the 4th switch and the first end of Part I second capacitor of described the second capacitor, the Part II of described the 4th switch the 4th switch disconnects the signaling path between the grid of described the second output transistor and the first end of Part II second capacitor of described the second capacitor.
12. operation amplifier circuits according to claim 1, wherein said capacitor cell also has the 3rd end and the 4th end, the 3rd end of described capacitor cell is coupled to the grid of described the first output transistor, and the 4th end of described capacitor cell is coupled to the grid of described the second output transistor.
13. operation amplifier circuits according to claim 12, wherein said capacitor cell comprises:
The 3rd capacitor, has first end and the second end, and the first end of described the 3rd capacitor is coupled to the grid of described the first output transistor, and the second end of described the 3rd capacitor is coupled to the output of described output-stage circuit; And
The 4th capacitor, has first end and the second end, and the second end of described the 4th capacitor is coupled to the grid of described the second output transistor, and the first end of described the 4th capacitor is coupled to the output of described output-stage circuit.
14. operation amplifier circuits according to claim 1, the output of wherein said output-stage circuit is coupled to the input of described input stage circuit, forms feedback circuit configuration.
15. operation amplifier circuits according to claim 1, second source/drain electrode of wherein said the first output transistor is coupled to the first system voltage, and second source/drain electrode of described the second output transistor is coupled to second system voltage.
16. operation amplifier circuits according to claim 1, wherein said control signal is the highest significant position of the digital signal that described input signal is corresponding.
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| CN201210464966.1A CN103825567B (en) | 2012-11-16 | 2012-11-16 | Operation amplifier circuit |
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| CN201210464966.1A CN103825567B (en) | 2012-11-16 | 2012-11-16 | Operation amplifier circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107666310A (en) * | 2016-07-29 | 2018-02-06 | 奕力科技股份有限公司 | Output buffer device |
| CN113258891A (en) * | 2020-02-12 | 2021-08-13 | 奇景光电股份有限公司 | Operational amplifier |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101588160B (en) * | 2008-05-20 | 2013-01-02 | 联咏科技股份有限公司 | Operational amplifier capable of improving slew rate and related method thereof |
| CN101674057B (en) * | 2008-09-09 | 2013-07-24 | 联咏科技股份有限公司 | Rail-to-rail operational amplifier capable of lowering power consumption |
| CN102201790B (en) * | 2010-03-26 | 2013-11-13 | 联咏科技股份有限公司 | Coupling blocking method and operational amplifier |
| JP5665641B2 (en) * | 2010-06-08 | 2015-02-04 | ルネサスエレクトロニクス株式会社 | Output circuit, data driver, and display device |
| CN102487266A (en) * | 2010-12-02 | 2012-06-06 | 联咏科技股份有限公司 | Operational amplifier and display driving circuit applying same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107666310A (en) * | 2016-07-29 | 2018-02-06 | 奕力科技股份有限公司 | Output buffer device |
| CN113258891A (en) * | 2020-02-12 | 2021-08-13 | 奇景光电股份有限公司 | Operational amplifier |
| CN113258891B (en) * | 2020-02-12 | 2024-02-06 | 奇景光电股份有限公司 | Operational amplifier |
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