CN217158188U - 沟槽式功率半导体装置 - Google Patents

沟槽式功率半导体装置 Download PDF

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CN217158188U
CN217158188U CN202220686841.2U CN202220686841U CN217158188U CN 217158188 U CN217158188 U CN 217158188U CN 202220686841 U CN202220686841 U CN 202220686841U CN 217158188 U CN217158188 U CN 217158188U
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epitaxial layer
active device
power semiconductor
semiconductor device
trench
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刘莒光
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Excelliance Mos Corp
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Abstract

本实用新型提供一种沟槽式功率半导体装置，包括基板、外延层、漏极电极、第一有源器件、第二有源器件以及数个隔离沟槽结构。外延层设置于基板的一面，漏极电极设置于基板的另一面。第一有源器件设置于外延层的第一部分中，并具有第一源极电极与第一栅极电极。第二有源器件设置于外延层的第二部分中，并具有第二源极电极与第二栅极电极。隔离沟槽结构设置于外延层的所述第一部分与所述第二部分之间，以电隔离第一有源器件与第二有源器件。本实用新型提供的沟槽式功率半导体装置，能改善同一基板上的两个有源器件之间的电性隔绝能力，以且不需要额外长时间的热氧化处理或额外的光掩膜工艺。

Description

沟槽式功率半导体装置
技术领域
本实用新型涉及一种功率半导体技术，尤其涉及一种沟槽式功率半导体装置。
背景技术
功率半导体器件一般用于开关模式电源或其他高速电源开关的装置中。为了更高的器件密度，功率半导体器件多采取垂直结构的设计，其利用芯片背面作为漏极，而于芯片正面制作源极以及栅极。
传统的功率半导体器件会根据应用电压范围的不同，制作在不同的芯片上，再利用晶片级封装进行电路连接，以避免漏电或产生其他电性问题。
然而，分开制作在不同芯片的方式既浪费时间也会增加制造成本。目前虽然也有利用厚氧化层等结构来进行器件电隔离，但是仍需要额外的步骤来形成厚氧化层。
实用新型内容
本实用新型提供一种沟槽式功率半导体装置，能改善同一基板上的两个有源器件之间的电性隔绝能力，以且不需要额外长时间的热氧化处理或额外的光掩膜工艺。
本实用新型的一种沟槽式功率半导体装置，包括基板、外延层、漏极电极、第一有源器件、第二有源器件以及数个隔离沟槽结构。基板具有相对的第一表面与第二表面。外延层设置于基板的所述第一表面。漏极电极设置于基板的所述第二表面。第一有源器件设置于外延层的第一部分中，具有第一源极电极与第一栅极电极。第二有源器件设置于外延层的第二部分中，具有第二源极电极与第二栅极电极。数个隔离沟槽结构设置于外延层的所述第一部分与所述第二部分之间，以电隔离第一有源器件与第二有源器件。
在本实用新型的实施例中，上述隔离沟槽结构的数目为3以上。
在本实用新型的实施例中，上述第一有源器件与上述第二有源器件之间的跨压值与隔离沟槽结构的数目正相关。
在本实用新型的实施例中，每个所述隔离沟槽结构包括浮动电位的多晶硅结构与绝缘层。所述多晶硅结构是从外延层的表面延伸至外延层内，而绝缘层介于多晶硅结构与外延层之间。
在本实用新型的实施例中，上述第一有源器件包括具有第一导电型的所述外延层、具有第二导电型的第一井区、数个第一沟槽式栅极结构、上述第一栅极电极、具有第一导电型的第一源极区以及上述第一源极电极。第一井区位于所述外延层内。第一沟槽式栅极结构设置于所述外延层内并从外延层的表面延伸至第一井区下方。第一栅极电极设置于外延层上方并电连接所述第一沟槽式栅极结构。第一源极区位于所述外延层的表面，第一源极电极则设置于外延层上方并电连接所述第一源极区。
在本实用新型的实施例中，上述沟槽式功率半导体装置还可包括具有第二导电型的数个第一重掺杂区，形成在第一源极电极下方的第一井区内，且第一源极电极电连接第一重掺杂区。
在本实用新型的实施例中，上述第一栅极电极包围上述第一源极电极。
在本实用新型的实施例中，上述第二有源器件包括具有第一导电型的所述外延层、具有第二导电型的第二井区、数个第二沟槽式栅极结构、上述第二栅极电极、具有第一导电型的第二源极区以及上述第二源极电极。第二井区位于所述外延层内。第二沟槽式栅极结构设置于所述外延层内并从外延层的表面延伸至第二井区下方。第二栅极电极设置于所述外延层上方并电连接所述第二沟槽式栅极结构。第二源极区位于所述外延层的表面，而第二源极电极设置于外延层上方并电连接所述第二源极区。
在本实用新型的实施例中，上述沟槽式功率半导体装置还可包括具有第二导电型的数个第二重掺杂区，形成在第二源极电极下方的第二井区内，且第二源极电极电连接第二重掺杂区。
在本实用新型的实施例中，上述第二栅极电极包围上述第二源极电极。
在本实用新型的实施例中，上述基板为具有第一导电型的半导体基板。
在本实用新型的实施例中，上述第一导电型为N型，上述第二导电型为P型。
在本实用新型的实施例中，上述第一导电型为P型，上述第二导电型为N型。
在本实用新型的实施例中，上述第一有源器件与上述第二有源器件具有相同的面积。
在本实用新型的实施例中，上述第一有源器件的面积小于上述第二有源器件的面积。
在本实用新型的实施例中，上述第一有源器件与上述第二有源器件为不对称的结构。
在本实用新型的实施例中，上述第一有源器件与上述第二有源器件为镜像对称的结构。
基于上述，本实用新型利用设置于外延层的第一与第二部分之间的数个隔离沟槽结构来电隔离第一有源器件与第二有源器件，且隔离沟槽结构与有源器件的沟槽式栅极结构基本一样，所以不需要额外长时间的热氧化处理或额外的光掩膜工艺，即可实现在同一基板上设置两个有源器件的目的。
为让本实用新型的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1是依照本实用新型的一实施例的一种沟槽式功率半导体装置的剖面示意图；
图2是上述实施例的沟槽式功率半导体装置的电路图；
图3A是上述实施例的一例的上视示意图；
图3B是上述实施例的另一例的上视示意图；
图3C是上述实施例的再一例的上视示意图。
附图标记说明
100：基板
100a:第一表面
100b:第二表面
102:外延层
102a:表面
104:漏极电极
106:第一有源器件
108:第二有源器件
110:隔离沟槽结构
112:多晶硅结构
114:绝缘层
116:第一沟槽式栅极结构
118:第一源极区
120:第一重掺杂区
122:第二沟槽式栅极结构
124:第二源极区
126:第二重掺杂区
CL:切割道
G1:第一栅极电极
G2:第二栅极电极
ILD:介电层
P1、P2:导电插塞
S1:第一源极电极
S2:第二源极电极
W1:第一井区
W2:第二井区
I:第一部分
II:第二部分
具体实施方式
以下内容提供许多不同的实施方式或实施例，用于实施本实用新型的不同特征。而且，这些实施例仅为示范例，并不用来限制本实用新型的范围与应用。再者，为了清楚起见，各区域或结构器件的相对尺寸(如长度、厚度、间距等)及相对位置可能缩小或放大。另外，在各附图中使用相似或相同的附图标记表示相似或相同器件或特征。
图1是依照本实用新型的一实施例的一种沟槽式功率半导体装置的剖面示意图。
请参照图1，本实施例的沟槽式功率半导体装置包括基板100、外延层102、漏极电极104、第一有源器件106、第二有源器件108以及数个隔离沟槽结构110。基板100具有相对的第一表面100a与第二表面100b。外延层102设置于基板100的第一表面100a。漏极电极104设置于基板100的第二表面100b。第一有源器件106设置于外延层102的第一部分I中，具有第一源极电极S1与第一栅极电极G1。第二有源器件108设置于外延层102的第二部分II中，具有第二源极电极S2与第二栅极电极G2。数个隔离沟槽结构110设置于外延层102的第一部分I与第二部分II之间，以电隔离第一有源器件106与第二有源器件108。
在本实施例中，第一有源器件106以及第二有源器件108可共用漏极(漏极电极104)，亦即图1是一个单晶粒(die)且切割道(cutting line)CL就在第一有源器件106与第二有源器件108的外侧，因此本实施例的沟槽式功率半导体装置的电路图例如图2所示。
在图2中，沟槽式功率半导体装置可以有以下四种操作模式：
第一种模式是输入电压Vin是第一有源器件106的第一源极S1的电压(Vin＝V(S1))、输出电压Vout是第二有源器件108的第二源极S2的电压(Vout＝V(S2))、第一有源器件106的第一栅极G1的电压V(G1)和第二有源器件108的第二栅极G2的电压V(G2)都是低电压。第一源极S1与第二源极S2的电位可以互调。
第二种模式是Vin＝V(S1)、Vout＝V(S2)、V(G1)是高电压、V(G2)是低电压。第一源极S1与第二源极S2的电位可以互调。
第三种模式是Vin＝V(S1)、Vout＝V(S2)、V(G1)是低电压、V(G2)是高电压。第一源极S1与第二源极S2的电位可以互调。
第四种模式是Vin＝V(S1)、Vout＝V(S2)、V(G1)和V(G2)都是高电压。第一源极S1与第二源极S2的电位可以互调。
请再度参照图1，隔离沟槽结构110的数目为4，但本实用新型并不限于此。第一有源器件106与第二有源器件108之间的跨压值(cross voltage)与隔离沟槽结构的数目正相关。举例来说，第一有源器件106与第二有源器件108之间的跨压值是30V，隔离沟槽结构的数目是3的话；若是第一有源器件106与第二有源器件108之间的跨压值高于30V，则隔离沟槽结构的数目可变更为4，依此类推。
在本实施例中，每个隔离沟槽结构110包括浮动电位的多晶硅结构112与绝缘层114。所述多晶硅结构112是从外延层102的表面102a延伸至外延层102内，而绝缘层114介于多晶硅结构112与外延层102之间。
在本实施例中，第一有源器件106包括具有第一导电型的外延层102、具有第二导电型的第一井区W1、数个第一沟槽式栅极结构116、第一栅极电极G1、具有第一导电型的第一源极区118以及第一源极电极S1。在本实施例中，基板100为具有第一导电型的半导体基板，且第一导电型为N型，第二导电型为P型。然而，本实用新型并不限于此；在另一实施例中，第一导电型为P型，第二导电型为N型。第一井区W1位于外延层102内。第一沟槽式栅极结构116设置于外延层102内并从外延层102的表面102a延伸至第一井区W1下方。第一栅极电极G1设置于外延层102上方并电连接第一沟槽式栅极结构116，且第一栅极电极G1可通过设置在介电层ILD的导电插塞P1电连接第一沟槽式栅极结构116。第一源极区118位于外延层102的表面102a，第一源极电极S1则设置于外延层102上方并电连接第一源极区118，且第一源极电极S1可通过设置在介电层ILD的另一导电插塞P1电连接第一源极区118。
在本实施例中，沟槽式功率半导体装置还可包括具有第二导电型的数个第一重掺杂区120，形成在第一源极电极S1下方的第一井区W1内，以增加与第一井区W1的欧姆接触。第一源极电极S1电连接第一重掺杂区120，且第一源极电极S1可通过设置在介电层ILD的导电插塞P1电连接第一重掺杂区120。
在本实施例中，第二有源器件108包括具有第一导电型的外延层102、具有第二导电型的第二井区W2、数个第二沟槽式栅极结构122、第二栅极电极G2、具有第一导电型的第二源极区124以及第二源极电极S2。第二井区W2位于外延层102内。第二沟槽式栅极结构122设置于外延层102内并从外延层102的表面102a延伸至第二井区W2下方。第二栅极电极G2设置于外延层102上方并电连接第二沟槽式栅极结构122，且第二栅极电极G2可通过设置在介电层ILD的导电插塞P2电连接第二沟槽式栅极结构122。第二源极区124位于外延层102的表面102a，而第二源极电极S2设置于外延层102上方并电连接第二源极区124，且第二源极电极S2可通过设置在介电层ILD的另一导电插塞P2电连接第二源极区124。
在本实施例中，沟槽式功率半导体装置还可包括具有第二导电型的数个第二重掺杂区126，形成在第二源极电极S2下方的第二井区W2内，以增加与第二井区W2的欧姆接触。第二源极电极S2电连接第二重掺杂区126，且第二源极电极S2可通过设置在介电层ILD的导电插塞P2电连接第二重掺杂区126。
除了图1所示的第一有源器件106以及第二有源器件108，本实用新型的有源器件也可采用结构上有不同设计的器件，例如省略图1中的部分构件的有源器件，或者在图1中增加结构层或是掺杂区的有源器件，并不局限于本实施例中的内容。
在一实施例中，隔离沟槽结构110的深度可与第一沟槽式栅极结构116的深度一样。在另一实施例中，隔离沟槽结构110的深度可与第二沟槽式栅极结构122的深度一样。在又一实施例中，第一沟槽式栅极结构116的深度可与第二沟槽式栅极结构122的深度一样。当第一沟槽式栅极结构116、第二沟槽式栅极结构122以及隔离沟槽结构110的深度都一样，则三者可利用同一工艺形成。
在图1中，第一井区W1与第二井区W2相邻，且隔离沟槽结构110分别位在部分第一井区W1与部分第二井区W2内，且一部分隔离沟槽结构110从外延层102的表面102a延伸至第一井区W1下方，另一部分隔离沟槽结构110从外延层102的表面102a延伸至第二井区W2下方。然而，本实用新型并不限于此；在另一实施例中，第一井区W1与第二井区W2并不相邻，且隔离沟槽结构110并未设置在第一井区W1与第二井区W2中，而是设置在第一井区W1与第二井区W2之间的外延层102内。
图1显示的是沟槽式功率半导体装置的剖面，而其上视图可以有以下几种范例。
图3A是上述实施例的一例的上视示意图。在图3A中，第一有源器件106与第二有源器件108具有相同的面积，本实用新型的隔离沟槽结构(未示出)则是围绕在第一有源器件106与第二有源器件108之间。在图3A中，第一有源器件106与第二有源器件108为镜像对称的结构，第一栅极电极G1包围第一源极电极S1，且第二栅极电极G2包围第二源极电极S2。
图3B是上述实施例的另一例的上视示意图。在图3B中，第一有源器件106与第二有源器件108具有相同的面积，本实用新型的隔离沟槽结构(未示出)则是围绕在第一有源器件106与第二有源器件108之间。在图3B中，第一有源器件106与第二有源器件108为镜像对称的结构，第一栅极电极G1包围第一源极电极S1，且第二栅极电极G2包围第二源极电极S2。
图3C是上述实施例的再一例的上视示意图。在图3C中，第一有源器件106的面积小于第二有源器件108的面积，本实用新型的隔离沟槽结构(未示出)则是围绕在第一有源器件106与第二有源器件108之间。在图3C中，第一有源器件106与第二有源器件108为不对称的结构，第一栅极电极G1包围第一源极电极S1，且第二栅极电极G2包围第二源极电极S2。
综上所述，本实用新型的沟槽式功率半导体装置是在同一基板上设置两个有源器件，并利用设置在两个有源器件之间的数个隔离沟槽结构来进行电隔离，且隔离沟槽结构与有源器件的沟槽式栅极结构基本一样，所以不需要额外长时间的热氧化处理或额外的光掩膜工艺。而且，本实用新型还可以根据两个有源器件之间的跨压，预先设定隔离沟槽结构的数目。
最后应说明的是：以上各实施例仅用以说明本实用新型的技术方案，而非对其限制；尽管参照前述各实施例对本实用新型进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本实用新型各实施例技术方案的范围。

Claims (17)

1.一种沟槽式功率半导体装置，其特征在于，包括：
基板，具有相对的第一表面与第二表面；
外延层，设置于所述基板的所述第一表面；
漏极电极，设置于所述基板的所述第二表面；
第一有源器件，设置于所述外延层的第一部分中，具有第一源极电极与第一栅极电极；
第二有源器件，设置于所述外延层的第二部分中，具有第二源极电极与第二栅极电极；以及
数个隔离沟槽结构，设置于所述外延层的所述第一部分与所述第二部分之间，以电隔离所述第一有源器件与所述第二有源器件。
2.根据权利要求1所述的沟槽式功率半导体装置，其特征在于，所述数个隔离沟槽结构的数目为3以上。
3.根据权利要求1所述的沟槽式功率半导体装置，其特征在于，所述第一有源器件与所述第二有源器件之间的跨压值与所述数个隔离沟槽结构的数目正相关。
4.根据权利要求1所述的沟槽式功率半导体装置，其特征在于，每个所述隔离沟槽结构包括：
浮动电位的多晶硅结构，从所述外延层的表面延伸至所述外延层内；以及
绝缘层，介于所述多晶硅结构与所述外延层之间。
5.根据权利要求1所述的沟槽式功率半导体装置，其特征在于，所述第一有源器件包括：
具有第一导电型的所述外延层；
具有第二导电型的第一井区，位于所述外延层内；
数个第一沟槽式栅极结构，设置于所述外延层内并从所述外延层的表面延伸至所述第一井区下方；
所述第一栅极电极，设置于所述外延层上方并电连接所述第一沟槽式栅极结构；
具有所述第一导电型的第一源极区，位于所述外延层的所述表面；以及
所述第一源极电极，设置于所述外延层上方并电连接所述第一源极区。
6.根据权利要求5所述的沟槽式功率半导体装置，其特征在于，还包括具有所述第二导电型的数个第一重掺杂区，形成在所述第一源极电极下方的所述第一井区内，且所述第一源极电极电连接所述数个第一重掺杂区。
7.根据权利要求5所述的沟槽式功率半导体装置，其特征在于，所述第一栅极电极包围所述第一源极电极。
8.根据权利要求1所述的沟槽式功率半导体装置，其特征在于，所述第二有源器件包括：
具有第一导电型的所述外延层；
具有第二导电型的第二井区，位于所述外延层内；
数个第二沟槽式栅极结构，设置于所述外延层内并从所述外延层的表面延伸至所述第二井区下方；
所述第二栅极电极，设置于所述外延层上方并电连接所述第二沟槽式栅极结构；
具有所述第一导电型的第二源极区，位于所述外延层的所述表面；以及
所述第二源极电极，设置于所述外延层上方并电连接所述第二源极区。
9.根据权利要求8所述的沟槽式功率半导体装置，其特征在于，还包括具有所述第二导电型的数个第二重掺杂区，形成在所述第二源极电极下方的所述第二井区内，且所述第二源极电极电连接所述数个第二重掺杂区。
10.根据权利要求8所述的沟槽式功率半导体装置，其特征在于，所述第二栅极电极包围所述第二源极电极。
11.根据权利要求5至10中任一所述的沟槽式功率半导体装置，其特征在于，所述基板为具有所述第一导电型的半导体基板。
12.根据权利要求11所述的沟槽式功率半导体装置，其特征在于，所述第一导电型为N型，所述第二导电型为P型。
13.根据权利要求11所述的沟槽式功率半导体装置，其特征在于，所述第一导电型为P型，所述第二导电型为N型。
14.根据权利要求1所述的沟槽式功率半导体装置，其特征在于，所述第一有源器件与所述第二有源器件具有相同的面积。
15.根据权利要求1所述的沟槽式功率半导体装置，其特征在于，所述第一有源器件的面积小于所述第二有源器件的面积。
16.根据权利要求1所述的沟槽式功率半导体装置，其特征在于，所述第一有源器件与所述第二有源器件为不对称的结构。
17.根据权利要求1所述的沟槽式功率半导体装置，其特征在于，所述第一有源器件与所述第二有源器件为镜像对称的结构。
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