CN216719089U

CN216719089U - Server

Info

Publication number: CN216719089U
Application number: CN202123222913.2U
Authority: CN
Inventors: 吕天傲; 钟鹏
Original assignee: Zhejiang Uniview Technologies Co Ltd
Current assignee: Zhejiang Uniview Technologies Co Ltd
Priority date: 2021-12-21
Filing date: 2021-12-21
Publication date: 2022-06-10
Anticipated expiration: 2031-12-21

Abstract

The utility model discloses a server, comprising: the system comprises a first processor, a second processor and a controller, wherein the controller is respectively connected with the first processor and the second processor and is used for respectively configuring parameters for the first processor and the second processor so as to disconnect a high-speed bus connection between the first processor and the second processor and operate different operating systems. Therefore, the method can meet the requirements of servers with different styles and configurations in actual application environments with various requirements, and the problem that services cannot be flexibly adjusted if the requirements change after the servers are configured is solved.

Description

Server

Technical Field

The embodiment of the utility model relates to the technical field of communication, in particular to a server.

Background

The current servers are commonly a single-node two-way server and a multi-node server. The single-node two-way server generally has two CPUs equipped in one server, and the two CPUs are interconnected through a high-speed bus to ensure cache consistency so as to run the same operating system and maximize the performance of the CPUs and IO expansion. Although the multi-path server has a plurality of CPUs, a single server can only run one operating system, and sometimes when partial services need to be deployed in different systems, a plurality of servers are required to be independent; a multi-node server usually configures a plurality of independent server board cards in a single chassis to realize high-density computation, but computation power and IO expansion of a single node are limited due to structural limitations, and different node board cards are relatively independent and cannot run the same operating system. In an actual application environment with various requirements, servers with different styles and configurations are often needed to deal with the requirements, so that the problem that services cannot be flexibly adjusted if the requirements change after the servers are configured is solved.

SUMMERY OF THE UTILITY MODEL

The utility model provides a server, which enables two CPUs in a single-node two-way server to independently run different operating systems.

To achieve the above object, the present invention provides a server, including: the system comprises a first processor, a second processor and a controller, wherein the controller is respectively connected with the first processor and the second processor and is used for respectively configuring parameters for the first processor and the second processor so as to disconnect a high-speed bus connection between the first processor and the second processor and independently operate different operating systems.

Optionally, the server further comprises: the device comprises a first memory and a second memory, wherein the first memory stores a first BIOS module, and the second memory stores a second BIOS module; the controller is used for configuring the first BIOS module to be connected with the first processor and also used for configuring the second BIOS module to be connected with the second processor, and at least one unconfigured high-speed bus signal is arranged between the first BIOS module and the second BIOS module.

Optionally, the controller is configured to configure the first processor with a first control signal so that the first BIOS module is not configured with a high-speed bus signal, and the controller is configured to configure the second processor with a first control signal so that the second BIOS module is not configured with a high-speed bus signal.

Optionally, the server further comprises: the high-speed switch is respectively connected with the controller and the high-speed bus, and the controller is used for configuring the high-speed switch to be disconnected so that the high-speed bus between the first processor and the second processor is in a disconnected state.

Optionally, the server further comprises: and the interface chip is respectively connected with the first processor and the second processor and is used for communication between the first processor and the second processor.

Optionally, the controller is one of a microcontroller, a complex programmable logic controller, and a baseboard management controller.

Optionally, the first memory and the second memory are both FLASH memories.

Optionally, the server further comprises: the controller is used for configuring the analog switch to be switched on or switched off so as to configure the management interface to be connected with the first processor or the second processor.

Optionally, the management interface is one of an external serial port, a VGA debugging interface, or a USB interface.

Optionally, the server further comprises: the first management network port is connected with the first processor, and the second management network port is connected with the second processor; further comprising: the network switching chip and the total management network port connected with the network switching chip, wherein the first management network port and the second management network port are respectively connected with the network switching chip.

Optionally, the first processor includes a first external IO connector, and the second processor includes a second external IO connector.

The server provided by the embodiment of the utility model comprises: the system comprises a first processor, a second processor and a controller, wherein the controller is respectively connected with the first processor and the second processor and is used for respectively configuring parameters for the first processor and the second processor so as to disconnect a high-speed bus connection between the first processor and the second processor and independently operate different operating systems. Therefore, the method can meet the requirements of servers with different styles and configurations in actual application environments with various requirements, and the problem that services cannot be flexibly adjusted if the requirements change after the servers are configured is solved.

Drawings

FIG. 1 is a schematic diagram of a server in the prior art;

fig. 2 is a schematic structural diagram of a server according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a server according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a server according to another embodiment of the present invention;

fig. 5 is a schematic structural diagram of a server according to another embodiment of the present invention;

fig. 6 is a schematic structural diagram of a server according to still another embodiment of the present invention;

fig. 7 is a schematic structural diagram of a server according to another embodiment of the present invention;

fig. 8 is a schematic structural diagram of a server according to another embodiment of the present invention;

fig. 9 is a schematic structural diagram of a server according to still another embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting of the utility model. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic diagram of a server in the prior art. As shown in fig. 1, the server 100 includes: a first processor 101, a second processor 102, and a controller 103, wherein the first processor 101 and the second processor 102 are connected by a high-speed bus 104. The controller 103 is in connection communication with only the first processor 101 for configuring parameters with the first processor 101, and the controller 103 is not in connection communication with the second processor 102. Wherein the first processor 101 and the second processor 102 communicate via a high speed bus 104. The first processor 101 is a master processor, and the second processor 102 is a slave processor. It is known that the first processor 101 and the second processor 102 operate under the same operating system. The server 100 is in a multi-way single node mode of operation. The server 100 cannot meet the requirements of servers with different models and configurations in an actual application environment with various requirements.

And when a single-node server needs to install a plurality of independent operating systems, a plurality of virtual servers need to be simulated by using virtualization software through a virtualization technology, and different operating systems are installed under the virtual servers. However, the virtualization technology has performance loss, and usually requires software to adapt, and has higher requirement on the compatibility of the peripheral. The current 8-way server can be split into 4 two-way servers at most by BMC configuration. However, the server is only minimally split into two-way servers, and the server cannot be further split into one-way servers, which causes the server not to be flexible enough in some application occasions; and the hardware bottom layer does not support the composition of a dual active redundancy system.

Therefore, the server provided by the utility model can be conveniently split into a plurality of relatively independent server systems through one multi-channel server, can run services more efficiently, reduces the workload of software and peripheral adaptation, and increases the stability of the system. The server proposed by the present invention is described below.

Fig. 2 is a schematic structural diagram of a server according to the present invention. As shown in fig. 2, the server 200 includes: a first processor 201, a second processor 202, and a controller 203;

the controller 203 is connected to the first processor 201 and the second processor 202, respectively, and is configured to configure parameters for the first processor 201 and the second processor 202, respectively, so that the first processor 201 and the second processor 202 are disconnected from the high-speed bus 204, and different operating systems are operated independently.

In the server 200, the first processor 201 and the second processor 202 are independent from each other through the above arrangement, and different operating systems can be run. The effect that a single server is used as a plurality of servers independently is achieved. I.e., the server 200 operates in a single-pass, multi-node mode. That is, the server 200 is switched from the multi-path single-node mode in the related art to the single-path multi-node mode. Therefore, the method can meet the requirements of servers with different styles and configurations in actual application environments with various requirements, and the problem that services cannot be flexibly adjusted if the requirements change after the servers are configured is solved.

The conversion of the above-mentioned server operation mode is realized by the following three ways.

First, optionally, as shown in fig. 3, the server 200 further includes: a first memory 205 and a second memory 206, the first memory 205 storing a first BIOS module 207, the second memory 206 storing a second BIOS module 208; the controller 203 is configured to configure the first BIOS module 207 to be connected to the first processor 201, and is further configured to configure the second BIOS module 208 to be connected to the second processor 202, where at least one unconfigured high-speed bus signal is provided between the first BIOS module 207 and the second BIOS module 208.

That is, when a high-speed bus signal is not configured in one of the first BIOS module 207 connected to the first processor 201 or the second BIOS module 208 connected to the second processor 202, the high-speed bus communication between the first processor 201 and the second processor 202 is disconnected. In another embodiment, the first BIOS module 207 connected to the first processor 201 and the second BIOS module 208 connected to the second processor 202 may be configured without high-speed bus signals. Further, the first processor 201 and the second processor 202 in the server 200 are enabled to operate under different operating systems independently.

Second, optionally, the controller 203 is configured to configure the first processor 201 with a first control signal so that the first BIOS module 207 is not configured with a high-speed bus signal, and the controller 203 is configured to configure the second processor 202 with a first control signal so that the second BIOS module 208 is not configured with a high-speed bus signal.

It should be noted that after the first processor 201 and the second processor 202 are powered on, the controller 203 configures a first control signal (high level or low level) to the first processor 201 through the GPIO interface of the first processor 201, and configures a first control signal (high level or low level) to the second processor 202 through the GPIO interface of the second processor 202, where the level signals configured to the first processor 201 and the second processor 202 are the same, the first processor 201 may control the first BIOS module 207 not to configure a high-speed bus signal according to the first control signal configured by the controller 203, and likewise, the second processor 202 may control the second BIOS module 208 not to configure a high-speed bus signal according to the first control signal configured by the controller 203, for example, it may be set in advance, when the controller 203 configures a high-level signal, the first BIOS module 207 does not configure a high-speed bus signal, when the second BIOS module 208 does not configure the high-speed bus signal, or the controller 203 configures the low level signal, the first BIOS module 207 does not configure the high-speed bus signal, and the second BIOS module 208 does not configure the high-speed bus signal. Thus, automatic connection and disconnection of the high-speed bus is realized.

Thirdly, optionally, as shown in fig. 4, the server 200 further includes: a high-speed switch 209, the high-speed switch 209 being respectively connected to the controller 203 and the high-speed bus 204, the controller 203 being configured to open the high-speed switch 209, so that the high-speed bus 204 between the first processor 201 and the second processor 202 is in an open state.

It should be noted that the controller 203 can control the on/off of the high-speed switch 209 through a control signal, so as to disconnect the high-speed bus 204 between the first processor 201 and the second processor 202, and further enable the first processor 201 and the second processor 202 to independently operate under different operating systems.

In the above two modes, the high-speed bus 204 between the first processor 201 and the second processor 202 is disconnected, and the first processor 201 and the second processor 202 respectively and independently operate under different operating systems.

In another embodiment, the server 200 may also be configured in a dual active redundancy mode of operation. In the dual active redundancy mode, optionally, as shown in fig. 5, the server 200 further includes: an interface chip 210, where the interface chip 210 is connected to the first processor 201 and the second processor 202, respectively, and the interface chip 210 is used for communication between the first processor 201 and the second processor 202.

An IO interface is respectively disposed in the first processor 201 and the second processor 202, and the interface chip 210 is connected to the first processor 201 through the IO interface in the first processor 201, and connected to the second processor 202 through the IO interface in the second processor 202. After the interface chip 210 is connected to the first processor 201 and the second processor 202, the dual systems can communicate with each other to ensure service synchronization, and the controller 203 monitors the heartbeat signal between the first processor 201 and the second processor 202 to determine the master-slave relationship between the systems, so that the server 200 operates in the dual active redundancy mode.

It is understood that when both the first processor 201 and the second processor 202 are powered on, a heartbeat signal is sent to the controller 203, for example, the first processor 201 is a master processor by default, and the second processor 202 is a slave processor, then when the controller 203 cannot monitor the heartbeat signal of the first processor 201, the second processor 202 takes over the traffic of the first processor 201 through the interface chip 210, and the first processor 201 tries to recover the function.

Optionally, the Controller 203 is one of a Microcontroller (MCU), a Complex Programmable Logic Device (CPLD), and a Baseboard Management Controller (BMC).

Optionally, the first memory 205 and the second memory 206 are both FLASH memories.

Optionally, as shown in fig. 6, the server 200 further includes: at least one management interface 211, and an analog switch 212 connected to the management interface 211, where the analog switch 212 is connected to the controller 203, and the controller 203 is configured to close or open the analog switch 212 to configure the management interface 211 to connect to the first processor 201 or the second processor 202.

Optionally, the management interface 211 is one of an external serial port, a VGA debugging interface, or a USB interface.

It is understood that the first processor 201 and the second processor 202 share the same management interface regardless of whether the server 200 operates in a single-pass multi-node mode or a dual active redundancy mode. When the controller 203 configures the first processor 201, the analog switch 212 may be configured to be turned on with the first processor 201, and when the controller 203 configures the second processor 202, the analog switch 212 may be configured to be turned on with the second processor 202, so that, although the two processors in the server 200 are under different operating systems, when configuring the two operating systems, the two operating systems are configured through only one management interface 211, and the server 200 does not need to add a new management interface, so as to save space for arranging the ports of the server 200. The analog switch 212 may be a switch tube.

Optionally, as shown in fig. 7, the server 200 further includes: a first management portal 213 and a second management portal 214, wherein the first management portal 213 is connected to the first processor 201, and the second management portal 214 is connected to the second processor 202; further comprising: a network switch chip 215, and a total management network interface 216 connected to the network switch chip 215, wherein the first management network interface 213 and the second management network interface 214 are respectively connected to the network switch chip 215.

It should be noted that the first processor 201 and the second processor 202 are respectively connected with their own management network ports, and these management network ports are connected together through the network switch chip 215 and connected with the external total management network port 216, so that signals can be input to the first processor 201 and the second processor 202 at the same time only through inputting signals through the external total management network port 216, and there is no need to additionally provide a management network port outside, thereby saving the port arrangement space of the server 200. Wherein the network switch chip 215 functions as a switch.

Optionally, as shown in fig. 8, the first processor 201 includes a first external IO connector, and the second processor 202 includes a second external IO connector. The first pair of external IO connectors and the second pair of external IO connectors are used for connecting external equipment.

Optionally, as shown in fig. 9, the first processor 201 and the second processor 202 further include a DDR interface, and the DDR interface is used to connect to an external DDR (Double Data Rate).

The working principle of the server 200 is as follows: in the power-on stage of the whole computer, the controller 203 (including MCU, CPLD, BMC, etc.) determines that the server 200 needs to operate in the single-channel dual-node mode through jumper configuration or internal memory configuration. The controller 203 connects the SPI pins of the two sets of CPUs to two independent flashes loaded with BIOS software, respectively, to provide two sets of independent BIOS for the two CPUs. The controller 203 disconnects the high-speed bus or signal directly interconnected between the two groups of CPUs through the BIOS software configuration shielding mode or the hardware link cutting mode. The controller 203 provides independent POWER-on timing and reset signal control for the two groups of CPUs, and comprises the steps of responding signals such as SLP _ S, PWRGD _ OUT and the like sent by the CPUs, controlling the CPUs and the peripheral POWER supply to be powered on, providing signals such as PWR _ GOOD, RSM _ RST, RST _ SYS, POWER _ BTN and the like for the CPUs, and meeting the requirements of the CPUs when the CPUs are independently started. At the moment, the electrification and the starting of the two groups of CPUs are independent from each other and do not influence each other. The external serial ports of the two groups of CPUs, the VGA, the USB and other debugging interfaces can be switched by using an analog switch or a high-speed switch through the controller 203, so that only one group of debugging interfaces is required to be arranged outside the panel, and the space of an IO interface panel is saved. The two groups of CPUs can be connected to peripheral equipment (such as a hard disk, a network card and the like) through respective independent IO interfaces, and respective operating systems are loaded through the peripheral equipment.

In the single-path dual-node mode system, the dual active redundancy mode can be further configured. The two CPU systems can be interconnected through internal IO buses (including PCIe, network and the like) through IO chips, communication between the two systems is carried out, and service synchronization is guaranteed. The controller 203 is responsible for monitoring heartbeat signals of the two systems and deciding the master-slave relationship between the systems. Therefore, the main and standby redundant systems can be realized through software and hardware configuration.

Based on the above, the utility model provides an implementation mode of splitting a single two-way server into two independent server systems directly running respective operating systems or forming a dual-active redundant system, so that the number of the independent operating systems which can be used by the single server is expanded or the single server is configured into the dual-active redundant server under the condition of not increasing physical servers and not using virtualization software. The method is more flexible in practical application, so that a single server can deal with more different application scenes.

In summary, the controller 203 of the present invention can control the server 200 to operate in a multi-channel mode or a multi-node mode, and the operation mode can be configured by a hardware switch (e.g. a button) or a software switch (e.g. a BIOS option). When the server 200 works in a multi-path mode, a plurality of CPUs of a single server are split into a plurality of groups; each group of CPUs independently work, independently run an operating system and are equivalent to independent servers; each external management interface (such as VGA, serial port, USB, etc.) of the CPU is managed and switched by the controller 203, and only one external interface is presented, which is convenient for management and reduces the physical space occupation of the management interface. When the server 200 is configured in a multi-path mode, dual-system redundancy can be realized through software and hardware configuration, service synchronization is ensured through internal communication, a CPU heartbeat signal is monitored through the controller 203, and a master-slave relationship is determined.

In summary, the server provided in the embodiment of the present invention includes: the system comprises a first processor, a second processor and a controller, wherein the controller is respectively connected with the first processor and the second processor and is used for respectively configuring parameters for the first processor and the second processor so as to disconnect a high-speed bus connection between the first processor and the second processor and run different operating systems. Therefore, the method can meet the requirements of servers with different styles and configurations in actual application environments with various requirements, and the problem that services cannot be flexibly adjusted if the requirements change after the servers are configured is solved.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the utility model. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A server, comprising: the system comprises a first processor, a second processor and a controller, wherein the controller is respectively connected with the first processor and the second processor and is used for respectively configuring parameters for the first processor and the second processor so as to disconnect a high-speed bus connection between the first processor and the second processor and independently operate different operating systems.

2. The server of claim 1, further comprising: the device comprises a first memory and a second memory, wherein the first memory stores a first BIOS module, and the second memory stores a second BIOS module; the controller is used for configuring the first BIOS module to be connected with the first processor and also used for configuring the second BIOS module to be connected with the second processor, and at least one unconfigured high-speed bus signal is arranged between the first BIOS module and the second BIOS module.

3. The server according to claim 2, wherein the controller is configured to configure the first processor with first control signals to disable the first BIOS module from configuring high speed bus signals, and the controller is configured to configure the second processor with first control signals to disable the second BIOS module from configuring high speed bus signals.

4. The server of claim 1, further comprising: the high-speed switch is respectively connected with the controller and the high-speed bus, and the controller is used for configuring the high-speed switch to be disconnected so that the high-speed bus between the first processor and the second processor is in a disconnected state.

5. The server according to any one of claims 1-4, further comprising: and the interface chip is respectively connected with the first processor and the second processor and is used for communication between the first processor and the second processor.

6. The server according to any of claims 1-4, wherein the controller is one of a microcontroller, a complex programmable logic controller, and a baseboard management controller.

7. The server according to any one of claims 1-4, further comprising: the controller is used for configuring the analog switch to be switched on or switched off so as to configure the management interface to be connected with the first processor or the second processor.

8. The server according to claim 7, wherein the management interface is one of an external serial port, a VGA debugging interface or a USB interface.

9. The server according to any one of claims 1-4, further comprising: the first management network port is connected with the first processor, and the second management network port is connected with the second processor;

further comprising: the network switching chip and the total management network port connected with the network switching chip, wherein the first management network port and the second management network port are respectively connected with the network switching chip.

10. The server according to any one of claims 1 to 4, wherein the first processor comprises a first external IO connection port and the second processor comprises a second external IO connection port.