CN112486868B - CPLD (Complex programmable logic device) -based storage double-control synchronization system, method and device and storage medium - Google Patents
CPLD (Complex programmable logic device) -based storage double-control synchronization system, method and device and storage medium Download PDFInfo
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Abstract
The invention provides a double-control synchronization system, a method, equipment and a storage medium based on CPLD storage, wherein the system comprises a master CPLD and a slave CPLD; the main CPLD is connected with a main BMC which is connected with a main CPU; the slave CPLD is connected with a slave BMC which is connected with a slave CPU; the master CPLD is connected with the slave CPLDs, and the master CPLD is connected with a sharing device; the slave CPU sends a request for obtaining the information of the shared device to the slave BMC, the slave BMC forwards the request for obtaining the information of the shared device to the slave CPLD, the slave CPLD sends the request for obtaining the information of the shared device through the master CPLD, and the slave CPU returns the information of the shared device along the original path. The invention introduces the double CPLD and obtains the information of the shared device from the CPLD, thereby avoiding the problem that the master BMC only concentrates on temperature, voltage and fan control and the master BMC returns data to the slave BMC overtime when the double-control BMC accesses the shared device.
Description
Technical Field
The invention belongs to the technical field of storage control, and particularly relates to a CPLD (complex programmable logic device) -based storage double-control synchronization system, method and device and a storage medium.
Background
The BMC is a substrate Management Controller, which is an abbreviation of the Baseboard Management Controller.
CPLD is a Complex programmable logic device for short of Complex Programming logic device.
VPD, which is short for vita Product Data, is a key Product technology, and VPD information of a server includes a Product serial number SN and configuration information such as CPU model number, speed and interface card type of each slot.
PSU is the Power Supply Unit for short, power module.
UI, user Interface for short.
The storage controllers form a double-control architecture setting ten years ago, and after one controller suddenly crashes, the other controller takes over the service. The double-control design greatly improves the data security and the disaster tolerance performance of the equipment. The double control early try also an active-standby structure, namely that one controller is in operation, and the other controller mirrors the service data of the active controller in real time. In recent years, double control is evolved into active-active, two controllers process service data at the same time, the double controllers are divided into a master controller and a slave controller, and the slave controller processes the service and also mirrors the service data information of the master controller in real time.
Each controller is an X86 complex motherboard based on an intel platform. Each controller is provided with a BMC chip which is used for controlling the temperature, voltage and fan of the case and accessing double-control shared devices such as VPD, PSU, UI boards and the like. The BMCs of both controllers have I2C physical connections to the shared device. When the system runs normally, two BMCs cannot access the shared device at the same time, otherwise, the I2C communication specification is violated, the problem of multiple hosts occurs, and communication failure is caused. Therefore, in the storage dual-control scenario, two BMCs must distinguish whether they are masters or slaves.
In normal operation of the storage device, the master BMC will occupy the I2C channel of the shared device, and the slave BMC will not occupy the I2C channel of the shared device.
When the main operating system needs to share the VPD information of the device, a command is issued to the main BMC through the IPMI, the main BMC captures the information in the VPD of the shared device from the I2C, and then data is returned in the original way.
When the slave operating system needs to share the device VPD information, a command is issued to the slave BMC through the IPMI, and the slave BMC acquires the device VPD information through a physical path such as I2C, UART or LAN between the slave BMC and the master BMC. And the master BMC captures the information in the VPD from the I2C and returns data in the original way.
Other special scenarios are: and (5) plugging and unplugging the controller. In practical application, the controller is hot-plugged. When the master controller is plugged out, the slave controller immediately converts the identity of the slave controller into the host.
In the framework described above, each time shared device information is obtained from the BMC, it is accessed by the master BMC. But the master BMC may have many other processes executing (e.g., polling for temperature, voltage, upgrading BIOS, etc.) in addition to accessing the shared devices. Or the BMC program runs some redfish applications. In general, when the master BMC is busy, it will not be able to respond immediately to requests to read the shared device VPD information from the BMC. If the response time is long, it will cause the data returned from the BMC to the slave operating system to time out, eventually causing application failures at the operating system level. The general shared device VPD information acquisition is overtime, which causes the storage cluster establishment of the slave operating system to fail.
This is a disadvantage of the prior art, and therefore, it is very necessary to provide a CPLD-based storage dual-control synchronization system, method, device and storage medium for addressing the above-mentioned disadvantages of the prior art.
Disclosure of Invention
Aiming at the defects that in the prior art, the slave BMC acquires the information of the shared device by depending on the master BMC, the master BMC is busy in service, and the slave BMC responds to the overtime request, so that the slave BMC feeds back the overtime information to the slave operating system, and finally the slave operating system fails to establish a storage cluster, the invention provides a CPLD-based storage double-control synchronization system, method, equipment and storage medium, so as to solve the technical problems.
In a first aspect, the invention provides a dual-control synchronization system based on CPLD storage, which comprises a master CPLD and a slave CPLD;
the main CPLD is connected with a main BMC which is connected with a main CPU;
the slave CPLD is connected with a slave BMC which is connected with a slave CPU;
the master CPLD is connected with the slave CPLDs, and the master CPLD is connected with a sharing device;
the slave CPU sends a request for obtaining the information of the shared device to the slave BMC, the slave BMC forwards the request for obtaining the information of the shared device to the slave CPLD, the slave CPLD sends the request for obtaining the information of the shared device through the master CPLD, and the slave CPU returns the information of the shared device along the original path.
Further, the main CPU sends a request for obtaining the information of the shared device to the main BMC, the main BMC forwards the request for obtaining the information of the shared device to the main CPLD, and the main CPLD obtains the information of the shared device and returns the information of the shared device to the main CPU along the original path.
Further, the shared device includes a VPD, a PSU, and a UI board.
Further, the main CPU sends a request for acquiring the information of the shared device to the main BMC through an IPMI protocol;
the slave CPU sends a request for acquiring the information of the shared device to the slave BMC through an IPMI protocol;
the main BMC forwards a shared device information acquisition request of the main CPU to the main CPLD through the I2C bus;
the slave BMC forwards the slave CPU request for obtaining shared device information to the slave CPLD through the I2C bus. The main CPU and the slave CPU respectively send an IPMI protocol request for acquiring the information of the shared device to the main BMC or the slave BMC through respective centros operating systems
Furthermore, the slave CPLD acquires the shared device information from the master CPLD through the I2C bus, the UART bus or the lattice wishband bus, and the master CPLD returns the shared device information to the slave CPLD through the I2C bus, the UART bus or the lattice wishband bus;
and the main CPLD acquires the shared device information through the I2C bus.
In a second aspect, the present invention provides a CPLD-based storage double-control synchronization method, including the steps of:
s1, after receiving a request for acquiring shared device information from a CPU from a BMC, forwarding the request for acquiring the shared device information to a slave CPLD;
s2, the slave CPLD sends a request for obtaining the information of the shared device through the master CPLD;
and S3, the main CPLD acquires the shared device information and returns the shared device information from the CPU along the original path.
Further, the method also comprises the following steps:
s4, after receiving the request of the main CPU for obtaining the information of the shared device, the main BMC forwards the request for obtaining the information of the shared device to the main CPLD;
and S5, the main CPLD acquires the information of the shared device and returns the information of the shared device to the main CPU along the original path.
Further, in step S3, the master CPLD acquires the shared device information, sends the shared device information to the slave CPLD, the slave CPLD sends the shared device information to the slave BMC, and the slave BMC returns the shared device information to the slave CPU;
in step S5, the main CPLD obtains the shared device information, and sends the shared device information to the main BMC, and the main BMC returns the shared device information to the main CPU.
In a third aspect, a terminal is provided, which includes:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is configured to call and run the computer program from the memory, so that the terminal performs the method of the second aspect.
In a fourth aspect, there is provided a computer storage medium having instructions stored thereon, which when executed on a computer, cause the computer to perform the method of the second aspect.
The beneficial effect of the invention is that,
according to the CPLD-based storage double-control synchronization system, method, equipment and storage medium, the double CPLDs are introduced, the shared device information is obtained from the CPLDs, and the problem that when the double-control BMC accesses the shared device, the main BMC only concentrates on temperature, voltage and fan control, and the main BMC returns data to the slave BMC and overtime occurs is solved.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of the system of the present invention;
FIG. 2 is a first schematic flow chart of the method of the present invention;
FIG. 3 is a second schematic flow chart of the method of the present invention;
in the figure, 1-the primary CPLD; 2-slave CPLD; 3-main BMC; 4-slave BMC; 5-a main CPU; 6-slave CPU; 7-sharing the device.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
as shown in fig. 1, the present invention provides a dual-control synchronization system based on CPLD storage, which includes a master CPLD 1 and a slave CPLD 2;
the main CPLD 1 is connected with a main BMC 3, and the main BMC 3 is connected with a main CPU 5;
the slave CPLD 2 is connected with a slave BMC 4, and the slave BMC 4 is connected with a slave CPU 6;
the master CPLD 1 is connected with the slave CPLD 2, and the master CPLD 1 is connected with a sharing device 7;
the slave CPU 6 sends a request for acquiring the information of the sharing device 7 to the slave BMC 4, the slave BMC 4 forwards the request for acquiring the information of the sharing device 7 to the slave CPLD 2, the slave CPLD 2 sends the request for acquiring the information of the sharing device 7 through the master CPLD 1, and the information of the sharing device 7 is returned to the slave CPU 6 along the original path;
the main CPU 5 sends a request for acquiring the information of the shared device 7 to the main BMC 3, the main BMC 3 forwards the request for acquiring the information of the shared device 7 to the main CPLD 1, and the main CPLD 1 acquires the information of the shared device 7 and returns the information of the shared device 7 to the main CPU 5 along the original path.
In certain embodiments, the shared devices 7 include VPDs, PSUs, and UI boards.
In some embodiments, the main CPU 5 sends a request for obtaining information of the shared device 7 to the main BMC 3 through the IPMI protocol;
the slave CPU 6 sends a request for acquiring the information of the shared device 7 to the slave BMC 4 through an IPMI protocol;
the main BMC 3 forwards a request for acquiring the information of the shared device 7 of the main CPU 5 to the main CPLD 1 through the I2C bus;
the slave BMC 4 forwards a request for acquiring the information of the shared device 7 of the slave CPU 6 to the slave CPLD 2 through the I2C bus;
the slave CPLD 2 acquires shared device information from the master CPLD 1 through an I2C bus, a UART bus or a lattice wisband bus, and the master CPLD 1 returns the shared device information to the slave CPLD 2 through the I2C bus, the UART bus or the lattice wisband bus;
the main CPLD 1 acquires the shared device 7 information through the I2C bus. The lattice wireless band bus supports an I3C bus protocol, the I3C is called an Improved Inter Integrated Circuit, the advantages of I2C and SPI are combined, the double lines are simple, low in power consumption and high in speed, and in-band interruption, dynamic addressing and power management functions are supported. The master CPU 5 and the slave CPU 6 respectively send IPMI protocol requests for acquiring the information of the shared device 7 to the master BMC 3 or the slave BMC 4 through respective centros operating systems.
In some embodiments, the current CPLD performing power-on and power-off control and reset control is added with a shared device information acquisition logic function, a new CPLD chip is not required to be added, the added function is simple, and the upgrading requirement of the current CPLD chip cannot be caused.
Example 2:
as shown in fig. 2, the present invention provides a dual-control synchronization method based on CPLD storage, which includes the following steps:
s1, after receiving a request for acquiring shared device information from a CPU (central processing unit), a slave BMC (baseboard management controller) forwards the request for acquiring the shared device information to a slave CPLD (complex programmable logic device);
s2, the slave CPLD sends a request for obtaining the information of the shared device through the master CPLD;
and S3, the main CPLD acquires the shared device information and returns the shared device information from the CPU along the original path.
Example 3:
as shown in fig. 3, the present invention provides a dual-control synchronization method based on CPLD storage, which includes the following steps:
s1, after receiving a request for acquiring shared device information from a CPU from a BMC, forwarding the request for acquiring the shared device information to a slave CPLD;
s2, the slave CPLD sends a request for obtaining the information of the shared device through the master CPLD;
s3, the main CPLD acquires the information of the shared device and returns the information of the shared device from the CPU along the original path;
s4, after receiving the request of the main CPU for obtaining the information of the shared device, the main BMC forwards the request for obtaining the information of the shared device to the main CPLD;
and S5, the main CPLD acquires the information of the shared device and returns the information of the shared device to the main CPU along the original path.
In some embodiments, in step S3, the master CPLD acquires the shared device information, sends the shared device information to the slave CPLD, the slave CPLD sends the shared device information to the slave BMC, and the slave BMC returns the shared device information to the slave CPU;
in step S5, the main CPLD obtains the shared device information, and sends the shared device information to the main BMC, and the main BMC returns the shared device information to the main CPU.
Example 4:
the present invention provides a terminal, including:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is configured to call and run the computer program from the memory, so that the terminal executes the method described in embodiment 2 or 3.
Example 5:
the present invention provides a computer storage medium having stored therein instructions that, when run on a computer, cause the computer to perform the method of embodiment 2 or embodiment 3 described above.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (8)
1. A double-control synchronization system based on CPLD storage is characterized by comprising a master CPLD and a slave CPLD;
the main CPLD is connected with a main BMC which is connected with a main CPU;
the slave CPLD is connected with a slave BMC which is connected with a slave CPU;
the master CPLD is connected with the slave CPLDs and is connected with a sharing device;
the slave CPU sends a request for obtaining the information of the shared device to the slave BMC, the slave BMC forwards the request for obtaining the information of the shared device to the slave CPLD, the slave CPLD sends the request for obtaining the information of the shared device through the master CPLD, and the slave CPU returns the information of the shared device along the original path;
the main CPU sends a request for obtaining the information of the shared device to the main BMC, the main BMC forwards the request for obtaining the information of the shared device to the main CPLD, and the main CPLD obtains the information of the shared device and returns the information of the shared device to the main CPU along the original path.
2. The CPLD-based storage bi-planar synchronization system of claim 1, wherein the shared devices comprise a VPD, a PSU, and a UI board.
3. The CPLD-based storage dual-control synchronization system of claim 1, wherein the main CPU sends a request for obtaining shared device information to the main BMC via IPMI protocol;
the slave CPU sends a request for acquiring the information of the shared device to the slave BMC through an IPMI protocol;
the main BMC forwards a shared device information acquisition request of the main CPU to the main CPLD through the I2C bus;
the slave BMC forwards the slave CPU request for obtaining shared device information to the slave CPLD through the I2C bus.
4. The CPLD-based storage bi-planar synchronization system of claim 3, wherein the slave CPLD obtains shared device information to the master CPLD via the I2C bus, the UART bus, or the lattice wisband bus, and the master CPLD returns shared device information to the slave CPLD via the I2C bus, the UART bus, or the lattice wisband bus;
and the main CPLD acquires the shared device information through the I2C bus.
5. A double-control synchronization method based on CPLD storage is characterized by comprising the following steps:
s1, after receiving a request for acquiring shared device information from a CPU from a BMC, forwarding the request for acquiring the shared device information to a slave CPLD;
s2, the slave CPLD sends a request for obtaining the shared device information through the master CPLD;
s3, the main CPLD acquires the information of the shared device and returns the information of the shared device from the CPU along the original path;
s4, after receiving the request of the main CPU for obtaining the shared device information, the main BMC forwards the request for obtaining the shared device information to the main CPLD;
and S5, the main CPLD acquires the information of the shared device and returns the information of the shared device to the main CPU along the original path.
6. The CPLD-based storage dual-control synchronization method of claim 5, wherein in step S3, the master CPLD acquires shared device information, sends the shared device information to the slave CPLD, the slave CPLD sends the shared device information to the slave BMC, and the slave BMC returns the shared device information to the slave CPU;
in step S5, the main CPLD obtains the shared device information, and sends the shared device information to the main BMC, and the main BMC returns the shared device information to the main CPU.
7. A terminal, comprising:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is configured to retrieve from the memory and execute the computer program, so that the terminal performs the method of any of the preceding claims 5-6.
8. A computer storage medium having stored thereon instructions which, when executed on a computer, cause the computer to perform the method of any of claims 5-6.
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