CN217157283U - Double-circuit server self-adaptive circuit and electronic equipment - Google Patents

Abstract

The application discloses two-way server self-adaptation circuit and electronic equipment, wherein, this two-way server self-adaptation circuit includes: the first processor and the second processor are connected; the first gating circuit is connected with the first processor; the second gating circuit is connected with the second processor; the control circuit is connected with the first gating circuit and the second gating circuit; the control circuit sends control signals to the first gating circuit or/and the second gating circuit to start or stop the first processor or/and the second processor. Through the mode, the function configuration of the first processor and the second processor in the self-adaptive circuit of the two-way server is more flexible, the first processor or/and the second processor can be started or stopped independently, and more effective and more sufficient use of the two-way server is guaranteed.

Description

Double-circuit server self-adaptive circuit and electronic equipment

Technical Field

The application relates to the technical field of servers, in particular to a double-path server self-adaptive circuit and electronic equipment.

Background

Currently, a Central Processing Unit (CPU) on a main board of a mainstream two-way server is designed primarily and secondarily and is compatible with a single two-way CPU configuration. And the main CPU is required to be started, but the secondary CPU cannot be normally started, so that the defects are as follows:

when a single-path CPU is configured, the function on the secondary CPU cannot be used, and the single-path complete machine function configuration lacks flexibility; when the main CPU module has a problem, the secondary CPU cannot work normally, and the whole machine cannot work normally.

SUMMERY OF THE UTILITY MODEL

The application provides a double-circuit server self-adaptation circuit and electronic equipment, this double-circuit server self-adaptation circuit can solve the double-circuit server among the prior art single-circuit complete machine function configuration and lack the flexibility, and the unable problem of running CPU alone of double-circuit CPU configuration.

In order to solve the technical problem, the application adopts a technical scheme that: there is provided a two-way server adaptive circuit, wherein the two-way server adaptive circuit includes: the first processor and the second processor are connected; the first gating circuit is connected with the first processor; the second gating circuit is connected with the second processor; the control circuit is connected with the first gating circuit and the second gating circuit; the control circuit sends control signals to the first gating circuit or/and the second gating circuit to start or stop the first processor or/and the second processor.

The control circuit sends a first control signal to the first gating circuit, so that the first gating circuit selects to correspondingly output a high-level signal or a low-level signal to the first processor under the action of the first control signal, and the first processor is started or stopped; and/or the control circuit sends a second control signal to the second gating circuit, so that the second gating circuit selects to correspondingly output a high-level signal or a low-level signal to the second processor under the action of the second control signal, and the second processor is started or stopped.

The two-way server self-adaptive circuit further comprises a power supply circuit, and the power supply circuit is connected with the first gating circuit and the second gating circuit to respectively provide high-level signals and low-level signals for the first gating circuit and the second gating circuit.

The first gating circuit comprises a first controlled end, a first power end, a first grounding end and a first signal output end, the first controlled end is connected with the control circuit, the first power end is connected with the power output end of the power circuit, the first grounding end is grounded, the first signal output end is connected with the first processor, and the first signal output end is selectively communicated with the first power end or the first grounding end; the second gating circuit comprises a second controlled end, a second power end, a second grounding end and a second signal output end, the second controlled end is connected with the control circuit, the second power end is connected with the power output end of the power circuit, the second grounding end is grounded, the second signal output end is connected with the second processor, and the second signal output end is selectively communicated with the second power end or the second grounding end.

The two-way server self-adaptive circuit further comprises a PCIE switching chip, wherein the PCIE switching chip is connected with the first processor and the second processor, so that when the first processor is started, the PCIE switching chip sets a port which is connected with the first processor as an uplink port, and sets a port which is connected with the second processor as a non-transparent bridge port; and when the second processor is started, the port of the PCIE switch chip, which is connected to the second processor, is set as an uplink port, and the port of the PCIE switch chip, which is connected to the first processor, is set as a non-transparent bridge port.

The two-way server self-adaptive circuit further comprises a basic input and output system flash memory and a first switch circuit which are connected, the first switch circuit is connected with the first processor, the second processor and the control circuit, a system operation program is stored in the basic input and output system flash memory, and the first switch circuit receives a third control signal sent by the control circuit so that the basic input and output system flash memory is selectively communicated with the first processor and/or the second processor based on the third control signal.

The dual-path server self-adaptive circuit further comprises an interface circuit, the interface circuit is connected with the control circuit and external electronic equipment, and the interface circuit is selectively communicated with the first processor or the second processor through the control circuit.

The two-way server self-adaptive circuit further comprises a second change-over switch circuit, the second change-over switch circuit is connected with the control circuit, the interface circuit, the first processor and the second processor, and the second change-over switch circuit receives a fourth control signal sent by the control circuit so that the interface circuit can be selectively communicated with the first processor or the second processor based on the fourth control signal.

The dual-path server self-adaptive circuit further comprises a first memory and a second memory, the first memory is connected with the first processor, the second memory is connected with the second processor, and the storage space of the first memory is smaller than that of the second memory.

In order to solve the above technical problem, the present application adopts another technical solution: there is provided an electronic device, wherein the electronic device comprises a chassis housing and a two-way server adaptive circuit mounted within the chassis housing, the two-way server adaptive circuit being a two-way server adaptive circuit as described in any of the above.

The beneficial effect of this application is: different from the prior art, the two-way server self-adaptive circuit in the application comprises: the first processor, the second processor, the first gating circuit, the second gating circuit and the control circuit are connected; the control circuit can send control signals to the first gating circuit or/and the second gating circuit to selectively and independently start or stop the first processor or/and the second processor, so that the problem that the whole two-way server cannot be started when the main processor cannot be started is solved, and the two-way server can be effectively and fully used. And because the first processor and the second processor are connected with each other, namely when the single-path is configured, the two processors can be reasonably used through signal interaction, the configuration of one server can be highlighted by the computing capacity in the design stage, and the configuration of the other server is highlighted by the storage capacity to meet the requirements of different use occasions, so that more flexible attribute configuration can be carried out.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

FIG. 1 is a schematic structural diagram of a first embodiment of a two-way server adaptive circuit according to the present application;

FIG. 2 is a schematic structural diagram of a second embodiment of a two-way server adaptive circuit according to the present application;

FIG. 3 is a schematic diagram of a third embodiment of a two-way server adaptive circuit according to the present application;

FIG. 4 is a schematic structural diagram of a fourth embodiment of the adaptive circuit of the two-way server according to the present application;

FIG. 5 is a schematic structural diagram of a fifth embodiment of a two-way server adaptive circuit according to the present application;

FIG. 6 is a schematic structural diagram of a sixth embodiment of a two-way server adaptive circuit according to the present application;

FIG. 7 is a schematic structural diagram of a seventh embodiment of a two-way server adaptive circuit according to the present application;

fig. 8 is a schematic structural diagram of an embodiment of an electronic device according to the present application.

Detailed Description

In order to make the technical problems solved, the technical solutions adopted, and the technical effects achieved by the present application clearer, the technical solutions of the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a two-way server adaptive circuit according to a first embodiment of the present application. In the present embodiment, the two-way server adaptation circuit 10 includes: a first processor 14, a second processor 15, a first gating circuit 12, a second gating circuit 13, and a control circuit 11.

For example, the two-way server adaptive circuit 10 may selectively start the first processor 14, the second processor 15, or both the first processor 14 and the second processor 15 according to a preset policy, so as to enable more effective and sufficient use of the two-way server. Of course, in other embodiments, the two-way server adaptive circuit 10 may also be used in any other electronic device that reasonably includes a two-way control center or a two-way driving motor and needs to be selectively started and stopped, and this embodiment does not limit this.

Specifically, the Control circuit 11 may include any reasonable program processing Unit such as an MCU (Micro Control Unit) circuit, a single chip microcomputer or a processor, and may be specifically understood as a single-channel and dual-channel adaptive management circuit, so as to be able to pass through pre-loaded program data or receive a set Control instruction sent by an upper computer, that is, any reasonable intelligent terminal communicatively connected to the Control circuit 11, for example, a background computer or a background server, to generate a corresponding Control signal, and complete selective start and stop of the first processor 14 and the second processor 15 based on the Control signal.

The first processor 14 and the second processor 15 may be specifically understood as two physical CPUs on a corresponding two-way server motherboard, so as to be capable of performing independent program processing functions such as data operation and data storage, and the two are connected to each other, so that when one of the two is started to run, the other can be called to perform function assistance.

Further, the first gating circuit 12 is connected to the first processor 14 and the control circuit 11 to receive the control signal sent by the control circuit 11 and to enable or disable the first processor 14 based on the control signal. The second gating circuit 13 is connected to the second processor 15 and the control circuit 11, and can receive a control signal transmitted from the control circuit 11 and start or stop the second processor 15 based on the control signal.

In the above scheme, the control circuit 11 sends the control signal to the first gating circuit 12 or/and the second gating circuit 13 to selectively and independently start or stop the first processor 14 or/and the second processor 15, so that the problem that the whole two-way server cannot be started when the main processor cannot be started is solved, that is, the two-way server can be more effectively and fully used. And because the first processor 14 and the second processor 15 are connected with each other, that is, when the two processors are configured in a single-path mode, the two processors can be reasonably used through signal interaction, the configuration of one server can be highlighted by the computing capacity in the design stage, and the configuration of the other server is highlighted by the storage capacity to meet the requirements of different use occasions, so that more flexible attribute configuration can be performed, that is, under the condition that the configuration cost is not much, the market multiple positioning requirements can be met, and the research and development cost of the two-path server can be effectively reduced.

In an embodiment, the control circuit 11 specifically sends the first control signal to the first gating circuit 12, so that the first gating circuit 12 selects to output a high level signal or a low level signal to the first processor 14 correspondingly under the action of the first control signal, for example, in response to a state of the first control signal according to a preset strategy, a pin of the first gating circuit 12, which is connected to the first processor 14 correspondingly, outputs a high level signal or a low level signal to start or stop the first processor 14.

The control circuit 11 may specifically set that the first gating circuit 12 starts the first processor 14 when outputting a high level signal to the first processor 14, and stops the first processor 14 when outputting a low level signal to the first processor 14; alternatively, the first gating circuit 12 may start the first processor 14 when outputting a low level signal to the first processor 14, and stop the first processor 14 when outputting a high level signal to the first processor 14, which is not limited in this application.

Further, the control circuit 11 specifically sends a second control signal to the second gating circuit 13, so that the second gating circuit 13 selects to output a high level signal or a low level signal to the second processor 15 correspondingly under the action of the second control signal, for example, in response to the state of the second control signal according to a preset strategy, a pin of the second gating circuit 13, which is correspondingly connected to the second processor 15, outputs a high level signal or a low level signal to start or stop the second processor 15.

The control circuit 11 may specifically set that the second gating circuit 13 starts the second processor 15 when outputting a high level signal to the second processor 15, and stops the second processor 15 when outputting a low level signal to the second processor 15; or, when the second gating circuit 13 outputs a low level signal to the second processor 15, the second processor 15 is started, and when the second gating circuit outputs a high level signal to the second processor 15, the second processor 15 is stopped, which is not limited in this application.

In an alternative embodiment, the signal connection end of the first gating circuit 12 connected to the first processor 14 may further include a plurality of high level signals and/or low level signals, which are correspondingly sent to the first processor 14 based on the first control signal, and only when the high level signals and/or low level signals, which are correspondingly output to the first processor 14, satisfy a specific number ratio and arrangement order, for example, taking the setting order of the signal pins of the first processor 14 connected to the first gating circuit 12 as an example, when the level signals, which are correspondingly output to the signal pins having the setting order, of the first gating circuit 12 are sequentially high level signals 2, low level signals 3, high level signals 1, low level signals 2 or any other reasonable arrangement combination of high level signals and low level signals (which is not listed here), the first processor 14 may be started, otherwise the first processor 14 remains shut down at all times.

Similarly, the signal connection end of the second gating circuit 13 connected to the second processor 15 may also include a plurality of signal connection ends, and the high level signal and/or the low level signal that is correspondingly sent to the second processor 15 based on the second control signal also includes a plurality of signal connection ends, and the second processor 15 may be started only when the high level signal and the low level signal that are correspondingly output to the second processor 15 satisfy a specific number ratio and an arrangement order, otherwise, the second processor 15 is always kept off.

Optionally, the voltage level of the high-level signal is any reasonable voltage value such as 2V, 3.3V, or 5V, and the voltage level of the low-level signal is any reasonable voltage value such as 1V, 0V, or-2V, which is not limited in this application.

In an embodiment, the two-way server adaptive circuit 10 further includes a PCIE (peripheral component interconnect express) switch chip (not shown in the drawing), for example, an NT (non-transparent) bridge chip or any other PCIE switch chip of any reasonable type, where the PCIE switch chip is connected to the first processor 14 and the second processor 15, so that when the first processor 14 is started, the PCIE switch chip sets a port of the PCIE switch chip, which is connected to the first processor 14, as an uplink port, and sets a port of the PCIE switch chip, which is connected to the second processor 15, as a non-transparent bridge port; when the second processor 15 is started, the port of the PCIE switch chip that is connected to the second processor 15 is set as an uplink port, and the port that is connected to the first processor 14 is set as a non-transparent bridge port.

It should be noted that the PCIE switch chip is mainly used to interconnect 2 CPUs, only the master CPU recognizes and takes over the chip by default, and the slave CPU takes over the chip when the master CPU fails.

Furthermore, the dual-channel server adaptive circuit further includes an HBA (Host bus adapter)/RAID (Redundant Arrays of Independent Disks) controller, an SAS (Serial Attached SCSI)/SATA (Serial Advanced Technology Attachment hard disk) expansion controller, and a hard disk, where the HBA/RAID controller is connected to the PCIE switch chip, the SAS/SATA expansion controller is connected to the HBA/RAID controller, and the hard disk is connected to the SAS/SATA expansion controller.

It should be noted that the host bus adapter is a network and switch, and is a board that can be inserted into a computer or a mainframe. The disk array has the meaning of an array with redundancy capability formed by independent disks. The disk array is a disk group with huge capacity composed of a plurality of independent disks, and the performance of the whole disk system is improved by the additive effect generated by providing data by individual disks. With this technique, data is divided into a plurality of sectors, each of which is stored on a respective hard disk.

It is understood that the NT bridge chip specifically includes NT PORTs (non-transparent bridge PORTs), Downstream PORTs (Downstream PORTs), and Upstream PORTs (Upstream PORTs), and the NT bridge chip can flexibly configure which PORTs are NT PORTs, Downstream PORTs, and Upstream PORTs. The working principle of the NT bridge in the double control mode is as follows: assuming that this time the server is powered on, starting from the first processor 14 with the second processor 15 as a standby, the PORT interconnecting the NT bridge chip and the first processor 14 will be set as an Upstream PORT, and the PORT interconnecting the second processor 15 as an NT PORT.

Wherein, for the first processor 14, the first processor 14 can recognize that all Downstream ports and NT ports of the NT chip are presented to NT virtual ports (non-transparent bridge virtual ports) of the first processor 14; for the second processor 15, the second processor 15 can only recognize the NT Link PORT (non-transparent bridge Link PORT) presented to the second processor 15 by the NT PORT, and once the first processor 14 goes wrong, the second processor 15 will take over the NT bridge chip, and then take over all downlink PORTs of the NT bridge chip, i.e. take over all downlink hard disk interfaces, thereby implementing the dual control function. It can be understood that the dual-control function is not limited to a hard disk, and all devices connected to the Downstream Port of the NT bridge can implement dual-control. Conversely, the case of booting from the second processor 15 with the first processor 14 as a spare is similar to the case of booting from the first processor 14, and will not be described again.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a two-way server adaptive circuit according to a second embodiment of the present application. In this embodiment, on the basis of the first embodiment of the two-way server adaptive circuit provided in this application, the two-way server adaptive circuit 20 further includes a power supply circuit 26.

It can be understood that, in order to satisfy the requirement that the first gating circuit 22 and the second gating circuit 23 can respectively send high-level signals or low-level signals to the first processor 24 and the second processor 25, the two-way server self-adapting circuit 20 also needs to respectively provide power supplies of the high-level signals and the low-level signals.

Specifically, the power circuit 26 is connected to the first gating circuit 22 and the second gating circuit 23 to be able to provide a high level signal and a low level signal to the first gating circuit 22 and the second gating circuit 23, for example, the first gating circuit 22 may specifically include two signal ends, one of the signal ends is connected to the high level output end of the power circuit 26, and the other end is connected to the low level output end of the power circuit 26 or ground.

In an embodiment, the power circuit 26 may be further specifically used as a power supply for the first processor 24, the second processor 25 and the control circuit 11, which is not limited in this application.

It is understood that, in the embodiment, the first processor 24, the second processor 25, the first gating circuit 22, the second gating circuit 23, and the control circuit 21 are respectively the same as the first processor 14, the second processor 15, the first gating circuit 12, the second gating circuit 13, and the control circuit 11, and specific reference is made to fig. 1 and related text, which are not repeated herein.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a third embodiment of a two-way server adaptive circuit according to the present application. This embodiment is based on the first embodiment of the two-way server adaptive circuit provided in this application, and the two-way server adaptive circuit 20 further includes a bios flash memory 38 and a first switch circuit 37 connected to each other.

It should be noted that the BIOS flash memory 38 is also a BIOS false (flash memory), wherein the BIOS is an abbreviation of Basic Input Output System, and the translated chinese name is "Basic Input Output System". It is a standard firmware interface in the industry for IBM PC (personal computer) compatible systems. The BIOS is the first software loaded at startup of the personal computer.

In fact, it is a set of programs solidified on a ROM chip on the main board of the computer, it stores the most important basic input and output programs of the computer, the self-checking program after power-on and the system self-starting program, it can read and write the specific information of the system setting from the CMOS (chip storing the basic starting information of the computer, such as date, time, starting setting, etc.). Its primary function is to provide the lowest level, most direct hardware setup and control for the computer. In addition, the BIOS provides some system parameters to the operating system. The change of system hardware is hidden by BIOS, and programs use BIOS functions rather than directly control the hardware. Modern operating systems ignore the abstraction layer provided by the BIOS and directly control the hardware components.

It will be appreciated that the first processor 34 and the second processor 35 can only be effectively started up and run when connected to the bios flash memory 38 to perform corresponding data operations and data storage functions.

Specifically, the first switch circuit 37 is connected to the bios flash memory 38, the first processor 34, the second processor 35 and the control circuit 31, the bios flash memory 38 stores a system running program, and the first switch circuit 37 can receive a third control signal sent by the control circuit 31, so as to enable the bios flash memory 38 to selectively connect the first processor 34 and/or the second processor 35 based on the third control signal, for example, by selectively connecting two terminals connected to the first processor 34 and the bios flash memory 38 inside thereof, respectively, so as to connect the bios flash memory 38 to the first processor 34, and disconnecting or disconnecting the two terminals when the second processor 35 needs to be switched or synchronously started, and connecting two terminals connected to the second processor 35 and the bios flash memory 38 inside thereof, respectively, thereby enabling the first processor 34 and/or the second processor 35, which are correspondingly connected to the bios flash memory 38, to start running.

It is understood that, in the embodiment, the first processor 34, the second processor 35, the first gating circuit 32, the second gating circuit 33, and the control circuit 31 are respectively the same as the first processor 14, the second processor 15, the first gating circuit 12, the second gating circuit 13, and the control circuit 11, and specific reference is made to fig. 1 and related text, which are not repeated herein.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a dual-server adaptive circuit according to a fourth embodiment of the present application. In this embodiment, based on the first embodiment of the two-way server adaptive circuit provided in this application, the two-way server adaptive circuit 40 further includes an interface circuit 49.

It is understood that, in order to expand the functions of the two-way server and realize data communication with other electronic devices 2, the two-way server adaptation circuit 40 may further integrate the interface circuit 49, and in order to reduce the complexity of the hardware layout and the manufacturing cost as much as possible, the interface circuit 49 may be used as a common channel of the two-way server, and only one way is set, and the first processor 44 or the second processor 45 which is currently started to operate is selectively switched on.

Specifically, the interface circuit 49 connects the control circuit 41 and the external electronic device 2, and the interface circuit 49 can make a connection with the first processor 44 or the second processor 45 by means of channel selection of the control circuit 41 to thereby enable the first processor 44 or the second processor 45 to perform data communication with the external electronic device 2.

Optionally, the interface Circuit 49 may specifically include one or more of an ADC (analog-to-digital conversion) interface, an SPI (serial peripheral interface), an IIC (Inter-Integrated Circuit bus) interface, and any reasonable communication interface such as a UART (Universal Asynchronous Receiver/Transmitter) interface, which is not limited in this application.

Optionally, the external electronic device 2 connected to the interface circuit 49 may be one or more of any reasonable electronic device 2 such as a U (universal serial bus) disk, a mobile hard disk, a smart phone, an unmanned aerial vehicle, and an electronic camera, which is not limited in this application.

It is understood that, in the embodiment, the first processor 44, the second processor 45, the first gating circuit 42, the second gating circuit 43, and the control circuit 41 are respectively the same as the first processor 14, the second processor 15, the first gating circuit 12, the second gating circuit 13, and the control circuit 11, and specific reference is made to fig. 1 and related text, which are not repeated herein.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a fifth embodiment of a two-way server adaptive circuit according to the present application. In this embodiment, on the basis of the fourth embodiment of the two-way server adaptive circuit provided in the present application, the two-way server adaptive circuit 50 further includes a second switch circuit 510.

Specifically, the second switch circuit 510 is connected to the control circuit 51, the interface circuit 59, the first processor 54, and the second processor 55, and the second switch circuit 510 can receive a fourth control signal sent by the control circuit 51, so that the interface circuit 59 can selectively communicate with the first processor 54 or the second processor 55 based on the fourth control signal, for example, two terminals inside thereof, which are respectively connected to the first processor 54 and the interface circuit 59, are selectively turned on based on the fourth control signal, so that the interface circuit 59 is connected to the first processor 54, and when it is required to switch to the second processor 55, the two terminals are turned off, so that two terminals inside thereof, which are respectively connected to the second processor 55 and the interface circuit 59, are turned on, so that the interface circuit 59 can be connected to the second processor 55.

It is to be understood that, in the present embodiment, the first processor 54, the second processor 55, the first gating circuit 52, the second gating circuit 53, the control circuit 51, and the interface circuit 49 are respectively the same as the first processor 44, the second processor 45, the first gating circuit 42, the second gating circuit 43, the control circuit 41, and the interface circuit 49, and specific reference is made to fig. 4 and related text, which are not repeated herein.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a sixth embodiment of a two-way server adaptive circuit according to the present application. In this embodiment, on the basis of the first embodiment of the two-way server adaptive circuit provided in the present application, the two-way server adaptive circuit 60 further includes a first memory 611 and a second memory 612.

Specifically, to implement the functions of data processing and data storage, the two-way server adaptive circuit 60 further includes a first memory 611 and a second memory 612, and the first memory 611 and the second memory 612 are respectively connected to the first processor 64 and the second processor 65, so as to be used as memory spaces for program operation and data storage of the first processor 64 and the second processor 65, respectively.

The storage space of the first memory 611 is smaller than that of the second memory 612.

It can be understood that, since the first processor 64 and the second processor 65 can independently and individually start operation or synchronously start operation, and are connected to each other and can be invoked with each other, in order to meet the market relocation requirement and optimize the overall performance of the two-way server, the first processor 64 and the second processor 65 can respectively highlight different performances and perform different configurations, for example, the first processor 64 can be designed to be configured with a main computing capability according to the market requirement, such as highlighting the expansion capability of PCIE (high speed serial computer expansion bus standard), and the second processor 65 can be designed to be configured with a main storage capability according to the market requirement, such as highlighting the expansion capability of SAS hard disk/SATA hard disk. In other embodiments, the first processor 64 and the second processor 65 may also focus on any reasonable performance, which is not limited in this application.

It is understood that, in the embodiment, the first processor 44, the second processor 45, the first gating circuit 42, the second gating circuit 43, and the control circuit 41 are respectively the same as the first processor 14, the second processor 15, the first gating circuit 12, the second gating circuit 13, and the control circuit 11, and specific reference is made to fig. 1 and related text, which are not repeated herein.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a seventh embodiment of a two-way server adaptive circuit according to the present application.

In the present embodiment, the two-way server adaptation circuit 70 specifically includes a first processor 74, a second processor 75, a first gating circuit 72, a second gating circuit 73, a control circuit 71, and a power supply circuit (not shown).

The first gating circuit 72 further includes a first controlled terminal S1, a first power terminal DN1, a first ground terminal DN2 and a first signal output terminal OUT1, the first controlled terminal S1 is connected to the control circuit 71, the first power terminal DN1 is connected to the power output terminal of the power circuit, the first ground terminal DN2 is grounded, the first signal output terminal OUT1 is connected to the first processor 74, and the first signal output terminal OUT1 is selectively connected to the first power terminal DN1 or the first ground terminal DN2, so that the first signal output terminal OUT1 can correspondingly output a high-level signal or a low-level signal to the first processor 74.

The second gating circuit 73 includes a second controlled terminal S2, a second power terminal DN3, a second ground terminal DN4 and a second signal output terminal OUT2, the second controlled terminal S2 is connected to the control circuit 71, the second power terminal DN3 is connected to the power output terminal of the power circuit, the second ground terminal DN4 is grounded, the second signal output terminal OUT2 is connected to the second processor 75, and the second signal output terminal OUT2 is selectively connected to the second power terminal DN3 or the second ground terminal DN4, so that the second signal output terminal OUT2 can correspondingly output a high-level signal or a low-level signal to the second processor 75.

In an embodiment, the first processor 74 further includes a plurality of first multiplexing pins, for example, STARP11 to STARP1n (n is an integer not less than 1), and the first gating circuit 72 includes a plurality of first gating sub-circuits, for example, first gating sub-circuit 1 to first gating sub-circuit n, each first gating sub-circuit is connected to a corresponding first multiplexing pin, for example, STARP11 to STARP1n are connected to the corresponding first gating sub-circuits 1 to first gating sub-circuit n, and each first gating sub-circuit selectively outputs a high level signal or a low level signal to the first processor 74, and the first processor 74 may start the operation only when the level states of the plurality of level signals received by the plurality of first multiplexing pins satisfy a first preset condition.

For example, the first preset condition may be satisfied when the plurality of level signals correspondingly output by the first gating sub-circuit 1 to the first gating sub-circuit n sequentially include 2 high level signals, 3 low level signals, 1 high level signal, and 2 low level signals, and when the control circuit 71 correspondingly enables the plurality of level signals output by the plurality of first gating sub-circuits to the first multiplexing pin to meet the characteristic, the first processor 74 is started, otherwise, the first processor 74 is always kept off.

In other embodiments, the first preset condition may also be any other reasonable arrangement combination of high and low level signals, which is not limited in this application and is not listed here.

Likewise, the second processor 75 further includes a plurality of second multiplexing pins, for example, STARP21 to STARP2n, and the second gating circuit 73 includes a plurality of second gating sub-circuits, for example, second gating sub-circuit 1 to second gating sub-circuit n, and each second gating sub-circuit is connected to a corresponding second multiplexing pin, for example, STARP21 to STARP2n are respectively connected to the second gating sub-circuits 1 to second gating sub-circuit n in a one-to-one correspondence, and each second gating sub-circuit selectively outputs a high level signal or a low level signal to the second processor 75, and the second processor 75 can start operation when the level states of the plurality of level signals received by the plurality of second multiplexing pins satisfy a second preset condition.

It is to be understood that the second preset condition may be the same as the first preset condition, or may be different from the first preset condition, which is not limited in this application and is not listed here.

Further, in an embodiment, the two-way server adaptation circuit 70 further includes a bios flash memory 77 and a two-way switch 76, wherein the two-way switch 76 connects the bios flash memory 77, the first processor 74, the second processor 75 and the control circuit 71, the bios flash memory 77 stores a system running program, and the two-way switch 76 can receive a control signal sent by the control circuit 71 to selectively connect the bios flash memory 77 to the first processor 74 and/or the second processor 75 based on the control signal.

In an embodiment, the first processor 74 further includes at least two memory controllers (not shown), a PCIE controller (not shown), and a SATA controller (not shown), and the at least two memory controllers, the PCIE controller, and the SATA controller are respectively and correspondingly connected to the at least two memory banks, the PCIE device, and the SATA device, so as to assist the first processor 74 to perform data operation and data storage, or perform function expansion thereof.

Further, the second processor 75 further includes at least two memory controllers (not shown), a PCIE controller (not shown), and an SATA controller (not shown), and the at least two memory controllers, the PCIE controller, and the SATA controller are respectively and correspondingly connected to the at least two memory banks, the PCIE device, and the SATA device, so as to assist the second processor 75 in performing data operation and data storage, or performing function expansion on the second processor.

Further, the two-way server adaptive circuit 70 further includes a PCIE switch chip 78, that is, an NT bridge chip, where the PCIE switch chip 78 is connected to the first processor 74 and the second processor 75, so that when the first processor 74 is started, the PCIE switch chip 78 sets a port of the PCIE switch chip, which is connected to the first processor 74, as an uplink port, and sets a port of the PCIE switch chip, which is connected to the second processor 75, as a non-transparent bridge port; when the second processor 75 is started, the port of the PCIE switch chip 78 that is connected to the second processor is set as an uplink port, and the port that is connected to the first processor 74 is set as a non-transparent bridge port.

Further, the two-way server adaptation circuit 70 further includes an HBA/RAID controller 79, an SAS/SATA expansion controller 710, and a hard disk 711, where the HBA/RAID controller 79 is connected to the PCIE switch chip 78, the SAS/SATA expansion controller 710 is connected to the HBA/RAID controller 79, and the hard disk 711 is connected to the SAS/SATA expansion controller 710.

It can be understood that the PCIE switch chip 78 specifically includes NT PORTs, downlink PORTs, and Upstream PORTs, and the PCIE switch chip 78 can flexibly configure which Port is an NT Port, a downlink Port, or an Upstream Port. The working principle of the NT bridge in the duel control mode is as follows: assuming that the server is powered on, started from the first processor 74 and the second processor 75 is in standby, the PORT interconnecting the PCIE switch chip 78 and the first processor 74 will be set as an Upstream PORT, and the PORT interconnecting the second processor 75 will be an NT PORT.

For the first processor 74, the first processor 74 can recognize that all downlink ports and NT ports of the PCIE switch chip 78 are presented to NT virtual ports (non-transparent bridge virtual ports) of the first processor 74; for the second processor 75, the second processor 75 can only recognize the NT Link PORT (non-transparent bridge Link PORT) presented to the second processor 75 by the NT PORT, and once the first processor 74 goes wrong, the second processor 75 will take over the PCIE switch chip 78, and then take over all downlink PORTs of the PCIE switch chip 78, that is, take over all interfaces of the downlink hard disk 711, thereby implementing the dual control function. It can be understood that the dual-control function is not limited to the hard disk 711, and all devices connected to the NT bridge downlink Port can implement dual-control. Conversely, the case of booting from the second processor 75 with the first processor 74 as a spare is similar to the case of booting from the first processor 74, and will not be described again.

Fig. 8 shows a schematic structural diagram of an embodiment of the electronic device in this application, where fig. 8 is a schematic structural diagram.

In this embodiment, the electronic device 81 includes a chassis housing 811 and a two-way server adaptive circuit 812 installed in the chassis housing 811, where the two-way server adaptive circuit 812 is any one of the two-way server adaptive circuit 10 to the two-way server adaptive circuit 70 described above, and please refer to fig. 1-7 and related text, which are not repeated herein.

It is understood that the housing shell 811 may be a mounting housing shell 811 for the two-way server adaptive circuit 812, and the two-way server adaptive circuit 812 is disposed inside the housing shell 811, so that the two-way server adaptive circuit 812 can be protected by the housing shell 811.

Different from the prior art, the two-way server self-adaptive circuit in the application comprises: the first processor and the second processor, the first gating circuit, the second gating circuit and the control circuit are connected; the control circuit can send control signals to the first gating circuit or/and the second gating circuit to selectively and independently start or stop the first processor or/and the second processor, so that the problem that the whole two-way server cannot be started when the main processor cannot be started is solved, and the two-way server can be effectively and fully used. And because the first processor and the second processor are connected with each other, namely when the single-path is configured, the two processors can be reasonably used through signal interaction, the configuration of one server can be highlighted by the computing capacity in the design stage, and the configuration of the other server is highlighted by the storage capacity to meet the requirements of different use occasions, so that more flexible attribute configuration can be carried out.

The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.

Claims (10)

1. A two-way server adaptive circuit, comprising:

the system comprises a first processor and a second processor which are connected;

the first gating circuit is connected with the first processor;

the second gating circuit is connected with the second processor;

a control circuit connected with the first gating circuit and the second gating circuit; the control circuit sends control signals to the first gating circuit or/and the second gating circuit to start or stop the first processor or/and the second processor.

2. The two-way server adaptation circuit according to claim 1,

the control circuit sends a first control signal to the first gating circuit, so that the first gating circuit selects to correspondingly output a high-level signal or a low-level signal to the first processor under the action of the first control signal, and the first processor is started or stopped; and/or the presence of a gas in the gas,

the control circuit sends a second control signal to the second gating circuit, so that the second gating circuit selects to correspondingly output the high-level signal or the low-level signal to the second processor under the action of the second control signal, and the second processor is started or stopped.

3. The two-way server adaptation circuit according to claim 2,

the two-way server self-adaptive circuit further comprises a power circuit, wherein the power circuit is connected with the first gating circuit and the second gating circuit to respectively provide the high-level signal and the low-level signal for the first gating circuit and the second gating circuit.

4. The two-way server adaptation circuit according to claim 3,

the first gating circuit comprises a first controlled end, a first power end, a first grounding end and a first signal output end, wherein the first controlled end is connected with the control circuit, the first power end is connected with the power output end of the power circuit, the first grounding end is grounded, the first signal output end is connected with the first processor, and the first signal output end is selectively communicated with the first power end or the first grounding end;

the second gating circuit comprises a second controlled end, a second power end, a second grounding end and a second signal output end, the second controlled end is connected with the control circuit, the second power end is connected with the power output end of the power circuit, the second grounding end is grounded, the second signal output end is connected with the second processor, and the second signal output end is selectively communicated with the second power end or the second grounding end.

5. The two-way server adaptation circuit according to claim 1,

the self-adaptive circuit of the two-way server further comprises a PCIE switching chip, wherein the PCIE switching chip is connected with the first processor and the second processor, so that when the first processor is started, the PCIE switching chip sets a port which is connected with the first processor as an uplink port, and sets a port which is connected with the second processor as a non-transparent bridge port; and when the second processor is started, the port of the PCIE switch chip, which is connected to the second processor, is set as an uplink port, and the port of the PCIE switch chip, which is connected to the first processor, is set as a non-transparent bridge port.

6. The two-way server adaptation circuit according to claim 1,

the two-way server self-adaptive circuit further comprises a basic input and output system flash memory and a first switch circuit which are connected, the first switch circuit is connected with the first processor, the second processor and the control circuit, a system operation program is stored in the basic input and output system flash memory, and the first switch circuit receives a third control signal sent by the control circuit so as to enable the basic input and output system flash memory to be selectively communicated with the first processor and/or the second processor based on the third control signal.

7. The two-way server adaptation circuit according to claim 1,

the dual-path server self-adaptive circuit further comprises an interface circuit, the interface circuit is connected with the control circuit and external electronic equipment, and the interface circuit is selectively communicated with the first processor or the second processor through the control circuit.

8. The two-way server adaptation circuit according to claim 7,

the two-way server self-adaptive circuit further comprises a second selector switch circuit, the second selector switch circuit is connected with the control circuit, the interface circuit, the first processor and the second processor, and the second selector switch circuit receives a fourth control signal sent by the control circuit so as to enable the interface circuit to be selectively communicated with the first processor or the second processor based on the fourth control signal.

9. The two-way server adaptation circuit according to any one of claims 1-8,

the dual-path server self-adaptive circuit further comprises a first memory and a second memory, the first memory is connected with the first processor, the second memory is connected with the second processor, and the storage space of the first memory is smaller than that of the second memory.

10. An electronic device comprising a chassis housing and a two-way server adaptive circuit mounted within the chassis housing, the two-way server adaptive circuit being as in any one of claims 1-9.

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