CN216671641U - Gallium nitride normally-off device with mixed gate electrode structure - Google Patents

Gallium nitride normally-off device with mixed gate electrode structure Download PDF

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CN216671641U
CN216671641U CN202121958168.5U CN202121958168U CN216671641U CN 216671641 U CN216671641 U CN 216671641U CN 202121958168 U CN202121958168 U CN 202121958168U CN 216671641 U CN216671641 U CN 216671641U
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gate electrode
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gan cap
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蒲涛飞
李柳暗
敖金平
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Ningbo Rhenium Micro Semiconductor Co ltd
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Ningbo Rhenium Micro Semiconductor Co ltd
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Abstract

The utility model discloses a gallium nitride normally-off device with a mixed gate electrode structure, which comprises: the buffer layer, the GaN channel layer, the AlGaN layer and the P-GaN cap layer are sequentially arranged on the substrate layer; two ohmic electrodes disposed on the AlGaN layer; the gate dielectric layers are arranged on the P-GaN cap layer and on two sides of the P-GaN cap layer; the passivation layer is arranged on the AlGaN layer between the ohmic electrode and the gate dielectric layers on two sides of the P-GaN cap layer; the gate electrode is arranged on the gate dielectric layer and fills the groove of the gate dielectric layer; the gate electrode on the gate dielectric layer on the P-GaN cap layer and the gate electrodes filled in the grooves form a mixed gate structure of an MIS gate electrode structure and a Schottky gate electrode structure; and the gate electrodes on the gate dielectric layers on the two sides of the P-GaN cap layer and the gate dielectric layers on the two sides of the P-GaN cap layer form a field plate structure. The utility model improves the threshold voltage of the gate electrode of the device, improves the switching frequency of the device and simultaneously improves the long-term reliability of the gate electrode of the device.

Description

Gallium nitride normally-off device with mixed gate electrode structure
Technical Field
The utility model belongs to the technical field of semiconductor power devices, and particularly relates to a gallium nitride normally-off device with a mixed gate electrode structure.
Background
Wide bandgap semiconductor materials, represented by gallium nitride (GaN), have a higher critical breakdown electric field, can realize a lower capacitance and on-resistance at the same breakdown voltage, and are known as next-generation power device materials. Therefore, the development of gallium nitride (GaN) power devices to replace traditional silicon (Si) -based devices is a key means for improving the utilization efficiency of electric energy and further relieving the energy crisis, and is expected to play a significant role in emerging markets. As a representative gallium nitride (GaN) device, a High Electron Mobility Transistor (HEMT) based on an AlGaN/GaN epitaxial structure has received much attention due to its unique High-mobility Two-dimensional Electron Gas (2 DEG) and exhibits excellent performance in terms of High power, High frequency, and the like.
The conventional AlGaN/GaN High Electron Mobility Transistor (HEMT) is a normally-on device, and an additional gate voltage needs to be loaded to cut off a channel in actual operation, so that the conventional AlGaN/GaN High Electron Mobility Transistor (HEMT) causes more complicated circuit design and unnecessary power consumption, and has a greater safety risk. In view of the practical operational deficiencies of normally-on devices, normally-off AlGaN/GaN High Electron Mobility Transistors (HEMTs) are becoming the direction of development. Currently, the implementation of normally-off devices using P-GaN cap layers is one of the most mature approaches and is successfully commercialized. The gate electrode structure of the normally-off device can be further subdivided into an ohmic gate electrode, a schottky gate electrode and a Metal-dielectric-Semiconductor (MIS) gate electrode by being different from a P-GaN contact type.
However, the threshold voltage of the gate electrode of the High Electron Mobility Transistor (HEMT) with the P-GaN cap layer is maintained at about 2V at present, and the requirement on the threshold voltage of the gate electrode in practical operation cannot be met.
SUMMERY OF THE UTILITY MODEL
To solve the above problems in the prior art, the present invention provides a gan normally-off device having a hybrid gate electrode structure. The technical problem to be solved by the utility model is realized by the following technical scheme:
the embodiment of the utility model provides a gallium nitride normally-off device with a mixed gate electrode structure, which comprises: a substrate layer; the buffer layer, the GaN channel layer, the AlGaN layer and the P-GaN cap layer are sequentially arranged on the substrate layer;
two ohmic electrodes disposed on the AlGaN layer; the two ohmic electrodes are respectively arranged at two ends of the upper surface of the AlGaN layer, and the P-GaN cap layer is arranged between the two ohmic electrodes;
the gate dielectric layers are arranged on the P-GaN cap layer and on two sides of the P-GaN cap layer; a plurality of grooves distributed at intervals are arranged on the gate dielectric layer on the P-GaN cap layer, and each groove penetrates through the gate dielectric layer to reach the upper surface of the P-GaN cap layer;
the passivation layer is arranged on the AlGaN layer and is positioned between the ohmic electrode and the gate dielectric layers on two sides of the P-GaN cap layer;
the gate electrode is arranged on the gate dielectric layer and filled in the grooves; the gate electrode on the gate dielectric layer on the P-GaN cap layer and the gate electrodes filled in the grooves form a mixed gate electrode structure of an MIS gate structure and a Schottky gate structure, and the gate electrodes on the gate dielectric layers on two sides of the P-GaN cap layer and the gate dielectric layers on two sides of the P-GaN cap layer form a field plate structure.
In one embodiment of the utility model, the thickness of the P-GaN cap layer is 50 nm-150 nm, and the doping concentration is 1.0 multiplied by 1017cm-3～1.0×1021cm-3。
In one embodiment of the utility model, the thickness of the gate dielectric layer on the P-GaN cap layer is 5nm to 100 nm.
In one embodiment of the present invention, each of the grooves has a width of 1 μm to 10 μm, and an interval between adjacent grooves is 1 μm to 10 μm.
In one embodiment of the utility model, the thickness of the gate dielectric layers on two sides of the P-GaN cap layer in the vertical direction is 55nm to 250 nm.
In one embodiment of the present invention, the thickness of the passivation layer is 5nm to 1000 nm.
In one embodiment of the present invention, further comprising:
and a Pad electrode disposed on the gate electrode and the ohmic electrode.
The utility model has the beneficial effects that:
according to the gallium nitride normally-off device with the mixed gate electrode structure, on the basis of a conventional P-GaN/AlGaN/GaN epitaxial structure, the gate electrode adopts a gate electrode structure formed by mixing an MIS gate electrode structure and a Schottky gate electrode structure, the threshold voltage of the gate electrode of the device is improved by utilizing the MIS gate electrode structure, and the threshold voltage of the gate electrode of the device in actual operation can reach 3V by combining the characteristics of high capacitance and high transconductance of the Schottky gate electrode structure; meanwhile, the high carrier mobility of the two-dimensional electron gas channel is utilized, the switching frequency of the normally-closed MIS gate electrode structure device is further improved under the condition that the high threshold voltage of the gate electrode of the device is maintained, meanwhile, the two ends of the gate electrode and the gate dielectric layer form a field plate structure, and the long-term reliability of the gate electrode of the device is improved.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a gan normally-off device with a hybrid gate electrode structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another GaN normally-off device with a hybrid gate electrode structure according to an embodiment of the utility model;
fig. 3 is a schematic flow chart illustrating a process for fabricating a gan normally-off device with a hybrid gate electrode structure according to an embodiment of the present invention;
FIGS. 4a to 4i are schematic diagrams illustrating the fabrication of a GaN normally-off device with a hybrid gate electrode structure according to an embodiment of the utility model;
fig. 5 is a schematic flow chart of another process for fabricating a gan normally-off device with a hybrid gate electrode structure according to an embodiment of the present invention.
Description of reference numerals:
1-a substrate layer; 2-a buffer layer; 3-a GaN channel layer; a 4-AlGaN layer; a 5-P-GaN cap layer; 6-a gate dielectric layer; 7-a passivation layer; an 8-ohmic electrode; 9-gate electrode.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
In order to increase the threshold voltage of the device, an embodiment of the present invention provides a gan normally-off device with a hybrid gate electrode structure, please refer to fig. 1, where fig. 1 is a schematic structural diagram of a gan normally-off device with a hybrid gate electrode structure according to an embodiment of the present invention, the device includes:
a substrate layer 1;
the buffer layer 2, the GaN channel layer 3 and the AlGaN layer 4 are sequentially arranged on the substrate layer 1;
a P-GaN cap layer 5 and two ohmic electrodes 8 arranged on the AlGaN layer 4; wherein, two ohmic electrodes 8 are respectively arranged at two ends of the upper surface of the AlGaN layer 4, and the P-GaN cap layer 5 is arranged between the two ohmic electrodes 8;
the gate dielectric layers 6 are arranged on the P-GaN cap layer 5 and on two sides of the P-GaN cap layer 5; a plurality of grooves distributed at intervals are arranged on the gate dielectric layer 6 on the P-GaN cap layer 5, and each groove penetrates through the gate dielectric layer 6 to the upper surface of the P-GaN cap layer 5;
the passivation layer 7 is arranged on the AlGaN layer, and the passivation layer 7 is positioned between the ohmic electrode and the gate dielectric layers 6 on two sides of the P-GaN cap layer 5;
the gate electrode is arranged on the gate dielectric layer 6 and filled in the grooves; the gate electrode on the gate dielectric layer 6 on the P-GaN cap layer 5 and the gate electrodes filled in the grooves form a mixed gate electrode structure of an MIS gate structure and a Schottky gate structure, and the gate electrodes on the gate dielectric layers 6 on two sides of the P-GaN cap layer 5 and the gate dielectric layers 6 on two sides of the P-GaN cap layer 5 form a field plate structure.
Specifically, in order to improve the threshold voltage of the gate electrode of the device, the embodiment of the utility model is based on a conventional normally-off MIS gate electrode structure, and aiming at the problem that the gate electrode capacitance, transconductance and switching frequency are lower in the structure, schottky contact is periodically introduced into the MIS gate electrode structure, the gate electrode capacitance, transconductance and switching frequency in the normally-off transistor device are improved, so that the threshold voltage of the gate electrode of the device is improved, and meanwhile, a field plate structure is formed around the gate electrode by using gate metal and a dielectric layer, so that the long-term reliability of the gate electrode of the device is improved. Specifically, the method comprises the following steps:
the embodiment of the utility model forms a P-GaN/AlGaN/GaN epitaxial heterojunction structure on a substrate layer 1, wherein an ohmic electrode 8 is arranged on the epitaxial heterojunction structure, an MIS gate electrode structure consisting of a gate dielectric layer 6 on a P-GaN cap layer 5 and a gate electrode 9 on the gate dielectric layer 6, a Schottky gate electrode structure consisting of the gate dielectric layer 6 and the gate electrode 9 filled in a plurality of grooves and contacted with the P-GaN cap layer 5 form a mixed gate electrode structure of the MIS gate electrode structure and the Schottky gate electrode structure which are periodically distributed, and a field plate structure consisting of the gate electrodes 9 on the gate dielectric layers 6 at two sides of the P-GaN cap layer 5 and the gate dielectric layers 6 at two sides of the P-GaN cap layer 5. The formed hybrid gate electrode structure integrates an MIS gate electrode and a Schottky gate electrode structure in the same gate electrode structure, and forms a hybrid gate electrode structure in which the MIS gate electrode and the Schottky gate electrode are periodically arranged in the gate electrode, so that the threshold voltage and the gate electrode leakage current of the gate electrode are improved, the transconductance and the conversion rate of the gate electrode are also improved, and the long-term reliability of the gate electrode of the device is further improved due to the fact that the edge of the hybrid gate electrode structure utilizes a field plate structure formed by gate metal on a gate dielectric layer 6 and the gate dielectric layer 6.
Preferably, the substrate 1 is a silicon substrate.
Preferably, the buffer layer 2 has a thickness of 0 μm to 5 μm; the thickness of the GaN channel layer 3 is 10 nm-4000 nm, and the GaN channel layer 3 is intrinsic doped; the thickness of the AlGaN barrier layer is 10 nm-25 nm, and the AlGaN barrier layer is doped intrinsically.
Preferably, the thickness of the P-GaN cap layer 5 is 50nm to 150nm, and the doping concentration is 1.0 multiplied by 1017cm-3～1.0×1021cm-3。
Preferably, the ohmic electrode 8 is a titanium/aluminum/titanium/gold multilayer thin film with a thickness of 200nm to 500 nm.
Preferably, the gate dielectric layer 6 is silicon nitride (SiN), and the thickness of the gate dielectric layer 6 is 5nm to 100 nm.
Preferably, each groove has a width of 1 μm to 10 μm, and an interval between adjacent grooves is 1 μm to 10 μm.
Preferably, the thickness of the gate dielectric layers 6 on both sides of the P-GaN cap layer 5 in the vertical direction is 55nm to 250 nm.
Preferably, the thickness of the passivation layer 7 is 5nm to 1000 nm.
Preferably, the gate electrode 9 is a titanium/gold multilayer film, and the thickness of the gate electrode 9 on the gate dielectric layer 6 is 30nm to 200 nm.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another gan normally-off device with a hybrid gate electrode structure according to another alternative embodiment of the present invention, where the device further includes:
and Pad electrodes disposed on the gate electrodes 9 and the ohmic electrodes 8.
Preferably, the Pad electrode is made of gold, and the thickness of the Pad electrode is 0.1-5 μm.
In summary, in the gallium nitride normally-off device with the hybrid gate electrode structure provided in the embodiment of the present invention, on the basis of the conventional P-GaN/AlGaN/GaN epitaxial structure, the gate electrode 9 on the P-GaN cap layer 5 adopts a gate electrode structure in which an MIS gate electrode structure and a schottky gate electrode structure are mixed, the threshold voltage of the gate electrode of the device is improved by using the MIS gate electrode structure, and the threshold voltage of the gate electrode of the device in actual operation can reach 3V by combining the characteristics of high capacitance and high transconductance of the schottky gate electrode structure; meanwhile, the switching frequency of the normally-closed MIS gate electrode structure device is further improved by utilizing the high carrier mobility of the two-dimensional electron air channel under the condition of maintaining the high threshold voltage of the gate electrode of the device, and meanwhile, the gate electrodes 9 on the gate dielectric layers 6 on two sides of the P-GaN cap layer 5 and the gate dielectric layers 6 on two sides of the P-GaN cap layer 5 form a field plate structure, so that the long-term reliability of the gate electrode of the device is improved.
For the device structure, the following preparation method can be adopted for preparation, and the preparation method specifically comprises the following steps:
s301, sequentially forming a buffer layer 2, a GaN channel layer 3, an AlGaN layer 4 and a P-GaN cap layer 5 on the substrate layer 1.
Specifically, referring to FIG. 4a, in the embodiment of the present invention, a buffer layer 2 with a thickness of 0 μm to 5 μm, an intrinsic doped GaN channel layer 3 with a thickness of 10nm to 4000nm, an intrinsic doped AlGaN barrier layer 4 with a thickness of 10nm to 25nm, a thickness of 50nm to 150nm, and a doping concentration of 1.0 × 10 are sequentially deposited on the surface of a substrate 1 by using a metal organic chemical vapor deposition method17cm-3～1.0×1021cm-3P-GaN cap layer 5.
S302, forming an isolation region in the whole structure comprising the substrate layer 1, the buffer layer 2, the GaN channel layer 3, the AlGaN layer 4 and the P-GaN cap layer 5, and etching the P-GaN cap layer 5, the AlGaN layer 4 and the GaN channel layer 3 outside the isolation region until reaching the buffer layer 2 to form isolation among devices.
Specifically, referring to fig. 4b, in the embodiment of the present invention, a photolithography and development technology is adopted, a photoresist is used as a mask layer to form an isolation region, the isolation region is formed in an overall structure including a substrate layer 1, a buffer layer 2, a GaN channel layer 3, an AlGaN layer 4, and a P-GaN cap layer 5, and a dry etching technology is adopted to etch the P-GaN cap layer, the AlGaN barrier layer, and the GaN channel layer 3 outside the isolation region to the buffer layer 2, so as to form isolation between devices.
S303, forming a gate electrode region on the P-GaN cap layer 5, etching the P-GaN cap layer 5 outside the gate electrode region until the AlGaN layer 4 and the P-GaN cap layer 5 in the gate electrode region.
Specifically, referring to fig. 4c, in the embodiment of the present invention, a photolithography and development technology is adopted, a photoresist is used as a mask layer to form a gate electrode region, a gate electrode region is formed on the P-GaN cap layer 5, the P-GaN cap layer 5 outside the gate electrode region is etched by a dry etching technology until the AlGaN layer 4, the P-GaN cap layer 5 of the gate electrode region, that is, the P-GaN cap layer 5 shown in fig. 1 is formed, and all the P-GaN cap layers 5 mentioned in the subsequent steps are the P-GaN cap layer 5 formed in the gate electrode region shown in fig. 1.
S304, depositing gate dielectric layers 6 on the P-GaN cap layer 5 of the gate electrode region and on two sides of the P-GaN cap layer 5 of the gate electrode region.
Specifically, referring to fig. 4d, in the embodiment of the present invention, a vapor phase epitaxy deposition technique is adopted to deposit a gate dielectric layer 6 with a thickness of 5nm to 100nm on the P-GaN cap layer 5 in the gate electrode region, and to deposit gate dielectric layers 6 with a thickness of 55nm to 250nm in the vertical direction on both sides of the P-GaN cap layer 5. The gate dielectric layer 6 may be a layer of silicon nitride (SiN), but is not limited to silicon nitride.
And S305, depositing a passivation layer 7 on the AlGaN layer 4 which is not covered by the gate dielectric layer 6.
Specifically, referring to fig. 4e, in the embodiment of the present invention, a passivation layer 7 with a thickness of 5nm to 1000nm is deposited on the AlGaN layer 4 not covered by the gate dielectric layer 6 by using a vapor phase epitaxy deposition technique. Wherein the passivation layer 7 may be a layer of silicon nitride (SiO)2) But is not limited to, silicon dioxide.
It should be noted that the gate dielectric layer 6 and the passivation layer 7 of S305 deposited in the embodiment of the present invention may be made of different materials, or may be made of the same material, and are deposited specifically according to actual requirements. If the deposited gate dielectric layer 6 and the passivation layer 7 are made of the same material, S304 and S305 can be implemented in one step without being implemented in two separate steps.
And S306, forming an ohmic region on the passivation layer 7, and etching the passivation layer 7 in the ohmic region to the AlGaN layer 4.
Specifically, referring to fig. 4f, in the embodiment of the present invention, a photolithography development technique is adopted, a photoresist is used as a mask layer to form an ohmic region, and the ohmic region is formed on the passivation layer 7; and etching the passivation layer 7 in the ohmic region to the AlGaN layer 4 by adopting a wet etching technology, wherein the wet etching solution is 15% of HF solution. According to the embodiment of the utility model, the etching precision of the ohmic region is improved through wet etching.
And S307, sequentially depositing a titanium/aluminum/titanium/gold multilayer film on the AlGaN layer 4 to form an ohmic electrode 8.
Specifically, referring to fig. 4g, in the embodiment of the present invention, a magnetron sputtering method is adopted, and titanium/aluminum/titanium/gold multilayer films are sequentially deposited at two ends of the upper surface of the AlGaN layer 4 to form the ohmic electrode 8. Then stripping the titanium/aluminum/titanium/gold multilayer film outside the AlGaN layer 4 by adopting a stripping method, and carrying out thermal annealing treatment in a nitrogen atmosphere at the annealing temperature of 500-900 ℃ to form ohmic contact.
S308, etching a plurality of grooves distributed at intervals on the gate dielectric layer 6 on the P-GaN cap layer 5, wherein each groove is etched to the P-GaN cap layer 5.
Specifically, referring to fig. 4h, in an alternative of the embodiment of the present invention, a photolithography development technology is adopted, and a photoresist is used as a mask layer to form a groove region on the gate dielectric layer 6 on the P-GaN cap layer 5; and etching the gate dielectric layer 6 in the groove region by adopting a dry etching technology to form a plurality of grooves distributed at intervals, and etching each groove until reaching the P-GaN cap layer 5 to form a Schottky gate electrode position. Preferably, each groove has a width of 1 μm to 10 μm, and an interval between adjacent grooves is 1 μm to 10 μm.
According to another alternative scheme of the embodiment of the utility model, after 70% -80% of the thickness of the gate dielectric layer 6 outside the groove region is etched in the dry etching process, the position of the Schottky gate electrode on the gate dielectric layer 6 is etched by adopting a wet etching technology, specifically, 15% of HF solution is used as a wet etching solution, and the rest gate dielectric layer 6 in the groove region is etched until the P-GaN cap layer 5 forms a plurality of grooves distributed at intervals. According to the embodiment of the utility model, the etching precision of the groove can be improved through wet etching.
After the groove is etched by the dry method or the wet method, the device structure shown in fig. 4h is annealed by adopting a rapid annealing technology, wherein the annealing temperature is 300-600 ℃, so that the contact quality of the gate dielectric layer 6 and the P-GaN cap layer 5 (the P-GaN cap layer in fig. 1) is improved.
S309, sequentially depositing a titanium/gold multilayer metal film on the gate dielectric layer 6 and in each groove to form a gate electrode 9; the gate electrode 9 formed on the gate dielectric layer 6 on the P-GaN cap layer 5 and in each groove forms a mixed gate structure of an MIS gate structure and a Schottky gate structure, and the gate electrodes 9 on the gate dielectric layers 6 on two sides of the P-GaN cap layer 5 and the gate dielectric layers 6 on two sides of the P-GaN cap layer 5 form a field plate structure.
Specifically, referring to fig. 4i, in the embodiment of the present invention, a magnetron sputtering method is adopted to sequentially deposit a titanium/gold multilayer film on the gate dielectric layer 6 and in each groove to form a gate electrode 9. And then stripping the metal outside the gate electrode area by adopting a stripping method, forming a mixed gate structure of an MIS gate electrode structure and a Schottky gate electrode structure by using the gate dielectric layer 6 on the P-GaN cap layer 5 and the gate electrode 9 formed in each groove, and forming a field plate structure by using the gate dielectric layers 9 on the gate dielectric layers on two sides of the P-GaN cap layer 5 and the gate dielectric layers 6 on two sides of the P-GaN cap layer 5. After the gate electrode 9 is formed, annealing the device structure shown in fig. 4i by using a rapid annealing technology, wherein the annealing temperature is 300-600 ℃, so as to improve the contact quality between the gate electrode 9 and the P-GaN cap layer 5.
Referring to fig. 5, fig. 5 is a schematic view of a process for manufacturing another gan normally-off device with a hybrid gate electrode structure according to an embodiment of the present invention, where the steps S301 to S309 are based on, and the process further includes:
and S310, forming a Pad area on the gate electrode 9 and the ohmic electrode 8, and depositing gold in the Pad area to form a Pad electrode 10.
Specifically, referring to fig. 2 again, in the embodiment of the present invention, a lithographic development technique is adopted, a Pad region is formed on the gate electrode 9 and the two ohmic electrodes 8 by using a photoresist as a mask layer, and gold is deposited in the Pad region by a magnetron sputtering method or an electroplating method to form a Pad electrode 10 with a thickness of 0.1 μm to 5 μm.
The metal organic chemical vapor deposition method, the magnetron sputtering method, the stripping method and other operation methods mentioned in the embodiments of the present invention are all the prior art, and are not described herein again.
For the preparation method embodiment, since it is basically similar to the device embodiment, the description is simple, and the relevant points can be referred to the partial description of the device embodiment.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a more detailed description of the utility model in connection with specific preferred embodiments and it is not intended that the utility model be limited to these specific details. For those skilled in the art to which the utility model pertains, several simple deductions or substitutions can be made without departing from the spirit of the utility model, and all shall be considered as belonging to the protection scope of the utility model.

Claims (6)

1. A gallium nitride normally-off device having a hybrid gate electrode structure, comprising: a substrate layer; the buffer layer, the GaN channel layer and the AlGaN layer are sequentially arranged on the substrate layer;
the P-GaN cap layer and the two ohmic electrodes are arranged on the AlGaN layer; the two ohmic electrodes are respectively arranged at two ends of the upper surface of the AlGaN layer, and the P-GaN cap layer is arranged between the two ohmic electrodes;
the gate dielectric layers are arranged on the P-GaN cap layer and on two sides of the P-GaN cap layer; a plurality of grooves distributed at intervals are arranged on the gate dielectric layer on the P-GaN cap layer, and each groove penetrates through the gate dielectric layer to reach the upper surface of the P-GaN cap layer;
the passivation layer is arranged on the AlGaN layer and is positioned between the ohmic electrode and the gate dielectric layers on two sides of the P-GaN cap layer;
the gate electrode is arranged on the gate dielectric layer and filled in the grooves; the gate electrode on the gate dielectric layer on the P-GaN cap layer and the gate electrodes filled in the grooves form a mixed gate electrode structure of an MIS gate structure and a Schottky gate structure, and the gate electrodes on the gate dielectric layers on two sides of the P-GaN cap layer and the gate dielectric layers on two sides of the P-GaN cap layer form a field plate structure.
2. The GaN normally-off device with hybrid gate electrode structure of claim 1, wherein the thickness of the gate dielectric layer on the P-GaN cap layer is 5nm to 100 nm.
3. The gan normally-off device with hybrid gate electrode structure of claim 1, wherein each of the recesses has a width of 1 μm to 10 μm and a spacing between adjacent recesses is 1 μm to 10 μm.
4. The GaN normally-off device with hybrid gate electrode structure of claim 1, wherein the gate dielectric layers on both sides of the P-GaN cap layer have a thickness of 55nm to 250nm in the vertical direction.
5. The gan normally-off device with hybrid gate electrode structure of claim 1, wherein the passivation layer has a thickness of 5nm to 1000 nm.
6. The gallium nitride normally-off device with a hybrid gate electrode structure of claim 1, further comprising:
and a Pad electrode disposed on the gate electrode and the ohmic electrode.
CN202121958168.5U 2021-08-19 2021-08-19 Gallium nitride normally-off device with mixed gate electrode structure Active CN216671641U (en)

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