CN116094502B

CN116094502B - Dynamic comparator, analog-to-digital converter and electronic equipment

Info

Publication number: CN116094502B
Application number: CN202310336191.8A
Authority: CN
Inventors: 吴积方; 何海龙
Original assignee: Shenzhen Jiutian Ruixin Technology Co ltd
Current assignee: Chengdu Jiutian Ruixin Technology Co.,Ltd.
Priority date: 2023-03-31
Filing date: 2023-03-31
Publication date: 2023-06-09
Anticipated expiration: 2043-03-31
Also published as: CN116094502A

Abstract

The invention discloses a dynamic comparator, an analog-to-digital converter and electronic equipment, wherein the dynamic comparator comprises an input stage module, a switch module and a latch module, and the input stage module outputs a first amplified voltage signal and a second amplified voltage signal; the switch module is used for controlling the first positive electrode input end and the first negative electrode input end to be respectively and alternately communicated with the first positive electrode output end and the first negative electrode output end in a one-to-one correspondence manner so that the first positive electrode output end and the first negative electrode output end respectively switch and output a first amplified voltage signal and a second amplified voltage signal; the latch module is used for outputting a comparison result. According to the technical scheme, the first amplified voltage signal and the second amplified voltage signal are alternately switched and output through the switch module, so that the input signals of the positive electrode input end and the negative electrode input end of the latch module are dynamically switched, the latch module can dynamically turn over along with the input signals, automatic comparison is not required to be performed completely depending on the turning over of the input end signals of the input stage module, and the situation of degradation of the comparator is avoided.

Description

Dynamic comparator, analog-to-digital converter and electronic equipment

Technical Field

The present invention relates to the field of analog integrated circuits, and more particularly, to a dynamic comparator, an analog-to-digital converter, and an electronic device.

Background

Analog-to-digital Converter (ADC) converters, in which comparators are an important component, perform the conversion of Analog signals to digital signals. With the development of advanced semiconductor manufacturing processes, particularly the current advanced processes such as the current advanced processes of 7nm and 3nm, the degradation (Aging) of transistor devices is more and more serious, and the degradation of devices can cause a series of problems such as leakage, slow speed, large offset and the like, which finally affect the performance of circuits; the transistor degradation causes include hot carrier injection (Hot Carrier Injection, HCI), bias temperature instability (Bias Temperature Instability, BTI), etc. Therefore, the degradation of the comparator affects the overall performance of the analog-to-digital converter, and thus the overall performance of the electronic product.

Disclosure of Invention

The embodiment of the invention provides a dynamic comparator, an analog-to-digital converter and electronic equipment, which are used for solving the problem that the integral performance of the analog-to-digital converter is affected due to the fact that the comparator is not resistant to degradation in the prior art.

A first aspect of an embodiment of the present invention provides a dynamic comparator, including:

The input stage module is used for amplifying the first voltage signal and the second voltage signal when the first clock signal is enabled and obtaining a first amplified voltage signal and a second amplified voltage signal;

the latch module comprises a second positive electrode input end and a second negative electrode input end, and is used for comparing the first amplified voltage signal with the second amplified voltage signal and outputting a comparison result; a kind of electronic device with high-pressure air-conditioning system

The switch module comprises a first positive electrode input end, a first negative electrode input end, a first positive electrode output end, a first negative electrode output end and a control end, wherein the first positive electrode input end is connected with one of the first amplified voltage signal and the second amplified voltage signal, the first negative electrode input end is connected with the other of the first amplified voltage signal and the second amplified voltage signal, one of the first positive electrode output end and the first negative electrode output end is connected with the second positive electrode input end of the latch module, the other of the first positive electrode output end and the first negative electrode output end is connected with the second negative electrode input end of the latch module, the control end is connected with a second clock signal, and the switch module is used for controlling the first positive electrode input end and the first negative electrode input end to be respectively and alternately communicated with the first positive electrode output end and the first negative electrode output end one by one, so that the first positive electrode output end and the first negative electrode output end are respectively switched to the first amplified voltage signal and the second negative electrode output end are respectively.

A second aspect of the embodiment of the present invention provides an analog-to-digital converter, which includes the dynamic comparator of the first aspect.

A third aspect of an embodiment of the present invention provides an electronic device, including the analog-to-digital converter according to the second aspect.

The technical effects of the embodiment of the invention are as follows: the switch module is arranged between the input stage module and the latch module, and the switch module is controlled to switch the output signal according to the second clock signal, so that the input signals of the positive electrode input end and the negative electrode input end of the latch module are dynamically switched, the latch module can dynamically turn over along with the input signals, and the state of the input end signal of the input stage module of the comparator is not required to be completely relied on for automatic turning over, so that the problem that the overall performance of the analog-digital converter is influenced due to the fact that the comparator is not resistant to degradation is avoided.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a dynamic comparator according to a first embodiment of the present invention;

fig. 2 is a schematic diagram of a dynamic comparator according to a second embodiment of the present invention;

fig. 3 is a schematic structural diagram of a switch module of a dynamic comparator according to a second embodiment of the present invention;

fig. 4 is a schematic structural diagram of a dynamic comparator according to a third embodiment of the present invention;

fig. 5 is a schematic structural diagram of an output stage module of a dynamic comparator according to a third embodiment of the present invention;

fig. 6 is a schematic diagram of a clock signal generating module of a dynamic comparator according to a third embodiment of the present invention;

fig. 7 is a circuit diagram of a clock signal generating module of a dynamic comparator according to a third embodiment of the present invention;

fig. 8 is a clock signal waveform diagram of a clock signal generating module of a dynamic comparator according to a third embodiment of the present invention;

fig. 9 is a schematic structural diagram of an input stage module of a dynamic comparator according to a fourth embodiment of the present invention;

FIG. 10 is a circuit diagram of a dynamic comparator according to a fifth embodiment of the present invention;

FIG. 11 is a waveform diagram of a clock signal of a dynamic comparator according to a fifth embodiment of the present invention;

in the figure: 101. an input stage module; 102. a switch module; 103. a latch module; 104. an output stage module; 121. a first control switch; 122. a second control switch; 123. a third control switch; 124. a fourth control switch; 141. a precharge module; 142. a fifth switch; 143. a sixth switch; 144. a seventh switch; 145. an eighth switch; 146. a ninth switch; 147. a tenth switch; 201. a reversing module; 202. a first D flip-flop; 203. a second D flip-flop; 204. a first clock signal generation module; 205. a second clock signal generation module; 206. a third clock signal generation module; 207. a fourth clock signal generation module; 208. and a fifth clock signal generation module.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the following description, for the purpose of providing a thorough understanding of the present invention, detailed structures and steps are presented in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

The dynamic comparator and the analog-to-digital converter provided by the embodiment of the invention are applied to various fields, including but not limited to the following technical fields:

technical field of communication systems: analog-to-digital converters are used for signal processing in digital communication systems, for example to convert analog speech signals into digital signal transmissions.

Technical field of control system: the analog-to-digital converter is used for collecting analog sensor signals, converting the analog sensor signals into digital signals, and then using the digital signal processor to control and monitor the control system.

Audio and video system technology: analog-to-digital converters are used to convert analog audio and video signals to digital signals, such as in CD, DVD, and digital television devices.

Test and measurement equipment technical field: analog-to-digital converters are used in a variety of test and measurement equipment such as data acquisition cards, oscilloscopes, signal generators, and the like.

Automotive electronics technology field: analog-to-digital converters are used for signal processing in automotive electronics, for example, to convert sensor signals to digital signals for processing by an on-board computer.

Medical equipment technical field: analog-to-digital converters are used in a variety of medical devices, such as electrocardiographs, blood pressure meters, blood glucose meters, and the like.

Example 1

An embodiment of the invention provides a dynamic comparator, which solves the problem that the overall performance of an analog-digital converter is affected due to degradation intolerance of the comparator in the prior art.

In one embodiment of the present invention, as shown in fig. 1, a dynamic comparator is provided, where the dynamic comparator includes:

the input stage module 101, the input end of which is connected with the first voltage signal and the second voltage signal, the control end of which is connected with the first clock signal CK1, is used for amplifying the first voltage signal and the second voltage signal when the first clock signal CK1 is enabled and obtaining a first amplified voltage signal and a second amplified voltage signal;

The latch module 103 comprises a second positive electrode input end and a second negative electrode input end, and the latch module 103 is used for comparing the first amplified voltage signal with the second amplified voltage signal and outputting a comparison result;

the switch module 102 includes a first positive input end, a first negative input end, a first positive output end, a first negative output end, and a control end, where the first positive input end is connected to one of the first amplified voltage signal and the second amplified voltage signal, the first negative input end is connected to the other of the first amplified voltage signal and the second amplified voltage signal, one of the first positive output end and the first negative output end is connected to the second positive input end of the latch module, the other of the first positive output end and the first negative output end is connected to the second negative input end of the latch module 103, the control end is connected to the second clock signal CK2, and the switch module 102 is configured to control the first positive input end and the first negative input end to be alternately communicated with the first positive output end and the first negative output end one by one according to the second clock signal CK2, so that the first positive output end and the first negative output end switch and the second amplified voltage signal to the latch module 103 respectively.

The first clock signal CK1 may be enabled in a rising edge state or a high level state, and the input stage module 101 is configured to amplify the first voltage signal and the second voltage signal according to the first clock signal CK1 when the first clock signal CK1 is enabled, so as to obtain the first voltage signal and the second voltage signal with higher resolution. The first clock signal CK1 being inactive means that the state in which the first clock signal CK1 is in is opposite to the enable state, for example, when the first clock signal CK1 is inactive and may be in a falling edge or a low level state, the first voltage signal and the second voltage signal are reset, and at this time, the output first amplified voltage signal and the second amplified voltage signal are both in a high level or a low level. The input stage module 101 may be isolated in addition to amplification to avoid reverse impact of subsequent circuitry on the input signal.

The switch module 102 includes a first positive input end, a first negative input end, a first positive output end, and a first negative output end, where the first positive input end is connected to the second amplified voltage signal when the first positive input end is connected to the first amplified voltage signal, or the first positive input end is connected to the second amplified voltage signal when the first positive input end is connected to the first amplified voltage signal. The switch module 102 may control the first positive input end and the first negative input end to be alternately connected with the first positive output end and the first negative output end according to the second clock signal, where the one-to-one correspondence refers to that one input end is connected with only one output end, and the case that one input end is not connected with two output ends or two input ends are connected with one output end is not included, including that the first positive input end is connected with the first positive output end, the first negative input end is connected with the first negative output end, or the first positive input end is connected with the first negative output end, and the first negative input end is connected with the first positive output end. The alternate connection means that the two groups of corresponding relations are switched on. The alternately connected time points may be within one period or may not be within one period of the second clock signal CK2. Taking alternate connection in one period as an example, for example, when the second clock signal CK2 is at a high level, the first positive input terminal is connected to the first positive output terminal, and the first negative input terminal is connected to the first negative output terminal; when the second clock signal CK2 is at a low level, the first positive input terminal is connected to the first negative output terminal, and the first negative input terminal is connected to the first positive output terminal. The switch module 102 may have two controllable switches, wherein an input end of each controllable switch is connected to a voltage signal, control ends of the two controllable switches are both connected to the second clock signal CK2, and different input ends and output ends are connected through a change-over switch; or four controllable switches are arranged, wherein the input ends of the two controllable switches are connected with a voltage signal, the control ends of the two controllable switches are connected with the second clock signal CK2, and the control ends of the other two controllable switches are connected with the second clock signal CK2 through an inverter. Or two complementary switching tubes (PNP or NPN switching tubes) and two diodes are adopted to form a switch gating circuit. The difference between the adding switch module 102 and the prior art is that the output signal is directly switched according to the state of the second clock signal CK2 without depending on the receiving signal, so that the output signal can be dynamically changed to the input end of the latch module more flexibly.

The latch module 103 is configured to compare the first amplified voltage signal and the second amplified voltage signal output from the switch module 102 and output a result. When the comparator is in a no-input flip scene or the input signal is unchanged for a long time, the latch module 103 maintains the latch state and cannot flip when the input signal is unchanged, so that the comparator is degraded. When the switch module 102 changes the state of the output signal of the output end of the switch module 102 according to the second clock signal CK2, the latch module 103 restarts to work, so that the state that the latch module 103 has no input signal or the latch state cannot be turned over is avoided.

The first embodiment of the invention has the technical effects that: by arranging the switch module between the input stage module and the latch module, the switch module is turned on and off according to the second clock signal, and the input end of the latch stage in the comparator can be controlled to be dynamically switched through the time sequence switch, so that the latch module can dynamically turn over along with the input signal, and the automatic comparison is not required to be completely carried out by the turning over of the input end signal of the input stage module, thereby avoiding the situation that the latch module maintains the latch state and cannot be turned over to cause degradation under the condition that the comparator does not have an input turning over scene or the input signal is unchanged for a long time.

Example two

The second embodiment of the invention provides a dynamic comparator, which solves the problem of how to realize that two clock signals control a switch module so as to output different signals to a latch module in the first embodiment.

According to the technical scheme provided by the second embodiment of the present invention, as shown in fig. 2, based on the technical scheme provided by the first embodiment, the control end of the switch module 102 is further connected to a third clock signal, and the switch module 102 is configured to control the first positive input end and the first negative input end to be alternately communicated with the first positive output end and the first negative output end in a one-to-one correspondence manner according to the second clock signal and the third clock signal, so that the first positive output end and the first negative output end respectively switch and output the first amplified voltage signal and the second amplified voltage signal to the latch module 103.

The difference between the second embodiment and the first embodiment is that the number of the input clock signals is different, and the second embodiment inputs the second clock signal and the third clock signal to the control terminal of the switch module 102 at the same time, so that the first amplified voltage signal and the second amplified voltage signal can be output in different manners. The output modes of the different modes include: the first output mode may be to alternately control the switch to be turned on by the second clock signal and the third clock signal, so that the first positive output terminal of the switch module 102 outputs the first amplified voltage signal, and the first negative output terminal outputs the second amplified voltage signal. The second output mode may be to alternately control the switch to be turned on by the second clock signal and the third clock signal, so that the first positive output terminal of the switch module 102 outputs the second amplified voltage signal, and the first negative output terminal outputs the first amplified voltage signal. The technical effect of the two modes is that the latch module 103 can automatically realize dynamic overturning. The third way may be to alternately control the switch to be turned on by the second clock signal and the third clock signal, so that the first positive output terminal of the switch module 102 alternately outputs the first amplified voltage signal and the second amplified voltage signal, and the first negative output terminal alternately outputs the second amplified voltage signal and the second amplified voltage signal. The third mode has the technical effect that the input signal of the latch module 103 can be dynamically adjusted by turning over the output signals of the first output end and the second output end, so that the latch module 103 can automatically realize dynamic turning over. The problem of aging caused by the fact that the input signal of the latch module 103 is unchanged for a long time is avoided.

For the third mode, in each clock cycle of the first clock signal, the second clock signal and the third clock signal control the first positive input terminal and the first negative input terminal to be alternately communicated with the first positive output terminal and the first negative output terminal in one-to-one correspondence. The specific operation of the switch module 102 is: when the second clock signal is enabled and the third clock signal is invalid, the first positive electrode input end is connected with the first positive electrode output end, and the first negative electrode input end is connected with the first negative electrode output end; when the second clock signal is invalid and the third clock signal is enabled, the first positive electrode input end is connected with the first negative electrode output end, and the first negative electrode input end is connected with the first positive electrode output end.

The second clock signal is enabled to be in a falling edge or low level state, and the second clock signal is disabled to be in a rising edge or high level state. The third clock signal enable may be a rising edge or a high state and the second clock signal disable may be a falling edge or a low state.

In the embodiment, two clock signals are adopted, so that the switching-on time of the input end and the output end of the switch can be adjusted more flexibly than the time of adopting one clock signal.

As an example of the implementation of the third manner, as shown in fig. 3, the switch module 102 includes a first control switch 121, a second control switch 122, a third control switch 123 and a fourth control switch 124, where an input end of the first control switch 121 and an input end of the fourth control switch 124 are commonly connected to form a first positive input end, an input end of the second control switch 122 and an input end of the third control switch 123 are commonly connected to form a first negative input end, a control end of the first control switch 121 and a control end of the second control switch 122 are both connected to a second clock signal, a control end of the third control switch 123 and a control end of the fourth control switch 124 are both connected to a third clock signal, an output end of the second control switch 122 and an output end of the fourth control switch 124 are commonly connected to form a first positive output end, an output end of the first control switch 121 and an output end of the third control switch 123 are commonly connected to form a first negative output end, when the second clock signal is enabled, the first control switch 121 and the second control switch 122 are both connected to the second clock signal, and the fourth control switch 124 are both connected to the third clock signal.

The first to fourth control switches 121 to 124 may be PMOS transistors, and at this time, the second clock signal enable may be a falling edge or a low level state, and the second clock signal disable may be a rising edge or a high level state. The third clock signal enable may be a rising edge or a high state and the second clock signal disable may be a falling edge or a low state. The first control switch 121 to the fourth control switch 124 may also be NMOS transistors, and enabling and disabling of the second clock signal and the third clock signal is opposite to the above.

For enabling time points of the second clock signal and the third clock signal, in each clock period of the first clock signal, the second clock signal and the third clock signal are used for enabling the first positive electrode input end and the first negative electrode input end to be respectively and alternately communicated with the first positive electrode output end and the first negative electrode output end in a one-to-one correspondence mode.

It should be noted that the second clock signal and the third clock signal are input ends of the latch stage alternately switched in each clock cycle of the first clock signal, and the switching manner of the second clock signal and the third clock signal in the present invention is not limited to this switching manner, and other switching manners such as random flip replacement switching are also applicable to the present invention.

The technical effect of the technical scheme provided in the second embodiment is as follows: through inputting second clock signal and third clock signal in the switch module, and then realize outputting or overturn and export first amplified voltage signal and second amplified voltage signal, can the input signal of dynamic regulation latch module for latch state can realize dynamic upset automatically, avoids latch module's input signal to constantly lead to ageing problem for a long time.

Example III

The third embodiment of the invention provides a dynamic comparator, which solves the problem of how to realize that the output polarity of the whole signal is unchanged when the output of the switch module in the second embodiment turns over the input signal.

The technical solution provided by the third embodiment of the present invention is based on the technical solution provided by the second embodiment, as shown in fig. 4, and the dynamic comparator further includes:

the output stage module 104 includes a third positive input end, a third negative input end, a third positive output end, a third negative output end and a control end, wherein the third positive input end is connected with the second positive output end of the latch module, the third negative input end is connected with the second negative output end of the latch module, the third positive output end outputs a first comparison signal, the third negative output end outputs a second comparison signal, and the control end is connected with the fourth clock signal CK4 and the fifth clock signal CK5, so that the polarities of the first comparison signal and the first voltage signal are consistent according to the fourth clock signal CK4 and the fifth clock signal CK5, and the polarities of the second comparison signal and the second voltage signal are consistent.

The input stage module 101 includes a fourth positive input end, a fourth negative input end, a fourth positive output end, and a fourth negative output end, where the fourth positive input end is connected to the first voltage signal, the fourth negative input end is connected to the second voltage signal, the fourth positive output end outputs a first amplified voltage signal to the first positive input end, the fourth negative output end outputs a second amplified voltage signal to the first negative input end, the first positive output end is connected to the second positive input end, and the first negative output end is connected to the second negative input end.

The fact that the first comparison signal is consistent with the signal polarity of the first positive input end of the switch module 102 and the second comparison signal is consistent with the signal polarity of the first negative input end of the switch module means that the third positive output end of the output stage module 104 has a corresponding relationship with the first positive input end of the switch module 102 and the third negative output end of the output stage module 104 has a corresponding relationship with the first negative input end of the switch module 102, in the comparator, the polarities of the input end and the output end refer to their voltage relationship, and the polarities are the same, which means that the two ports have the same voltage relationship. For example, when the voltage at the non-inverting input terminal of the comparator is higher than the voltage at the inverting input terminal, the voltage at the output terminal is high or positive, and the polarities of the input terminal and the output terminal are the same, both being high or positive. Similarly, when the voltage at the inverting input is higher than the voltage at the non-inverting input, the voltage at the output is either low or negative, and the polarities of the input and output are the same. That is, when the switch module 102 normally outputs signals of the first positive input end and the first negative input end, the latch module 103 is turned over and then outputs the signals to the output stage module, and the third positive output end and the third negative output end of the output stage module 104 normally output a first comparison signal and a second comparison signal; when the switch module 102 turns over and outputs the signals of the first positive electrode input end and the first negative electrode input end, the latch module 103 outputs the signals to the output stage module 104 after turning over, and the third positive electrode output end and the third negative electrode end of the output stage module 104 turn over and output the first comparison signal and the second comparison signal, so that the overall polarity can be kept unchanged.

As an example, when the voltage value of the signal of the fourth positive input terminal of the input stage module 101 is greater than the voltage value of the signal of the fourth negative input terminal of the input stage module 101, the polarity of the first comparison signal is at a high level, and the polarity of the second comparison signal is at a low level; when the voltage value of the signal at the fourth positive input terminal of the input stage module 101 is smaller than the voltage value of the signal at the fourth negative input terminal of the input stage module 101, the polarity of the first comparison signal is low, and the polarity of the second comparison signal is high.

In order that the first comparison signal and the second comparison signal reflect the magnitude relationship (the same polarity) between the signal at the fourth positive input terminal of the input stage module 101 and the signal at the fourth negative input terminal of the input stage module 101, there is a correspondence relationship between the fourth clock signal CK4 and the fifth clock signal CK5 and the second clock signal and the third clock signal: for example, when the second clock signal and the third clock signal function to directly transmit the first amplified voltage signal and the second amplified voltage signal to the latch module 103, the fourth clock signal CK4 and the fifth clock signal CK5 cause the output stage module 104 to directly output the comparison result of the latch module 103; when the second clock signal and the third clock signal are used to invert the first amplified voltage signal and the second amplified voltage signal and send the inverted signals to the latch module 103, the fourth clock signal CK4 and the fifth clock signal CK5 enable the output stage module 104 to invert the comparison result of the latch module 103 and output the inverted result. The technical effect of the working mode is to ensure that the output polarity is unchanged.

Wherein, in a period of the first clock, when the second clock signal is enabled and the third clock signal is disabled, the fourth clock signal is enabled and the fifth clock signal is disabled, the polarities of the first comparison signal and the first voltage signal are the same, and the polarities of the second comparison signal and the second voltage signal are the same; when the second clock signal is inactive and the third clock signal is enabled, the fourth clock signal is inactive and the fifth clock signal is enabled, the polarities of the first comparison signal and the first voltage signal are the same, and the polarities of the second comparison signal and the second voltage signal are the same.

When the second positive input end of the latch module 103 is connected with the first amplified voltage signal and the second negative input end is connected with the second amplified voltage signal, the latch module 103 compares the first amplified voltage signal with the second amplified voltage signal, and outputs a third comparison signal from the second positive output end and a fourth comparison signal from the second negative output end; when the second positive input terminal of the latch module 103 is connected to the second amplified voltage signal and the second negative input terminal is connected to the first amplified voltage signal, the latch module 103 compares the first amplified voltage signal and the second amplified voltage signal, and outputs a fourth comparison signal from the second positive output terminal and a third comparison signal from the second negative output terminal.

In one period of the first clock, when the second clock signal is enabled and the third clock signal is disabled, the fourth clock signal CK4 is enabled and the fifth clock signal CK5 is disabled, the polarities of the first comparison signal and the third comparison signal are the same, and the polarities of the second comparison signal and the fourth comparison signal are the same; when the second clock signal is inactive and the third clock signal is enabled, the fourth clock signal CK4 is inactive and the fifth clock signal CK5 is enabled, the polarities of the first comparison signal and the fourth comparison signal are the same, and the polarities of the second comparison signal and the third comparison signal are the same.

In order to achieve the above-mentioned result, the structure of the output stage module 104 is designed to include a switch capable of inverting a signal, as an example, as shown in fig. 5, the output stage module 104 includes a precharge module 141, a fifth switch 142, a sixth switch 143, a seventh switch 144, an eighth switch 145, a ninth switch 146, and a tenth switch 147, the control terminals of the first control terminal and the ninth switch 146 of the precharge module 141 are input with the fourth clock signal CK4, the control terminals of the second control terminal and the tenth switch 147 of the precharge module 141 are input with the fifth clock signal CK5, the input terminal of the precharge module 141 is connected with the output terminal of the fifth switch 142 and the output terminal of the seventh switch 144, and forms a third positive output terminal of the output stage module 104, the second output terminal of the precharge module 141 is connected with the output terminal of the eighth switch 145, and forms a third negative output terminal of the output stage module 104, the control terminal of the fifth switch 142 and the control terminal of the eighth switch 146 are connected with the fifth switch 146, and the control terminal of the fifth switch 145 is connected with the fifth switch 146 is connected with the fifth input terminal of the fifth switch 143, and the fourth output terminal of the eighth switch is connected with the fifth switch 143 is connected with the fifth positive output terminal of the output stage module 104.

When the fourth clock signal CK4 is enabled and the fifth clock signal CK5 is disabled, the ninth switch 146 is turned on, the tenth switch 147 is turned off, when the level signal of the third positive input terminal is at a high level and the level signal of the third negative input terminal is at a low level, the sixth switch 143 and the seventh switch 144 are turned on, the fifth switch 142 and the eighth switch 145 are turned off, the third negative output terminal is connected to ground through the seventh switch 144 and the ninth switch 146, and the precharge module 141 outputs a high level signal to the third positive output terminal, so the third positive output terminal of the output stage module 104 outputs a high level signal, and the third negative output terminal outputs a low level signal.

When the fourth clock signal CK4 is inactive and the fifth clock signal CK5 is enabled, the ninth switch 146 is turned off, the tenth switch 147 is turned on, when the level signal of the third positive input terminal is at a low level and the level signal of the third negative input terminal is at a high level, the sixth switch 143 and the seventh switch 144 are turned off, the fifth switch 142 and the eighth switch 145 are turned on, the third negative output terminal is connected to ground through the eighth switch 145 and the tenth switch 147, and the precharge module 141 outputs a high level signal to the third positive output terminal, so the third positive output terminal of the output stage module 104 outputs a high level signal, and the third negative output terminal outputs a low level signal, and at this time, the output stage module 104 inverts the input signal.

In order to achieve the above function and solve the problem of how to output a clock signal, according to a fourth technical solution provided in an embodiment of the present invention, as shown in fig. 6, the dynamic comparator further includes a clock signal generating module, the clock signal generating module is connected to an initial clock signal, and the clock signal generating module includes:

an inverting module 201, the input end of which is connected with an initial clock signal;

a first D flip-flop 202, the clock input of which is connected to the output of the inverting module 201;

a second D flip-flop 203 having a clock input connected to the initial clock signal and a data input connected to the output of the first D flip-flop 202;

the input end of the first clock signal generating module 204 is connected with the output end of the reversing module 201;

a second clock signal generating module 205, a first input end of which is connected to the output end of the first D flip-flop 202, and a second input end of which is connected to the initial clock signal;

a third clock signal generating module 206, a first input terminal of which is connected to the output terminal of the first D flip-flop 202, and a second input terminal of which is connected to the initial clock signal;

a fourth clock signal generating module 207, a first input end of which is connected to the output end of the second D flip-flop 203, and a second input end of which is connected to the output end of the inverting module 201;

The first input end of the fifth clock signal generating module 208 is connected to the output end of the second D flip-flop 203, and the second input end is connected to the output end of the inverting module 201.

Further, as shown in fig. 7, the reversing module 201 includes a reverser G1, a reverser G2, and a reverser G3; the first D flip-flop 202 is a D flip-flop D1, the second D flip-flop 203 is a D flip-flop D2, the first clock signal generating module 204 is an inverter G6, the second clock signal generating module 205 is a nand gate G10, the third clock signal generating module 206 includes an inverter G5 and a nand gate G11, the fourth clock signal generating module 207 includes an inverter G7 and an and gate G9, and the fifth clock signal generating module 208 is an and gate G8; the initial clock signal is connected with an input end of the inverter G1, an input end of the inverter G3, an input end of the inverter G4, a first input end of the NAND gate G10, a clock input end of the D trigger D2 and a first input end of the NAND gate G11, an output end of the inverter G4 is connected with an input end of the inverter G6, an output end of the inverter G6 outputs a first clock signal CK1, an output end of the inverter G3 is connected with a clock input end of the D trigger D1, a Q output end of the D trigger D1 is connected with an input end of the inverter G2, a data input end of the D trigger D2, an input end of the inverter G5 and a second input end of the NAND gate G10, an output end of the NAND gate G11 outputs a third clock signal CK3, an output end of the NAND gate G10 outputs a second clock signal CK2, a Q output end of the D trigger D2 is connected with an input end of the inverter G7 and a first input end of the AND gate G8, a data input end of the D trigger D2, an input end of the inverter G5 is connected with a second input end of the AND gate G9, and an output end of the second clock signal CK 9 is connected with an output end of the AND gate G9.

With the above-described exemplary configuration, the output waveforms as shown in fig. 8 can be realized, and the initial clock signal CK0 is passed through the clock signal generating module to obtain the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, and the fifth clock signal CK5, respectively.

The technical effect of the technical scheme provided by the third embodiment of the invention is as follows: through setting the corresponding relation between the fourth clock signal and the fifth clock signal of the output stage module and the second clock signal and the third clock signal, the first comparison signal and the second comparison signal output by the output stage module reflect the magnitude relation of the input voltage signals of the positive electrode input end and the negative electrode input end of the switch module, and the output polarity is ensured to be unchanged.

Example IV

The fourth embodiment of the invention provides a dynamic comparator, which solves the problem of how to reduce the kickback noise of an input voltage signal in the first embodiment.

The first technical scheme provided by the fourth embodiment of the present invention is applicable to the technical schemes provided by at least one of the first to third embodiments. Taking the technical scheme based on the third embodiment as an example, the fourth positive input end of the input stage module 101 is further connected to a first voltage compensation module, and the first voltage compensation module is used for performing voltage compensation on the first voltage signal; and/or, the fourth negative input end of the input stage module 101 is further connected to a second voltage compensation module, and the second voltage compensation module is used for performing voltage compensation on the second voltage signal.

In the process of waiting for the first clock signal to enable, a certain kick noise is generated on the first input terminal and the second input terminal of the input stage module 101, so that the common mode voltage is reduced. In order to boost the common mode voltage, a voltage compensation of the first voltage signal and/or the second voltage signal is required. The voltage compensation module is connected with the first input end and the second input end to provide compensation voltage. The voltage compensation module is a voltage source module for storing voltage, for example, the voltage compensation module is charged by an external power supply, so that the voltage compensation module maintains a certain voltage value, and further voltage compensation is performed.

The technical effect of the first technical scheme of the fourth embodiment is that by performing voltage compensation on the voltages input by the first input end and the second input end, the kick noise of the first input end and the second input end is reduced, and the reduced common mode voltage is also compensated.

Further, based on the first technical solution provided in the fourth embodiment, the fourth embodiment provides a second technical solution, in which, in order to optimize the power supply terminals of the first voltage compensation module and the second voltage compensation module, the first clock signal is used to compensate the first voltage compensation module and the second voltage compensation module. The first end of the first voltage compensation module is connected with the first input end of the input stage module 101, the first end of the second voltage compensation module is connected with the second input end of the input stage module 101, and the second end of the first voltage compensation module and the second end of the second voltage compensation module are both connected with the first clock signal.

The first voltage compensation module comprises a first compensation capacitor, a first end of the first compensation capacitor is connected with a fourth positive input end of the input stage module, and a second end of the first compensation capacitor is connected with a first clock signal; and/or the second voltage compensation module comprises a second compensation capacitor, a first end of the second compensation capacitor is connected with a fourth negative input end of the input stage module, and a second end of the second compensation capacitor is connected with the first clock signal.

The technical effects of the second technical scheme of the fourth embodiment are as follows: the first voltage compensation module and the second compensation module are charged through the first clock signal, voltage compensation is conducted on the voltage input by the first input end and the second input end, kickback noise of the first input end and the second input end is reduced, meanwhile, the lowered common-mode voltage is compensated, the clock signal is adopted for voltage compensation, a voltage source of a compensation circuit is not required to be additionally arranged, the clock signal is multiplexed, and the problem that the voltage of the voltage compensation module drops and the input voltage cannot be compensated timely is avoided.

As an example, as shown in fig. 9, the input stage module 101 includes a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, and an NMOS transistor M5. In this structure, when the clock signal CK1 is low, the source-drain voltages of the NMOS transistor M3 and the NMOS transistor M4 are pulled up to the power supply voltage VDD. After the clock signal CK1 is pulled up to a high level, the source voltages of the NMOS transistors M3 and M4 are pulled down to the ground level GND, so that kickback noise is generated on the common mode voltage input to the comparator through the gate-source overlap capacitance of the input tube. The difference between this example and the prior art is that the input stage module 101 further includes a capacitor C1 and a capacitor C2, where a first end of the capacitor C1 is connected to the gate of the NMOS transistor M3 and connected to the first voltage signal, a second end of the capacitor C1 is connected to the gate of the NMOS transistor M5 and connected to the first clock signal, a first end of the capacitor C2 is connected to the gate of the NMOS transistor M4 and connected to the second voltage signal, and a second end of the capacitor C1 is connected to the gate of the NMOS transistor M5 and connected to the first clock signal. When the rising edge of the first clock signal comes, the capacitor C1 and the capacitor C2 are charged, and the voltage formed on the capacitor C1 and the capacitor C2 supplements the voltage of the first voltage signal and the voltage of the second voltage signal, so that the kickback noise of the first input end and the second input end is reduced, and the reduced common-mode voltage is compensated.

Example five

The fifth embodiment of the present invention provides a dynamic comparator, and the first to fourth embodiments are specifically described by specific circuit structures.

In the fifth embodiment of the present invention, as shown in fig. 10 and 11, the dynamic comparator includes an input stage module 101, a switch module 102, a latch module 103, and an output stage module 104, where a first voltage signal VIP is input to a fourth positive input terminal of the input stage module 101, a second voltage signal VIN is input to a fourth negative input terminal of the input stage module 101, a first clock signal CK1 is input to a control terminal, a first positive input terminal of the switch module 102 is connected to a fourth positive output terminal of the input stage module 101, a first negative input terminal of the switch module 101 is connected to a first negative input terminal of the switch module 102, a second clock signal CK2 is input to a first control terminal of the switch module 102, a third clock signal CK3 is input to a second control terminal of the switch module 102, a first negative output terminal of the switch module 102 is connected to a second positive input terminal of the latch module 103, a second positive output terminal of the latch module 103 is connected to a third positive input terminal of the output stage module 104, a second negative output terminal of the latch module 103 is connected to a second negative input terminal of the second clock signal CK4 is input to the fourth negative input terminal of the latch module 104.

The input stage module 101 includes a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, a capacitor C1, and a capacitor C2, where the gate of the NMOS transistor M3 is commonly connected to the first end of the capacitor C1 and forms a fourth negative input end of the input stage module 101, the second end of the capacitor C1 is connected to the gate of the NMOS transistor M5 and forms a control end of the input stage module 101, the gate of the NMOS transistor M4 is commonly connected to the first end of the capacitor C2 and forms a fourth positive input end of the input stage module 101, the second end of the capacitor C2 is connected to the gate of the NMOS transistor M5, the drain of the NMOS transistor M5 is connected to the source of the NMOS transistor M3 and the source of the NMOS transistor M4, the drain of the NMOS transistor M3 is connected to the drain of the PMOS transistor M1 and forms a fourth negative output end of the input stage module 101, the drain of the NMOS transistor M4 is connected to the drain of the PMOS transistor M2 and forms a fourth positive output end of the input stage module 101, the sources of the PMOS transistor M1 and the PMOS transistor M2 are connected to a high level signal, and the source of the PMOS transistor M2 is connected to the first clock signal.

The switch module 102 comprises a PMOS tube M6, a PMOS tube M7, a PMOS tube M8 and a PMOS tube M9, wherein the drain electrode of the PMOS tube M6 and the drain electrode of the PMOS tube M9 are connected to form a first positive input end of the switch module 102, the drain electrode of the PMOS tube M7 and the drain electrode of the PMOS tube M8 are connected to form a first negative input end of the switch module 102, the grid electrode of the PMOS tube M6 and the grid electrode of the PMOS tube M7 are connected to form a first control end of the switch module 102, the grid electrode of the PMOS tube M8 and the grid electrode of the PMOS tube M9 are connected to form a second control end of the switch module 102, the source electrode of the PMOS tube M6 and the source electrode of the PMOS tube M8 are connected to form a first negative output end of the switch module 102, and the source electrode of the PMOS tube M7 and the source electrode of the PMOS tube M9 are connected to form a first positive output end of the switch module 102.

The latch module 103 includes a PMOS transistor M10, a PMOS transistor M11, a PMOS transistor M12, a PMOS transistor M13, an NMOS transistor M14, an NMOS transistor M15, an NMOS transistor M16, and an NMOS transistor M17, where the gate of the PMOS transistor M12 and the gate of the NMOS transistor M14 are commonly connected and form a second positive input terminal of the latch module 103, the gate of the PMOS transistor M13 and the gate of the NMOS transistor M17 are commonly connected and form a second negative input terminal of the latch module 103, the drain of the PMOS transistor M12, the drain of the NMOS transistor M14, the drain of the NMOS transistor M15 are commonly connected and form a second negative output terminal of the latch module 103, the drain of the NMOS transistor M13, the drain of the NMOS transistor M16, the drain of the NMOS transistor M17 and form a second positive output terminal of the latch module 103, the source of the NMOS transistor M14 and the source of the NMOS transistor M15 are commonly connected to ground, the source of the NMOS transistor M16 and the source of the NMOS transistor M17 are commonly connected to ground, the gate of the NMOS transistor M15 is connected to the gate of the PMOS transistor M10, the drain of the PMOS transistor M10 is connected to the drain of the PMOS transistor M12, and the drain of the PMOS transistor M11 is connected to the drain of the PMOS transistor M11, and the drain of the source of the PMOS transistor M11 is connected to the drain of the PMOS transistor M11.

The output stage module 104 includes a precharge module 141, a fifth switch 142, a sixth switch 143, a seventh switch 144, an eighth switch 145, a ninth switch 146, and a tenth switch 147, the first control terminal of the precharge module 141 and the control terminal of the ninth switch 146 input a fourth clock signal, the second control terminal of the precharge module 141 and the control terminal of the tenth switch 147 input a fifth clock signal, the input terminal of the precharge module 141 is connected to a high level, the first output terminal of the precharge module 141 is connected to the output terminal of the fifth switch 142 and the output terminal of the seventh switch 144, and constitutes a third positive output terminal of the output stage module 104, the second output terminal of the precharge module 141 is connected to the output terminal of the sixth switch 143 and the output terminal of the eighth switch 145, and constitutes a third negative output terminal of the output stage module 104, the control terminal of the fifth switch 142 and the control terminal of the eighth switch 145 are commonly connected to form a third negative input terminal, the control terminal of the fifth switch 143 and the control terminal of the seventh switch are commonly connected to the output terminal of the eighth switch 146, the output terminal of the eighth switch 146 is connected to the input terminal of the eighth switch 146, and the output terminal of the eighth switch 146 is connected to the input terminal of the eighth switch 146.

The fifth switch 142 is an NMOS transistor M28, the sixth switch 143 is an NMOS transistor M29, the seventh switch 144 is an NMOS transistor M30, the eighth switch 145 is an NMOS transistor M31, the ninth switch 146 is an NMOS transistor M32, the tenth switch 147 is an NMOS transistor M33, the precharge module 141 includes a PMOS transistor M18, a PMOS transistor M19, a PMOS transistor M20, a PMOS transistor M21, a PMOS transistor M22, a PMOS transistor M23, a PMOS transistor M24, a PMOS transistor M25, a PMOS transistor M26, a PMOS transistor M27, a source of the PMOS transistor M18, a source of the PMOS transistor M19, a source of the PMOS transistor M21, a source of the PMOS transistor M22, a source of the PMOS transistor M23, a common connection, a high level, a gate of the PMOS transistor M18, a gate of the PMOS transistor M22, a gate of the PMOS transistor M25, a gate of the PMOS transistor M27, a gate of the PMOS transistor M32, a first control terminal, a PMOS transistor M23, a gate of the PMOS transistor M24, a PMOS transistor M23, a drain of the PMOS transistor M21, a drain of the PMOS transistor M21, a PMOS transistor M25, a drain of the PMOS transistor M25, and a drain of the PMOS transistor M25.

The working process of the technical scheme provided by the fifth embodiment is as follows: as shown in fig. 10, when the first clock signal is in the low level state, the input stage module 101 is in the reset state, and the first amplified voltage signal VOP1 and the second amplified voltage signal VON1 outputted by the input stage module are both in the high level; the latch module 103 is in a reset state, and the first amplified voltage signal VOP3 and the second amplified voltage signal VON3 output by the latch module are both at low level; the output stage module 104 is in a reset state, and the first amplified voltage signal VOP and the second amplified voltage signal VON output by the output stage module are both at a high level. When the rising edge of the second period of the first clock signal comes, the input stage block 101 is in an amplified state, and the first amplified voltage signal VOP1 and the second amplified voltage signal VON1 are discharged at different speeds. When the second clock signal of the switch module 102 is a falling edge, the PMOS transistor M6 and the PMOS transistor M7 are turned on, the signal VOP2 output by the first positive output end of the switch module 102 is the same as the first amplified voltage signal VOP1, and the signal VON2 output by the first negative output end of the switch module 102 is the same as the second amplified voltage signal VON 1. When the third clock signal of the switch module 102 is a falling edge, the PMOS transistor M8 and the PMOS transistor M9 are turned on, the signal VOP2 output by the first positive output end of the switch module 102 is the same as the second amplified voltage signal VON1, and the signal VON2 output by the first negative output end of the switch module 102 is the same as the first amplified voltage signal VOP 1. The input of the latch module 103 compares the output VOP2 and VON2 of the switch module 102, and when the second clock signal is a rising edge, the latch module outputs comparison results VOP3 and VON3, one of which is at a high level and one of which is at a low level, and VOP3 and VON3 are finally at a high level or at a low level, depending on the relative sizes of VOP2 and VON2 at that time; when the third clock signal is at the rising edge, the latch module outputs the comparison results VOP3 and VON3, one of which is at a high level and one of which is at a low level, and VOP3 and VON3 are finally at a high level or at a low level, depending on the relative sizes of VOP2 and VON2 at that time. When the fourth clock signal and the fifth clock signal are in a low level state, the output stage module 104 switches on the PMOS transistor M18, the PMOS transistor M19, the PMOS transistor M24, the PMOS transistor M25, the PMOS transistor M20, the PMOS transistor M21, the PMOS transistor M22, the PMOS transistor M23, the PMOS transistor M26 and the PMOS transistor M27, the NMOS transistor M28, the NMOS transistor M29, the NMOS transistor M30, the NMOS transistor M31, the NMOS transistor M32 and the NMOS transistor M33, and the third positive output terminal VOP and the third negative output terminal VON of the output stage module 104 are reset to a high level; the output stage module 104 is enabled at a high level of the second clock signal and enabled at a fourth clock signal, the NMOS transistor M32 is turned on, the VOP output state is a VOP3 state, the VON output state is a VON3 state, at this time, the transistors NMOS transistor M30, NMOS transistor M31, NMOS transistor M33 are turned off, the PMOS transistor M23, the PMOS transistor M26, the PMOS transistor M19, the PMOS transistor M24 maintain the reset state, and the PMOS transistor M20 and the PMOS transistor M21 are in a latch state; when the third clock signal is enabled at a high level and the fifth clock signal is enabled, the NMOS transistor M33 is turned on, the VOP output state is a state of VON3, the VON output state is a state of VOP3, the NMOS transistor M28, the NMOS transistor M29, and the NMOS transistor M32 are turned off, the PMOS transistor M18, the PMOS transistor M25, the PMOS transistor M22, and the PMOS transistor M27 are in a state when being maintained in reset, and the PMOS transistor M20 and the PMOS transistor M21 are in a latch state.

Example six

An analog-to-digital converter according to a sixth embodiment of the present invention includes the dynamic comparator provided in the above embodiment.

The analog-to-digital converter provided in the sixth embodiment can be a chip, and is widely applied to the technical fields of communication systems, control systems, audio and video systems, test and measurement equipment, and automotive electronics.

If the comparator is unstable, the output signal may be biased or distorted, which may result in a decrease in the output accuracy of the analog converter. Therefore, the comparator with degradation resistance is of great importance for the analog converter, and can ensure the output accuracy and stability of the analog converter, and can also improve the reliability and stability of the system.

Example seven

An embodiment seven of the present invention provides an electronic device, which includes the analog-to-digital converter provided in the sixth embodiment.

The electronic equipment can be a voltage control oscillator, a data acquisition system, digital television equipment, medical equipment, measuring equipment, automobile electronic equipment and the like, and reliability and stability of the electronic equipment can be improved by adopting the degradation-resistant comparator.

The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.

Claims

1. A dynamic comparator, the dynamic comparator comprising:

2. The dynamic comparator of claim 1, wherein the control terminal of the switching module is further connected to a third clock signal, and the switching module is configured to control the first positive input terminal and the first negative input terminal to alternately communicate with the first positive output terminal and the first negative output terminal, respectively, in one-to-one correspondence, according to the second clock signal and the third clock signal, so that the first positive output terminal and the first negative output terminal switch and output the first amplified voltage signal and the second amplified voltage signal to the latch module, respectively.

3. The dynamic comparator of claim 2, wherein the first positive input is connected to the first positive output and the first negative input is connected to the first negative output when the second clock signal is enabled and the third clock signal is disabled;

when the second clock signal is invalid and the third clock signal is enabled, the first positive input terminal is connected with the first negative output terminal, and the first negative input terminal is connected with the first positive output terminal.

4. The dynamic comparator of claim 3, wherein the switch module comprises a first control switch, a second control switch, a third control switch and a fourth control switch, wherein the input end of the first control switch and the input end of the fourth control switch are commonly connected to form the first positive input end, the input end of the second control switch and the input end of the third control switch are commonly connected to form the first negative input end, the control end of the first control switch and the control end of the second control switch are both connected with a second clock signal, the control end of the third control switch and the control end of the fourth control switch are both connected with a third clock signal, the output end of the second control switch and the output end of the fourth control switch are commonly connected to form the first negative output end, the output end of the first control switch and the output end of the third control switch are commonly connected to form the first positive output end, and when the second clock signal is enabled, the first control switch and the third control switch and the fourth control switch are enabled to conduct.

5. The dynamic comparator of claim 2, wherein the second clock signal and the third clock signal are configured to alternately communicate the first positive input terminal and the first negative input terminal with the first positive output terminal and the first negative output terminal, respectively, in one-to-one correspondence for each clock cycle of the first clock signal.

6. The dynamic comparator of claim 2, wherein the dynamic comparator further comprises:

the output stage module comprises a third positive electrode input end, a third negative electrode input end, a third positive electrode output end, a third negative electrode output end and a control end, wherein the third positive electrode input end is connected with the second positive electrode output end of the latch module, the third negative electrode input end is connected with the second negative electrode output end of the latch module, the third positive electrode output end outputs a first comparison signal, the third negative electrode output end outputs a second comparison signal, and the control end is connected with a fourth clock signal and a fifth clock signal and is used for enabling the polarities of the first comparison signal and the first voltage signal to be consistent according to the fourth clock signal and the fifth clock signal and enabling the polarities of the second comparison signal and the second voltage signal to be consistent.

7. The dynamic comparator of claim 6, wherein the fourth clock signal is enabled and the fifth clock signal is disabled when the second clock signal is enabled and the third clock signal is disabled during one cycle of a first clock, the first comparison signal and the first voltage signal are the same polarity, and the second comparison signal and the second voltage signal are the same polarity; when the second clock signal is inactive and the third clock signal is enabled, the fourth clock signal is inactive and the fifth clock signal is enabled, polarities of the first comparison signal and the first voltage signal are the same, and polarities of the second comparison signal and the second voltage signal are the same.

8. The dynamic comparator of claim 6, wherein the output stage module comprises a precharge module, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, and a tenth switch;

the first control end of the precharge module and the control end of the ninth switch are input with a fourth clock signal, the second control end of the precharge module and the control end of the tenth switch are input with a fifth clock signal, the input end of the precharge module is connected with a high level, the first output end of the precharge module is connected with the output end of the fifth switch and the output end of the seventh switch and forms a third positive output end of the output stage module, the second output end of the precharge module is connected with the output end of the sixth switch and the output end of the eighth switch and forms a third negative output end of the output stage module, the control end of the fifth switch and the control end of the eighth switch are commonly connected to form a third negative input end and are connected with a fourth comparison signal, the control end of the sixth switch and the control end of the seventh switch are commonly connected to form a third positive input end and are connected with a third comparison signal, the input end of the fifth switch is connected with the output end of the eighth switch and the eighth switch is connected with the input end of the ninth switch, and the output end of the eighth switch is connected with the input end of the eighth switch is grounded.

9. The dynamic comparator of claim 6, further comprising a clock signal generation module coupled to the initial clock signal, the clock signal generation module comprising:

the input end of the reverse module is connected with the initial clock signal;

the clock input end of the first D trigger is connected with the output end of the reversing module;

the clock input end of the second D trigger is connected with the initial clock signal, and the data input end of the second D trigger is connected with the output end of the first D trigger;

the input end of the first clock signal generation module is connected with the output end of the reversing module;

the first input end of the second clock signal generation module is connected with the output end of the first D trigger, and the second input end of the second clock signal generation module is connected with the initial clock signal;

the first input end of the third clock signal generation module is connected with the output end of the first D trigger, and the second input end of the third clock signal generation module is connected with the initial clock signal;

the first input end of the fourth clock signal generation module is connected with the output end of the second D trigger, and the second input end of the fourth clock signal generation module is connected with the output end of the reversing module;

and the first input end of the fifth clock signal generating module is connected with the output end of the second D trigger, and the second input end of the fifth clock signal generating module is connected with the output end of the reversing module.

10. The dynamic comparator of claim 9, wherein the inverting module comprises an inverter G1, an inverter G2, an inverter G3; the first D trigger is a D trigger D1, the second D trigger is a D trigger D2, the first clock signal generating module is an inverter G6, the second clock signal generating module is a NAND gate G10, the third clock signal generating module comprises an inverter G5 and a NAND gate G11, the fourth clock signal generating module comprises an inverter G7 and an AND gate G9, and the fifth clock signal generating module is an AND gate G8;

the initial clock signal is connected with the input end of the inverter G1, the input end of the inverter G3, the input end of the inverter G4, the first input end of the nand gate G10, the clock input end of the D flip-flop D2 and the first input end of the nand gate G11, the output end of the inverter G4 is connected with the input end of the inverter G6, the output end of the inverter G6 outputs a first clock signal, the output end of the inverter G3 is connected with the clock input end of the D flip-flop D1, the Q output end of the D flip-flop D1 is connected with the input end of the inverter G2, the data input end of the D flip-flop D2, the input end of the D flip-flop G5 and the second input end of the nand gate G10, the output end of the nand gate G11 outputs a third clock signal, the output end of the nand gate G10 outputs a second clock signal, the output end of the D flip-flop D7 and the second input end of the D flip-flop G8, the output end of the second and the second input end of the nand gate G7 outputs a second clock signal, the output end of the second input end of the nand gate G8 and the second input end of the nand gate G10.

11. The dynamic comparator of claim 6, wherein the input stage module comprises a fourth positive input terminal, a fourth negative input terminal, a fourth positive output terminal, and a fourth negative output terminal, the fourth positive input terminal being connected to a first voltage signal, the fourth negative input terminal being connected to a second voltage signal, the fourth positive output terminal outputting a first amplified voltage signal to a first positive input terminal, the fourth negative output terminal outputting a second amplified voltage signal to a first negative input terminal, the first positive output terminal being connected to the second positive input terminal, the first negative output terminal being connected to the second negative input terminal;

the fourth positive electrode input end of the input stage module is also connected with a first voltage compensation module, the first voltage compensation module is used for carrying out voltage compensation on the first voltage signal, the first end of the first voltage compensation module is connected with the fourth positive electrode input end of the input stage module, and the second end of the first voltage compensation module is connected with the first clock signal; and/or

The fourth negative electrode input end of the input stage module is also connected with a second voltage compensation module, the second voltage compensation module is used for carrying out voltage compensation on the second voltage signal, the first end of the second voltage compensation module is connected with the fourth negative electrode input end of the input stage module, and the second end of the second voltage compensation module is connected with the first clock signal.

12. The dynamic comparator of claim 11, wherein the first voltage compensation module comprises a first compensation capacitor, a first terminal of the first compensation capacitor being connected to a fourth positive input terminal of the input stage module, a second terminal of the first compensation capacitor being connected to the first clock signal; and/or

The second voltage compensation module comprises a second compensation capacitor, a first end of the second compensation capacitor is connected with a fourth negative input end of the input stage module, and a second end of the second compensation capacitor is connected with the first clock signal.

13. The dynamic comparator of claim 12, wherein the input stage module comprises a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, a capacitor C1, and a capacitor C2, wherein a gate of the NMOS transistor M3 is commonly connected to a first end of the capacitor C1 and forms a fourth negative input terminal of the input stage module, a second end of the capacitor C1 is connected to a gate of the NMOS transistor M5 and forms a control terminal of the input stage module and is connected to a first clock signal, a gate of the NMOS transistor M4 is commonly connected to a first end of the capacitor C2 and forms a fourth positive input terminal of the input stage module, a second end of the capacitor C2 is connected to a gate of the NMOS transistor M5, a drain of the NMOS transistor M5 is connected to a source of the NMOS transistor M3 and a source of the capacitor C4, a drain of the NMOS transistor M3 is connected to a drain of the NMOS transistor M1 and forms a control terminal of the input stage module and is connected to a first clock signal, and a drain of the PMOS transistor M2 is connected to a drain of the NMOS transistor M4 and forms a fourth positive input terminal of the input stage module.

14. An analog-to-digital converter, characterized in that it comprises a dynamic comparator according to any one of claims 1 to 13.

15. An electronic device comprising the analog-to-digital converter of claim 14.