CN216288419U

CN216288419U - Chip packaging structure

Info

Publication number: CN216288419U
Application number: CN202121697169.9U
Authority: CN
Inventors: 霍佳仁; 宋关强; 刘德波
Original assignee: Sky Chip Interconnection Technology Co Ltd
Current assignee: Sky Chip Interconnection Technology Co Ltd
Priority date: 2021-07-23
Filing date: 2021-07-23
Publication date: 2022-04-12
Anticipated expiration: 2031-07-23

Abstract

The application provides a chip packaging structure. The chip packaging structure comprises a substrate, an electronic component and a first dielectric layer; the electronic components are attached to the surface of the substrate, and the front surface of at least one electronic component faces the substrate; the first dielectric layer is arranged on the substrate and at least wraps the electronic component. The chip packaging structure shortens an electric path and a heat dissipation path, and has low impedance and good heat dissipation effect.

Description

Chip packaging structure

Technical Field

The utility model relates to the technical field of semiconductor packaging, in particular to a chip packaging structure.

Background

In the information society of today, the dependence of human beings on electronic products is increasing day by day, and the electronic products are developing vigorously in the direction of high integration, miniaturization and miniaturization.

Currently, in order to achieve high integration, miniaturization and miniaturization of products, a Package In Package (PiP), a Package on Package (PoP) or a System In Package (SiP) is generally adopted to Package each component; however, the chip package structure of the prior art has poor heat dissipation and current capacity.

SUMMERY OF THE UTILITY MODEL

The application provides a chip packaging structure, this chip packaging structure can solve current chip packaging structure and be difficult to satisfy the problem of little volume, multi-chip connection encapsulation, and has shortened electric route and heat dissipation path, and low impedance, radiating effect are better.

In order to solve the technical problem, the application adopts a technical scheme that: a chip package structure is provided. The chip packaging structure comprises a substrate, an electronic component and a first dielectric layer; the electronic components are attached to the surface of the substrate, and the front surface of at least one electronic component faces the substrate; the first dielectric layer is arranged on the substrate and at least wraps the electronic component.

Wherein the front surfaces of all the electronic components face the substrate; the first dielectric layer at least wraps all the electronic components.

The electronic component is attached to the surface of one side, away from the substrate, of the first conducting layer; the first dielectric layer wraps the electronic component and the first conducting layer.

The first circuit layer is formed on the surface of one side, away from the substrate, of the first dielectric layer and is connected with the electronic component.

The first dielectric layer is provided with conductive holes, the conductive holes penetrate through the surfaces of the electronic component and the substrate, and the first circuit layer is communicated with the electronic component through the conductive holes.

The second conductive layer is arranged between the first dielectric layer and the first circuit layer.

The second dielectric layer is arranged on the surface of one side, away from the first dielectric layer, of the first circuit layer and wraps the first circuit layer.

The second dielectric layer covers the surface of one side of the first circuit layer, which is far away from the first dielectric layer, and is in contact with the partial surface of one side of the first dielectric layer, which is far away from the substrate, so as to wrap the side surface of the first circuit layer.

The electronic component is characterized by further comprising a second circuit layer, wherein the second circuit layer is formed on the surface of one side, away from the electronic component, of the substrate.

The substrate is provided with a through hole, and the part of the first dielectric layer is embedded into the through hole and is flush with the surface of one side of the substrate, which is far away from the electronic component.

According to the chip packaging structure, the substrate is arranged, the electronic components are pasted on the surface of the substrate, and the front face of at least one electronic component faces the substrate, so that an electric path and a heat dissipation path are shortened, and the chip packaging structure has excellent low-resistance characteristics and a heat dissipation effect; meanwhile, the first dielectric layer is arranged on the substrate, and the electronic component is at least wrapped by the first dielectric layer, so that the electronic component is packaged and protected, and further the miniaturization and the lightness of the chip packaging structure are realized.

Drawings

Fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a substrate according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a chip package structure according to another embodiment of the present application;

fig. 4 is a flowchart of a method for manufacturing a chip package structure according to an embodiment of the present disclosure;

FIG. 5 is a sub-flowchart of step S11 according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a substrate according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a product after being processed in step S113 according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a product after being processed in step S114 according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a product after being processed in step S1 according to an embodiment of the present application;

FIG. 10 is a sub-flowchart of step S12 according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a product after being processed in step S121 according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a product after being processed in step S122 according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of a product after being processed in step S123 according to an embodiment of the present application;

fig. 14 is a schematic structural diagram illustrating a third conductive layer laminated on the first dielectric layer and the substrate, respectively, according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a product after being processed in step S124 according to an embodiment of the present application;

fig. 16 is a schematic structural diagram of a product after being processed in step S125 according to an embodiment of the present application;

fig. 17 is a sub-flowchart of step S12 according to another embodiment of the present application;

fig. 18 is a schematic structural diagram of a product after being processed in step S212 according to an embodiment of the present application;

fig. 19 is a schematic structural diagram illustrating a third conductive layer laminated on the first dielectric layer and the substrate, respectively, according to another embodiment of the present disclosure;

fig. 20 is a schematic structural diagram of a product after being processed in step S213 according to an embodiment of the present application;

fig. 21 is a schematic structural diagram of a product after being processed in step S214 according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first", "second" and "third" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any indication of the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. All directional indications (such as up, down, left, right, front, and rear … …) in the embodiments of the present application are only used to explain the relative positional relationship between the components, the movement, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indication is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The present application will be described in detail with reference to the accompanying drawings and examples.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the present application; in the present embodiment, a chip package structure 10 is provided, where the chip package structure 10 includes a substrate 11, at least one electronic component 12, and a first dielectric layer 131.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a substrate according to an embodiment of the present disclosure; the substrate 11 may be a metal substrate, such as a copper substrate or an aluminum substrate. And the substrate 11 may have a plurality of through holes 111.

The number of the electronic components 12 may be multiple, and a plurality of electronic components 12 are attached to the surface of the substrate 11, so as to realize interconnection among the electronic components 12 through the substrate 11. Specifically, compared with a scheme that the front surface of at least one electronic component 12 of the plurality of electronic components 12 faces the substrate 11 and is attached to the surface of the substrate 11, the front surface of at least one electronic component 12 faces the side away from the substrate 11, the electric path and the heat dissipation path can be effectively shortened, and the low-resistance characteristic and the heat dissipation effect are excellent. In a specific embodiment, the front surfaces of some of the electronic components 12 on the substrate 11 face the substrate 11, and the front surfaces of the other electronic components 12 face a direction away from the substrate 11, so as to improve the heat dissipation effect while facilitating mounting; while improving the flexibility of the interconnection. In another embodiment, the front surfaces of all the electronic components 12 on the substrate 11 face the substrate 11, so as to effectively improve the heat dissipation effect of the chip package structure 10 on the basis of ensuring the interconnection among the electronic components 12. The chip packaging structure 10 can simultaneously realize face-down and/or face-down packaging of the electronic component 12, and has flexible interconnection characteristics.

Specifically, referring to fig. 1, the electronic components 12 are attached to the first surface of the substrate 11, and compared with a scheme in which the electronic components 12 are attached to two opposite surfaces of the substrate 11, the scheme is convenient for attaching the electronic components 12 to the substrate 11, and for integrally packaging the electronic components 12, and can save packaging materials and reduce production cost; meanwhile, the chip package structure 10 is favorable for development toward lightness and thinness.

The electronic component 12 includes one or any combination of a resistor, an inductor, a capacitor, a chip, and a bare chip of a power supply. Of course, in other embodiments, the electronic component 12 may further include a diode and a transistor, which is not limited in this embodiment.

The first dielectric layer 131 is disposed on a side surface of the electronic component 12 away from the substrate 11 to at least wrap all the electronic components 12, so as to protect the electronic components 12 mounted on the substrate 11. In a specific embodiment, a portion of the first dielectric layer 131 penetrates through the through hole 111 and is flush with a surface of the substrate 11 facing away from the electronic component 12, so as to increase the stress of the substrate 11; the rest part covers the surface of the substrate 11 and wraps the surface of one side of the electronic component 12, which is far away from the substrate 11, and the side of the electronic component 12.

Referring to fig. 1, in an embodiment, the chip package structure 10 further includes a first conductive layer 14, the first conductive layer 14 is disposed on a side surface of the substrate 11, and the electronic component 12 is specifically attached to a side surface of the first conductive layer 14 facing away from the substrate 11, so as to attach the electronic component 12 and achieve electrical connection between the electronic component 12 and the substrate 11. In this embodiment, the first dielectric layer 131 wraps the electronic component 12 and the side of the first conductive layer 14. The first conductive layer 14 may be a conductive adhesive.

Specifically, the first conductive layer 14 is disposed on a portion of the surface of the substrate 11 for mounting the electronic component 12; and the surface area of the first conductive layer 14 can be consistent with the surface area of the electronic component 12 in contact with the first conductive layer 14, so that the electronic component 12 and the substrate 11 are interconnected, conductive materials are saved, and the production cost is reduced.

Further, referring to fig. 1, the chip package structure 10 further includes a first circuit layer 15, wherein the first circuit layer 15 is formed on a surface of the first dielectric layer 131 facing away from the substrate 11. In a specific embodiment, the first dielectric layer 131 is formed with a conductive hole 133, the conductive hole 133 penetrates through the surfaces of the electronic component 12 and the substrate 11, so that a portion of the conductive hole 133 is connected to the electronic component 12, and the first circuit layer 15 is specifically connected to the electronic component 12 through the conductive hole 133. The first circuit layer 15 and the conductive via 133 form a step-shaped interconnection, so that double-sided heat dissipation of the chip package structure 10 can be achieved. Specifically, a conductive layer is formed in the conductive hole 133, and the conductive layer may be a copper layer. In a specific implementation process, the conductive hole 133 may be filled with a conductive layer by a plating hole filling or a copper deposition process to form the conductive hole 133, so as to electrically connect the first circuit layer 15 and the electronic component 12. Compared with a scheme of adopting lead connection, the copper interconnection and wiring are adopted, and the effects of miniaturization and light weight and thinness can be achieved.

In an embodiment, the chip package structure 10 further includes a second conductive layer 18, the second conductive layer 18 is disposed on a side surface of the first dielectric layer 131 facing away from the substrate 11 and located between the first dielectric layer 131 and the first circuit layer 15, and the first circuit layer 15 is specifically stacked on the first dielectric layer 131 through the second conductive layer 18 to improve adhesion between the first dielectric layer and the first circuit layer 131.

In an embodiment, the chip package structure 10 may further include a second dielectric layer 132, where the second dielectric layer 132 covers a surface of the first circuit layer 15 facing away from the first dielectric layer 131 and contacts a portion of a surface of the first dielectric layer 131 facing away from the substrate 11 to wrap a side surface of the first circuit layer 15, so as to protect the first circuit layer 15 and the second conductive layer 18. By providing the first dielectric layer 131 and the second dielectric layer 132, a high packaging effect of the chip packaging structure 10 can be achieved.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a chip package structure according to another embodiment of the present application; in an embodiment, the chip package structure 10 further includes a second circuit layer 16, and the second circuit layer 16 is specifically formed on a side surface of the substrate 11 facing away from the first circuit layer 15. Specifically, the thickness of the second circuit layer 16 may be greater than that of the first circuit layer 15, and the second circuit layer 16 may wrap a portion of the first dielectric layer 131 exposed on a side surface of the substrate 11 away from the first circuit layer 15 through the through hole 111; compared with the scheme that the first dielectric layer 131 is directly exposed on the surface of one side of the substrate 11 departing from the first circuit layer 15 through the through hole 111, the product stress is reduced, and the product reliability is improved.

In the chip package structure 10 provided by this embodiment, the substrate 11 is disposed, the electronic component 12 is mounted on the surface of the substrate 11, and the front surface of the at least one electronic component 12 faces the substrate 11, so as to shorten the electrical path and the heat dissipation path, so that the chip package structure 10 has excellent low resistance and heat dissipation effects; meanwhile, the first dielectric layer 131 is arranged on the surface of one side, away from the substrate 11, of the electronic component 12, so that the electronic component 12 is at least wrapped by the first dielectric layer 131, the electronic component 12 is packaged and protected, and the chip packaging structure 10 is further miniaturized and light and thin; meanwhile, the structure of the chip packaging structure 10 is simple.

The chip package structure 10 provided in this embodiment can be specifically manufactured by the following method for manufacturing a chip package structure.

Referring to fig. 4, fig. 4 is a flowchart illustrating a method for manufacturing a chip package structure according to an embodiment of the disclosure; in this embodiment, a method for manufacturing a chip package structure is provided, where the method includes:

step S11: and an electronic component is pasted on the surface of the substrate.

In a specific embodiment, referring to fig. 5, fig. 5 is a sub-flowchart of step S11 provided in an embodiment of the present application. Step S11 specifically includes:

step S111: a substrate is provided.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a substrate according to an embodiment of the present disclosure; the specific structure of the substrate 11 can be seen in fig. 6. The substrate 11 may be a copper substrate.

Step S112: and carrying out patterning treatment on the substrate to form a plurality of through holes on the substrate.

The product structure after processing in step S112 can be specifically seen in fig. 2.

Step S113: a releasable material is provided on one side surface of the substrate.

Specifically, the structure of the product after being processed in step S113 can be seen in fig. 7, and fig. 7 is a schematic view of the structure of the product after being processed in step S113 according to an embodiment of the present application; specifically, the detachable material 17 is provided on the second surface of the substrate 11. Wherein the detachable material 17 may be a plastic film or a glue layer. Wherein, by providing the detachable material 17 on the second surface of the substrate 11, the product stress can be reduced, reducing the probability of warpage problems during post-processing.

Step S114: a first conductive layer is disposed on a first surface of a substrate.

Wherein the first surface and the second surface of the substrate 11 are disposed opposite to each other. Specifically, the product structure processed in step S114 can be seen in fig. 8, and fig. 8 is a schematic view of the product structure processed in step S114 according to an embodiment of the present disclosure. Specifically, the first conductive layer 14 may be disposed at a plurality of preset positions on the first surface of the substrate 11, and the first conductive layer 14 may be a conductive adhesive, so as to attach the electronic component 12 to the substrate 11. The preset positions on the substrate 11 specifically refer to positions where the substrate 11 is used for mounting the electronic component 12.

Step S115: and an electronic component is pasted on the surface of one side of the first conducting layer, which is far away from the substrate.

Specifically, the structure of the product after the processing in step S115 can be seen in fig. 9, and fig. 9 is a schematic view of the structure of the product after the processing in step S115 according to an embodiment of the present application. Specifically, at least a part of the electronic component 12 is disposed with its front surface facing the substrate 11 to shorten the electrical path and the heat dissipation path, thereby improving the heat dissipation effect. In a specific embodiment, the front surface of a part of the electronic components 12 may be disposed toward the substrate 11, and the front surface of the other part of the electronic components 12 may be disposed toward the surface away from the substrate 11; in another embodiment, the front surfaces of all the electronic components 12 may be disposed toward the substrate 11, so as to effectively improve the heat dissipation capability.

Step S12: and manufacturing a dielectric layer on the surface of the substrate to form a package body.

In an implementation manner, referring to fig. 10, fig. 10 is a sub-flowchart of step S12 provided in an embodiment of the present application; step S12 specifically includes:

step S121: and sequentially manufacturing a first dielectric layer and a second conductive layer on the surface of one side of the substrate, which is far away from the separable material.

Specifically, the structure of the product after the processing in step S121 can be seen in fig. 11, and fig. 11 is a schematic view of the structure of the product after the processing in step S121 according to an embodiment of the present application. Wherein the first dielectric layer 131 penetrates through the through hole 111 of the substrate 11 and contacts the separable material 17; and the first dielectric layer 131 covers the first surface of the substrate 11 and wraps the electronic component 12 and the side surfaces of the first conductive layer 14 to protect the electronic component 12. The first dielectric layer 131 may be a prepreg. The second conductive layer 18 is located on a side surface of the first dielectric layer 131 facing away from the substrate 11, and the second conductive layer 18 may be a copper layer.

Step S122: the separable material is removed to expose the second surface of the substrate and a portion of the first dielectric layer.

Specifically, the product structure processed in step S122 can be seen in fig. 12, and fig. 12 is a schematic view of the product structure processed in step S122 according to an embodiment of the present disclosure.

Step S123: a plurality of conductive holes are formed through the first dielectric layer, and a portion of the substrate and/or a portion of the electronic component are exposed through the conductive holes.

Specifically, the structure of the product after the processing in step S123 can be seen in fig. 13, and fig. 13 is a schematic view of the structure of the product after the processing in step S123 according to an embodiment of the present application. Through holes can be formed in the first dielectric layer 131 and the second conductive layer 18 by laser physical etching or chemical etching to expose a portion of the first surface of the substrate 11 and a surface of the electronic component 12 away from the substrate 11.

Step S124: and preparing a first circuit layer on the surface of one side of the first dielectric layer, which is far away from the substrate, and forming a second circuit layer on the surface of one side of the substrate, which is far away from the first circuit layer.

Referring to fig. 14 and fig. 15, in which fig. 14 is a schematic structural diagram illustrating a third conductive layer laminated on the first dielectric layer and the substrate respectively according to an embodiment of the present disclosure; fig. 15 is a schematic structural diagram of a product after being processed in step S124 according to an embodiment of the present application; specifically, the structure of the product after processing in step S124 can be seen in fig. 15. Specifically, the step includes laminating third conductive layers 19a/19b on a surface of the first dielectric layer 131 facing away from the substrate 11 and a surface of the substrate 11 facing away from the electronic component 12 (see fig. 14); the third conductive layer 19a laminated on the side of the first dielectric layer 131 facing away from the substrate 11 penetrates through the conductive hole 133, so as to interconnect the third conductive layer 19a with the electronic component 12 and/or the substrate 11; then, the laminated third conductive layers 19a/19b are patterned by physical or chemical etching to expose a portion of the first dielectric layer 131 to form the first wiring layer 15 and the second wiring layer 16, respectively (see fig. 15), thereby completing the package logic. The first wiring layer 15 is in communication with the electronic component 12 through the conductive hole 133. Specifically, the first circuit layer 15 and the second circuit layer 16 are formed on the first surface and the second surface of the substrate 11, so that double-sided heat dissipation can be achieved, product stress can be reduced, and product reliability can be improved.

Step S125: and forming a second dielectric layer on the surface of one side of the first circuit layer, which is far away from the first dielectric layer, so as to package the first circuit layer.

Specifically, the structure of the product after the processing in step S125 can be seen in fig. 16, and fig. 16 is a schematic view of the structure of the product after the processing in step S125 according to an embodiment of the present disclosure. Specifically, the second dielectric layer 132 is formed on the side and the surface of the first circuit layer 15, the side of the second conductive layer 18 and the exposed first dielectric layer 131 to wrap at least the side and the surface of the first circuit layer 15, the side of the second conductive layer 18 and the exposed first dielectric layer 131, thereby realizing the packaging of the whole product.

Of course, in other embodiments, the second conductive layer 18 may not be formed, and the application is not limited thereto. It is understood that, in this embodiment, the through-holes 111 penetrate only the upper and lower surfaces of the first dielectric layer 131.

In another implementation, referring to fig. 17, fig. 17 is a sub-flowchart of step S12 provided in another embodiment of the present application; step S12 specifically includes:

step S211: and sequentially manufacturing a first dielectric layer and a second conductive layer on the surface of one side of the substrate, which is far away from the separable material.

Specifically, the specific implementation process of step S211 may refer to the specific implementation process of step S121 in the foregoing embodiment, and the same or similar technical effects may be achieved, and specifically refer to the foregoing text description, which is not repeated herein.

Step S212: a plurality of conductive holes are formed through the first dielectric layer, and a portion of the substrate and/or a portion of the electronic component are exposed through the conductive holes.

Fig. 18 shows a structure of the product after being processed in step S212, and fig. 18 is a schematic view of the structure of the product after being processed in step S212 according to an embodiment of the present application. Specifically, the specific implementation process of step S212 may refer to the specific implementation process of step S123 in the foregoing embodiment, and may achieve the same or similar technical effects, and specifically refer to the foregoing text description, which is not repeated herein.

Step S213: and preparing a first circuit layer on the surface of one side of the first dielectric layer, which is far away from the substrate.

Referring to fig. 19 and 20, fig. 19 is a schematic structural diagram illustrating a third conductive layer laminated on the first dielectric layer and the substrate respectively according to another embodiment of the present disclosure; fig. 20 is a schematic structural diagram of a product after being processed in step S213 according to an embodiment of the present application; specifically, the structure of the product after the processing of step S213 can be seen in fig. 20. This step specifically includes surface lamination of a third conductive layer 19a (see fig. 19) on the side of the first dielectric layer 131 facing away from the substrate 11; wherein, the third conductive layer 19a laminated on the side of the first dielectric layer 131 facing away from the substrate 11 penetrates through the conductive hole 133 to interconnect the metal layer with the electronic component 12 and/or the substrate 11; then, the laminated third conductive layer 19a is patterned by physical or chemical etching to expose a portion of the first dielectric layer 131 to form the first wiring layer 15, thereby completing the package logic.

Step S214: and forming a second dielectric layer on the surface of one side of the first circuit layer, which is far away from the first dielectric layer, so as to package the first circuit layer.

Fig. 21 shows a structure of the product after the processing in step S214, and fig. 21 is a schematic diagram of the structure of the product after the processing in step S214 according to an embodiment of the present application. Specifically, the specific implementation process of step S214 can be referred to the specific implementation process of step S125 in the foregoing embodiments, and the same or similar technical effects can be achieved, and specifically refer to the foregoing text description, which is not repeated herein.

Step S215: the separable material is removed to expose the second surface of the substrate and a portion of the first dielectric layer.

The structure of the product after processing in step S215 can be specifically seen in fig. 1.

Of course, in this embodiment, the second conductive layer 18 may not be prepared, and the application is not limited thereto.

Step S13: and cutting the packaging body to form a plurality of chip packaging structures.

Specifically, the structure of the product after the processing of step S13 can be seen in fig. 1 or fig. 3; in the specific implementation process, after the packaged package body is cut and tested, a plurality of chip package structures 10 are formed.

The method for manufacturing a chip package structure provided in this embodiment may be applied to the Field of manufacturing Metal-Oxide-Semiconductor Field Effect transistors (mosfets), which are abbreviated as Mosfet, Insulated Gate Bipolar Transistors (IGBTs), power modules, and electronic components 12 embedded in circuit boards. The preparation method can be completely compatible with circuit board equipment and processes, can realize double-sided heat dissipation, and has a high-efficiency packaging effect.

According to the method, the electronic components 12 are pasted on the surface of the substrate 11, and the front surface of at least one electronic component 12 faces the substrate 11, so that an electric path and a heat dissipation path are shortened, and the prepared chip packaging structure 10 has excellent low-resistance characteristics and a heat dissipation effect; meanwhile, a dielectric layer is manufactured on the surface of the substrate 11 to form a packaging body, and the dielectric layer at least wraps the electronic component 12, so that the electronic component 12 is protected, and the effects of miniaturization and lightness are achieved; in addition, by adopting the separable material 17 in the preparation process, the stress of the product is greatly reduced, and the probability of the product warping is reduced.

The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.

Claims

1. A chip package structure, comprising:

a substrate;

the electronic components are attached to the surface of the substrate, and the front surface of at least one electronic component faces the substrate;

the first dielectric layer is arranged on the substrate and at least wraps the electronic component.

2. The chip package structure according to claim 1, wherein the front surfaces of all the electronic components face the substrate; the first dielectric layer at least wraps all the electronic components.

3. The chip packaging structure according to claim 1, further comprising a first conductive layer disposed on a side surface of the substrate, wherein the electronic component is attached to a side surface of the first conductive layer facing away from the substrate; the first dielectric layer wraps the electronic component and the first conducting layer.

4. The chip package structure according to claim 1, further comprising a first circuit layer formed on a side surface of the first dielectric layer facing away from the substrate and connected to the electronic component.

5. The chip package structure according to claim 4, wherein the first dielectric layer has a conductive hole formed therein, the conductive hole penetrating the surfaces of the electronic component and the substrate, and the first circuit layer is connected to the electronic component through the conductive hole.

6. The chip package structure according to claim 4, further comprising a second conductive layer disposed between the first dielectric layer and the first circuit layer.

7. The chip package structure according to claim 4, further comprising a second dielectric layer disposed on a side surface of the first circuit layer facing away from the first dielectric layer and covering the first circuit layer.

8. The chip package structure according to claim 7, wherein the second dielectric layer covers a surface of the first circuit layer on a side facing away from the first dielectric layer, and contacts a portion of a surface of the first dielectric layer on a side facing away from the substrate to wrap the side of the first circuit layer.

9. The chip package structure according to claim 1, further comprising a second circuit layer formed on a surface of the substrate facing away from the electronic component.

10. The chip package structure according to claim 1, wherein the substrate has a through hole formed therein, and a portion of the first dielectric layer is embedded in the through hole and flush with a surface of the substrate facing away from the electronic component.