CN214313180U - Chip packaging body and electronic device - Google Patents

Chip packaging body and electronic device Download PDF

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Publication number
CN214313180U
CN214313180U CN202022151139.XU CN202022151139U CN214313180U CN 214313180 U CN214313180 U CN 214313180U CN 202022151139 U CN202022151139 U CN 202022151139U CN 214313180 U CN214313180 U CN 214313180U
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Prior art keywords
chip
metal substrate
insulating layer
chip package
layer
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CN202022151139.XU
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Chinese (zh)
Inventor
霍佳仁
宋关强
江京
刘建辉
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Sky Chip Interconnection Technology Co Ltd
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Sky Chip Interconnection Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

The application discloses chip package and electron device, wherein, this chip package includes: the patterning metal substrate plate, wherein the metal substrate plate is provided with a groove, and the depth of the groove is smaller than the thickness of the metal substrate plate; the chip is arranged in the groove; a first insulating layer covering the chip and the metal substrate board, wherein a through hole is provided in the first insulating layer to expose a portion of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip package in this application can realize the two-sided heat dissipation of chip, and the structure is comparatively simple, and electric route and heat dissipation path are short, have excellent low resistance characteristic and radiating effect, can realize the miniaturization and the frivolousization of chip package.

Description

Chip packaging body and electronic device
Technical Field
The present disclosure relates to chip packaging technologies, and particularly to a chip package and an electronic device.
Background
In recent years, with the application of Mosfet (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as Mosfet) and IGBT (Insulated Gate Bipolar Transistor) power modules to almost all power industry products, corresponding power devices are steadily developing in the direction of high performance, high speed, small volume and multi-chip connection packaging.
However, conventional wire bonding and double-sided copper interconnect processes and process methods have been increasingly difficult to meet the requirements of high performance, fast speed, small volume, multi-chip connection packaging and modularization of power devices. The power semiconductor packaging process needs to be developed towards a more excellent packaging mode of a PLFO (sheet level Fan out) process.
SUMMERY OF THE UTILITY MODEL
The application provides a chip package and an electronic device, which aim to solve the problem that the chip package in the prior art cannot realize the technical effects of miniaturization, lightness and thinness and excellent electrical and heat dissipation characteristics.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a chip package, wherein the chip package includes: the patterning metal substrate plate is provided with a groove, and the depth of the groove is smaller than the thickness of the metal substrate plate; the chip is arranged in the groove; a first insulating layer covering the chip and the metal substrate board, wherein a through hole is provided in the first insulating layer to expose a portion of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer.
And a patterned second conductive layer is arranged between the overlapped parts of the first insulating layer and the first conductive layer, and the chip is connected to the second conductive layer and the metal substrate board through the first conductive layer.
And a third conducting layer is also arranged between the overlapped part of the metal substrate plate and the chip, and the chip is attached to the metal substrate plate through the third conducting layer.
The chip packaging body further comprises a conductive metal layer, and the conductive metal layer is arranged on the surface, far away from the first insulating layer, of the metal substrate board.
The chip packaging body further comprises a second insulating layer, and the second insulating layer covers the first conducting layer and the first insulating layer which is partially exposed.
Wherein the thermal conductivity of the second insulating layer is greater than the thermal conductivity of the first insulating layer.
Wherein, the bottom area of the chip is smaller than that of the groove.
Wherein the surface area of the side of the through hole facing the metal base plate is smaller than the surface area of the side far away from the metal base plate.
In order to solve the above technical problem, the present application adopts another technical solution: there is provided an electronic device, wherein the electronic device comprises a chip package as defined in any one of the above.
The beneficial effect of this application is: unlike the case of the prior art, the chip package in the present application includes: the patterning metal substrate plate, wherein the metal substrate plate is provided with a groove, and the depth of the groove is smaller than the thickness of the metal substrate plate; the chip is arranged in the groove; a first insulating layer covering the chip and the metal substrate board, wherein a through hole is provided in the first insulating layer to expose a portion of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip in the chip package of this application can dispel the heat through the metal substrate board of patterning to and set up the patterned conducting layer that has bigger heat radiating area in the insulating layer through-hole, thereby make this chip can realize two-sided heat dissipation, and make corresponding chip package's structure simpler, electric route and heat dissipation path are shorter, thereby have excellent low resistance characteristic and radiating effect, and can realize chip package's miniaturization and frivolousization.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
fig. 1 is a schematic structural diagram of a chip package according to a first embodiment of the present application;
FIG. 2 is a schematic structural diagram of a second embodiment of a chip package according to the present application;
FIG. 3 is a schematic structural diagram of a third embodiment of a chip package according to the present application;
FIG. 4 is a schematic structural diagram of a fourth embodiment of a chip package according to the present application;
fig. 5 is a schematic structural diagram of a fifth embodiment of the chip package of the present application;
fig. 6 is a schematic structural diagram of a sixth embodiment of a chip package according to the present application;
fig. 7 is a schematic structural diagram of an embodiment of an electronic device according to the present application.
Detailed Description
In order to make the technical problems solved, the technical solutions adopted, and the technical effects achieved by the present application clearer, the technical solutions of the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip package according to a first embodiment of the present application.
In the present embodiment, the chip package includes a patterned metal base material plate 10, a chip 20, a first insulating layer 30, and a patterned first conductive layer 40. Wherein the metal substrate plate 10 is provided with a groove, and the depth of the groove is smaller than the thickness of the metal substrate plate 10, it can be understood that the depth of the groove can be one of a plurality of possible settings, such as half or one third or one fourth of the thickness of the metal substrate plate 10. The chip 20 is disposed in the groove, the first insulating layer 30 covers the chip 20 and the metal substrate 10, and a through hole is disposed in the first insulating layer 30 to expose a portion of the metal substrate 10 and the chip 20, and further, a first conductive layer 40 is disposed in the through hole and on the first insulating layer 30 to enable the chip 20 to be electrically connected to the metal substrate 10 through the first conductive layer 40 and finally form a pin of the chip package, so that the chip package has a short electrical path and a short heat dissipation path, and has excellent low resistance and heat dissipation effects.
The number of the through holes in the first insulating layer 30 includes at least two, at least one through hole is disposed above the chip 20, at least another through hole is correspondingly disposed on the metal substrate 10, and the at least two through holes are electrically connected to each other by the first conductive layer 40 covering the inside of each through hole. And a portion of the structure corresponding to the metal base plate 10 under the at least two through holes may serve as a package pin of the chip package to electrically connect with an external device or other chips.
The patterning of the metal substrate 10 and the first conductive layer 40 is correspondingly configured to be suitable for the logic circuit to be implemented by the chip 20, and different chip pins correspond to different patterned electrical paths, and the patterning can be performed by chemical etching or ion etching.
Alternatively, the material of the metal substrate 10 may be one of copper, aluminum, gold, silver and their alloys or metal-filled organics, the material used for the first insulating layer 30 may be one of silicon oxide, silicon nitride, silicon oxynitride-filled organic insulator, circuit board material, and ink, and the material of the first conductive layer 40 is selected from one of copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organics, so that the chip 20 in the chip package can realize double-sided heat dissipation through the metal substrate 10 and the first conductive layer 40 in the through hole, thereby having more excellent heat dissipation characteristics.
Alternatively, the bottom area of the chip 20 may be smaller than the bottom area of the groove provided on the metal substrate 10 for placing the chip 20, and in other embodiments, the bottom area of the chip 20 may also be equal to the bottom area of the groove, which is not limited in this application.
Alternatively, the surface area of the through hole provided in the first insulating layer 30 on the side facing the metal base plate 10 may be set to be smaller than the surface area on the side away from the metal base plate 10, that is, the bottom areas of the two sides of the through hole may be set to be different, while in other embodiments, the bottom areas of the two sides of the through hole may also be set to be the same, and the through hole may also penetrate through the metal base plate 10, which is not limited in this application.
Alternatively, the edge portions of the first insulating layer 30 corresponding to the respective through holes may be inclined edges having at least two different inclination angles, or may be arranged in any reasonable structural pattern such as an arc-shaped curved surface, a wavy curved surface, and the like.
Unlike the case of the prior art, the chip package in the present application includes: the patterning metal substrate plate, wherein the metal substrate plate is provided with a groove, and the depth of the groove is smaller than the thickness of the metal substrate plate; the chip is arranged in the groove; a first insulating layer covering the chip and the metal substrate board, wherein a through hole is provided in the first insulating layer to expose a portion of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip in the chip package of this application can dispel the heat through the metal substrate board of patterning to and set up the patterned conducting layer that has bigger heat radiating area in the insulating layer through-hole, thereby make this chip can realize two-sided heat dissipation, and make corresponding chip package's structure simpler, electric route and heat dissipation path are shorter, thereby have excellent low resistance characteristic and radiating effect, and can realize chip package's miniaturization and frivolousization.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a chip package according to a second embodiment of the present application. The present embodiment is different from the first embodiment of the chip package provided in the present application in fig. 1 in that the chip package further includes a patterned second conductive layer 50, wherein the second conductive layer 50 is disposed between the overlapping portions of the first insulating layer 30 and the first conductive layer 40.
In the present embodiment, the second conductive layer 50 is disposed on the portion of the first insulating layer 30 not opened with the through hole, and the chip 20 is connected to the second conductive layer 50 through the first conductive layer 40 and finally connected to the metal substrate 10.
The material used for the second conductive layer 50 is also selected from one of copper, aluminum, gold, silver, tin, lead, and their alloys or metal-filled organics, which is not limited in this application.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a chip package according to a third embodiment of the present application. The present embodiment is different from the first embodiment of the chip package provided in fig. 1 of the present application in that the chip package further includes a third conductive layer 60, wherein the third conductive layer 60 is disposed between the portion where the metal substrate plate 10 and the chip 20 overlap.
In the present embodiment, the metal substrate 10 is first provided with the third conductive layer 60 in the groove, and the chip 20 is correspondingly provided on the third conductive layer 60, wherein the chip 20 can be tightly attached to the metal substrate 10 through the third conductive layer 60.
Alternatively, the third conductive layer 60 may be a layer of conductive adhesive with adhesive property, i.e. an adhesive with certain conductivity after being cured or dried, such as one of silver-based conductive adhesive, gold-based conductive adhesive, copper-based conductive adhesive and carbon-based conductive adhesive, or adhesive alloy, such as one of copper, aluminum, gold, silver and their alloy or metal-filled organic matter, wherein the chip 20 and the metal substrate 10 can be reliably connected together through the third conductive layer 60 and an effective conductive path is formed.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a chip package according to a fourth embodiment of the present application. This embodiment differs from the first embodiment of the chip package provided in fig. 1 of the present application in that the chip package further comprises a conductive metal layer 70, wherein the conductive metal layer 70 is disposed on the surface of the metal substrate board 10 away from the first insulating layer 30, i.e. the conductive metal layer 70 is disposed on the surface of the metal substrate board 10 on the other side where the chip 20 is disposed.
In the present embodiment, the conductive metal layer 70 is made of the same material as the metal substrate 10, and is selected from one of copper, aluminum, gold, silver and their alloys or metal-filled organic substances, which is a thickened and stacked arrangement of the metal substrate 10 to ensure that the finally formed patterned metal substrate 10, i.e. the corresponding leads of the chip package, have more reliable strength and are not easily bent or broken.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a chip package according to a fifth embodiment of the present application. The present embodiment is different from the first embodiment of the chip package provided in fig. 1 of the present application in that the chip package further includes a second insulating layer 80, wherein the second insulating layer 80 covers the first conductive layer 40 and the partially exposed first insulating layer 30.
In the present embodiment, the patterned first insulating layer 30 is partially exposed and not completely covered by the first conductive layer 40, wherein the second insulating layer 80 is further disposed in the chip package to cover the first conductive layer 40 and the partially exposed first insulating layer 30, so as to effectively protect the first conductive layer 40 from being damaged by an external force, thereby preventing the logic circuit of the corresponding pin of the chip package from being unable to be effectively implemented due to the external force.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a chip package according to a sixth embodiment of the present application.
Optionally, in an embodiment, the chip package specifically includes: a patterned metal substrate board 10, a chip 20, a first insulating layer 30, a patterned first conductive layer 40, a patterned second conductive layer 50, a third conductive layer 60, a conductive metal layer 70, and a second insulating layer 80.
Wherein a groove is formed on the patterned metal substrate 10, the depth of the groove is less than the thickness of the metal substrate 10, the third conductive layer 60 is disposed in the groove, the chip 20 is disposed on the third conductive layer 60, the first insulating layer 30 covers the chip 20 and the metal substrate 10, and the patterned second conductive layer 50 is further disposed on the first insulating layer 30, wherein through holes are formed in the first insulating layer 30 and the second conductive layer 50 to expose portions of the metal substrate 10 and the chip 20, and the patterned first conductive layer 40 is disposed on the second conductive layer 50 and in the through holes, so that the chip 20 can be connected to the patterned second conductive layer 50 and the patterned metal substrate 10 through the patterned first conductive layer 40 to form a lead of a chip package, thereby the chip package has a short electrical path and a heat dissipation path, and has excellent low resistance characteristics and heat dissipation effects.
The conductive metal layer 70 is disposed on the surface of the metal substrate 10 away from the first insulating layer 30, and the conductive metal layer 70 is a thickened and stacked layer of the metal substrate 10 to ensure the patterned metal substrate 10 to be finally formed, i.e., the corresponding pins of the chip package have more reliable strength, and are not easily bent or broken. The second insulating layer 80 covers the first conductive layer 40 and the partially exposed second conductive layer 50 to effectively protect the first conductive layer 40 and the second conductive layer 50 from being damaged by external force, so as to prevent the logic circuit of the corresponding pin of the chip package from being unable to be effectively realized due to the external force.
Alternatively, the material of the metal substrate 10 and the conductive metal layer 70 may be one of copper, aluminum, gold, silver and their alloys or metal-filled organics, the material used for the first insulating layer 30 and the second insulating layer 80 may be one of silicon dioxide, silicon nitride, silicon oxynitride-filled organic insulator, circuit board material, and ink, the material of the first conductive layer 40 and the second conductive layer 50 may be one selected from copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organics, and the third conductive layer 60 may be one of silver-based conductive paste, gold-based conductive paste, copper-based conductive paste, and carbon-based conductive paste, or adhesive alloy, such as one of copper, aluminum, gold, silver, and their alloys or metal-filled organics, so that the chip 20 in the chip package can realize double-sided heat dissipation through the metal substrate 10 and the first conductive layer 40 in the through hole, thereby having more excellent heat dissipation characteristics.
Alternatively, the bottom area of the chip 20 may be smaller than the bottom area of the groove provided on the metal substrate 10 for placing the third conductive layer 60 and the chip 20, and in other embodiments, the bottom area of the third conductive layer 60 and the chip 20 may also be equal to the bottom area of the groove, which is not limited in this application.
Alternatively, the surface area of the through hole provided in the first insulating layer 30 on the side facing the metal base plate 10 may be set to be smaller than the surface area on the side away from the metal base plate 10, that is, the bottom areas of the two sides of the through hole may be set to be different, while in other embodiments, the bottom areas of the two sides of the through hole may also be set to be the same, and the through hole may also penetrate through the metal base plate 10, which is not limited in this application.
Optionally, the insulating material used for the second insulating layer 80 is different from the insulating material used for the first insulating layer 30, and the thermal conductivity of the insulating material used for the second insulating layer 80 is better than that of the insulating material used for the first insulating layer 30, that is, the thermal conductivity of the second insulating layer 80 is higher than that of the first insulating layer 30, so that after the first conductive layer 40 and the second conductive layer 50 are coated, the chip 20 can achieve a better heat dissipation effect through the second insulating layer 80.
Optionally, a solder resist insulating layer is further provided on a side of the chip 20 remote from the metal base material plate 10 to allow only the first conductive layer 40 to be connected to the position corresponding to the pad on the side of the chip 20. The bonding pad is a copper layer portion exposed by a side of the chip 20 that needs to be soldered to electrically connect with an external device, and a non-bonding pad on the side of the chip 20 is provided as a solder resist insulating layer.
Optionally, the outermost layer of the chip package, that is, the outer side of the conductive metal layer 70 and the second insulating layer 80, is further provided with an insulating envelope material of any reasonable color, such as black, green or yellow, so as to make the appearance of the chip package more ornamental.
Alternatively, the edge portions of the metal substrate 10 corresponding to the corresponding grooves and the structure of the remaining portions after etching may be beveled edges having at least two different angles of inclination, or may be arranged in any reasonable structural pattern such as an arc-shaped curved surface, a wavy curved surface, and the like.
Alternatively, there may be a void at a position where the metal base material plate 10 is connected to the first conductive layer 40, or inside the first conductive layer 40, and the void is further filled with an insulating resin to prevent the entry of air and/or water molecules.
Optionally, the metal substrate 10 is filled with an insulating envelope material of one of any reasonable colors, such as black, green or yellow, at patterned gaps on a side thereof away from the chip 20, so as to make the appearance of the chip package more ornamental.
Alternatively, the chip package has a plurality of metal base plates 10 and insulating layers stacked correspondingly, and the interconnection of the plurality of metal base plates 10 is realized by a plurality of conductive layers in corresponding through holes.
Optionally, solder balls are further disposed on a side of the metal substrate 10 or the conductive metal layer 70 away from the chip 20 to electrically connect with an external device.
Optionally, a side of the chip package away from the metal substrate board 10 is further connected with a power module device, such as one or more of any reasonable power devices, such as a resistor, a capacitor, a transistor, etc., through the first conductive layer 40.
Optionally, at least two chips 20 are disposed on a side of the metal substrate 10 close to the chips 20, and the at least two chips 20 may be electrically connected to each other through the metal substrate 10 and the first conductive layer 40, or the at least two chips 20 are independent of each other and are not electrically connected, which is specifically set by a user according to the circuit logic that the user needs to achieve.
Fig. 7 is a schematic structural diagram of an embodiment of an electronic device according to the present application, and fig. 7 is a schematic structural diagram of the electronic device according to the present application. The electronic device 700 includes any of the chip packages 710 described above.
Unlike the case of the prior art, the chip package in the present application includes: the patterning metal substrate plate, wherein the metal substrate plate is provided with a groove, and the depth of the groove is smaller than the thickness of the metal substrate plate; the chip is arranged in the groove; a first insulating layer covering the chip and the metal substrate board, wherein a through hole is provided in the first insulating layer to expose a portion of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip in the chip package of this application can dispel the heat through the metal substrate board of patterning to and set up the patterned conducting layer that has bigger heat radiating area in the insulating layer through-hole, thereby make this chip can realize two-sided heat dissipation, and make corresponding chip package's structure simpler, electric route and heat dissipation path are shorter, thereby have excellent low resistance characteristic and radiating effect, and can realize chip package's miniaturization and frivolousization.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.

Claims (9)

1. A chip package, comprising:
the patterning metal substrate plate is provided with a groove, and the depth of the groove is smaller than the thickness of the metal substrate plate;
the chip is arranged in the groove;
a first insulating layer covering the chip and the metal base plate, wherein a through hole is provided in the first insulating layer to expose a portion of the metal base plate and the chip;
a patterned first conductive layer disposed on the first insulating layer and within the via such that the chip is connected to the metal substrate board by the first conductive layer.
2. The chip package of claim 1,
a patterned second conductive layer is further arranged between the first insulating layer and the overlapped part of the first conductive layer, and the chip is connected to the second conductive layer and the metal substrate board through the first conductive layer.
3. The chip package of claim 1,
the metal substrate board with still be provided with the third conducting layer between the part that the chip overlaps, the chip passes through the third conducting layer with the laminating of metal substrate board.
4. The chip package of claim 1,
the chip packaging body further comprises a conductive metal layer, and the conductive metal layer is arranged on the surface, far away from the first insulating layer, of the metal substrate board.
5. The chip package of claim 1,
the chip packaging body further comprises a second insulating layer, and the second insulating layer covers the first conducting layer and the first insulating layer which is partially exposed.
6. The chip package of claim 5,
the thermal conductivity of the second insulating layer is greater than the thermal conductivity of the first insulating layer.
7. The chip package of claim 1,
the bottom area of the chip is smaller than that of the groove.
8. The chip package of claim 1,
the surface area of one side of the through hole facing the metal base material plate is smaller than the surface area of one side of the through hole far away from the metal base material plate.
9. An electronic device comprising the chip package according to any one of claims 1-8.
CN202022151139.XU 2019-09-25 2020-09-25 Chip packaging body and electronic device Active CN214313180U (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910913230X 2019-09-25
CN201910913230 2019-09-25

Publications (1)

Publication Number Publication Date
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CN202022151139.XU Active CN214313180U (en) 2019-09-25 2020-09-25 Chip packaging body and electronic device
CN202011025222.0A Pending CN112563221A (en) 2019-09-25 2020-09-25 Chip package, manufacturing method thereof and electronic device
CN202011025215.0A Pending CN112563219A (en) 2019-09-25 2020-09-25 Chip package, manufacturing method thereof and electronic device
CN202022149330.0U Active CN214313178U (en) 2019-09-25 2020-09-25 Chip packaging body and electronic device
CN202022150645.7U Active CN214313179U (en) 2019-09-25 2020-09-25 Chip packaging body and electronic device
CN202011025216.5A Pending CN112563220A (en) 2019-09-25 2020-09-25 Chip package, manufacturing method thereof and electronic device

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CN202011025215.0A Pending CN112563219A (en) 2019-09-25 2020-09-25 Chip package, manufacturing method thereof and electronic device
CN202022149330.0U Active CN214313178U (en) 2019-09-25 2020-09-25 Chip packaging body and electronic device
CN202022150645.7U Active CN214313179U (en) 2019-09-25 2020-09-25 Chip packaging body and electronic device
CN202011025216.5A Pending CN112563220A (en) 2019-09-25 2020-09-25 Chip package, manufacturing method thereof and electronic device

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CN112563219A (en) 2021-03-26
CN214313179U (en) 2021-09-28
CN112563220A (en) 2021-03-26
CN214313178U (en) 2021-09-28

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