CN215866790U - Test fixture for semiconductor device - Google Patents

Abstract

The utility model relates to the technical field of semiconductor device tests and discloses a test fixture for a semiconductor device, which comprises a PCB (printed Circuit Board) and a first self-excitation prevention circuit and a second self-excitation prevention circuit which are arranged on the PCB; the PCB is provided with a device port, and the device port comprises a device grid port and a device drain port; the PCB is also provided with a first grid port, a first drain port, a radio frequency input port and a radio frequency output port; the radio frequency input port and the first grid port are connected with the grid port of the device through the first self-excitation preventing circuit, and the radio frequency output port and the first drain port are connected with the drain port of the device through the second self-excitation preventing circuit. Has the advantages that: when a reliability test of a semiconductor device is performed, a self-excitation problem of the semiconductor device is overcome by a first self-excitation preventing circuit and a second self-excitation preventing circuit. The matching circuit composed of the capacitor and the resistor meets the requirements of device performance test, and the clamp can be directly used for performing the performance test of the semiconductor device after the experiment.

Description

Test fixture for semiconductor device

Technical Field

The utility model relates to the technical field of semiconductor device tests, in particular to a test fixture of a semiconductor device.

Background

In the development process of a chip, such as a GaN chip, the chip needs to be packaged on a ceramic packaging body, then HTOL reliability verification is performed on the chip, the batch production of engineering can be converted into mass production after the test is passed, and a clamp is needed to be used as a carrier when the HTOL reliability verification is performed, so that the chip can perform HTOL verification.

Most of HTOL test fixtures on the market at present are used as power supply line distribution plates, and the self-excitation problem of devices is not prevented. For radio frequency devices, a self-excitation problem is easy to occur during an HTOL test, so that the HTOL test fails due to non-chip self reasons, and the chip cannot pass HTOL verification.

Meanwhile, after the chip passes through HTOL verification, radio frequency performance test cannot be performed on the conventional HTOL test fixture, and performance test can be performed only by detaching the chip from the HTOL test fixture and installing the chip into the radio frequency performance test fixture. A series of problems of ESD risk, poor test repeatability, low test efficiency and the like can be caused in the process of assembling and disassembling the chip.

In summary, the conventional test fixture for semiconductor devices has a single function, cannot meet the requirements of HTOL tests in various aspects, and simultaneously can generate the self-excitation problem of chips when the HTOL test fixture in the prior art is used, so that the chips cannot pass the HTOL tests. Therefore, the test fixture needs to be improved, so that the test fixture can overcome the problem of self-excitation of the chip during HTOL verification of the chip, and meanwhile, the radio frequency performance of the chip can be tested by adopting the test fixture.

SUMMERY OF THE UTILITY MODEL

The purpose of the utility model is: the novel test fixture for the semiconductor device is provided, so that the self-excitation problem of a chip can be overcome during HTOL verification, and meanwhile, the radio frequency performance of the chip can be tested.

In order to achieve the above object, the present invention provides a test jig for a semiconductor device, comprising: the circuit comprises a PCB, and a first self-excitation prevention circuit and a second self-excitation prevention circuit which are arranged on the PCB; the PCB is provided with a device port, and the device port comprises a device grid port and a device drain port; the PCB is also provided with a first grid port, a first drain port, a radio frequency input port and a radio frequency output port; the radio frequency input port and the first grid port are connected with the grid port of the device through the first self-excitation preventing circuit, and the radio frequency output port and the first drain port are connected with the drain port of the device through the second self-excitation preventing circuit.

Further, the radio frequency input port and the first grid port are respectively connected with a first input port and a second input port of the first self-excitation preventing circuit, and a first output port of the first self-excitation preventing circuit is connected with the grid port of the device.

Further, the first self-excitation prevention circuit comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a first resistor; the first port of the first capacitor is connected with the first input port, the second port of the first capacitor is connected with the first output port, the second port of the first capacitor is connected with the first port of the second capacitor, the second port of the second capacitor is grounded, the first port of the second capacitor is connected with the first port of the first resistor, the second port of the first resistor is connected with the second input port, the first port of the third capacitor is connected with the second port of the first resistor, the second port of the third capacitor is grounded, the first port of the fourth capacitor is connected with the second port of the first resistor, and the second port of the fourth capacitor is grounded.

Further, the radio frequency output port and the first drain port are respectively connected with a third input port and a fourth input port of the second self-excitation prevention circuit, and the second output port of the second self-excitation prevention circuit is connected with the drain port of the device.

Further, the second self-excitation preventing circuit includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, and a twelfth capacitor, a first port of the eighth capacitor is connected to the second output port, a second port of the eighth capacitor is connected to ground, a first port of the ninth capacitor is connected to the second output port, a second output port of the ninth capacitor is connected to the third input port, a first port of the tenth capacitor is connected to the second port of the ninth capacitor, a second port of the tenth capacitor is connected to ground, a first port of the eleventh capacitor is connected to the second port of the ninth capacitor, a second port of the eleventh capacitor is connected to ground, a first port of the twelfth capacitor is connected to the second port of the ninth capacitor, a second port of the twelfth capacitor is connected to ground, and a first port of the fifth capacitor is connected to the second output port, the second port of the fifth capacitor is grounded, the first port of the sixth capacitor is connected with the second output port, the second port of the sixth capacitor is grounded, the first port of the seventh capacitor is connected with the second output port, and the second port of the seventh capacitor is grounded.

Further, the aging fixture further comprises a structural member, the PCB is arranged on the structural member, and a first groove matched with the device port is formed in the structural member.

Furthermore, one end of the radio frequency input port, which is far away from the first self-excitation preventing circuit, is connected with a first load, and one end of the radio frequency output port, which is far away from the second self-excitation preventing circuit, is connected with a second load.

Furthermore, a radio frequency input port of the structural member is provided with a first SMA head, a radio frequency output port is provided with a second SMA head, the first load is connected with the radio frequency input port through the first SMA head, and the second load is connected with the radio frequency output port through the second SMA head.

Further, the PCB is connected with the structural member through screws, and the PCB is provided with screw holes matched with the structural member.

Furthermore, a device source electrode port is further arranged on the PCB.

Compared with the prior art, the test fixture for the semiconductor device has the beneficial effects that: the radio frequency input port and the first grid port are connected with the grid port of the device through the first self-excitation preventing circuit, the radio frequency output port and the first drain port are connected with the drain port of the device through the second self-excitation preventing circuit, and when the semiconductor device is verified, the self-excitation problem of the semiconductor device is solved through the first self-excitation preventing circuit and the second self-excitation preventing circuit. The matching circuit composed of the capacitor and the resistor meets the performance test requirements of the device, and the performance of the device can be measured by using the clamp. The HTOL aging and the performance test of the device are realized on the same clamp. Therefore, the device is not required to be disassembled, and the problems of ESD (electro-static discharge) caused by disassembling the device, poor test repeatability and low test efficiency are avoided. The safety and the test accuracy of the device in the aging experiment are ensured, and the test efficiency is improved.

Drawings

FIG. 1 is a schematic diagram of an anti-self-excitation circuit and device ports on a PCB board of the present invention;

fig. 2 is a schematic view of the connection of the first and second loads and the PCB board in the present invention;

FIG. 3 is a top view of the overall structure of the weathering fixture of the present invention;

fig. 4 is a left side view of the overall structure of the burn-in jig of fig. 3 according to the present invention.

In the figure, 1, device gate port; 2. a device source port; 3. a device drain port; 4. a first gate port; 5. a first source port; 6. a first drain port; 7. a PCB board; 8. a first load; 9. a second load; 10. a first SMA head; 11. a second SMA head; 12. a structural member.

Detailed Description

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the utility model but are not intended to limit the scope of the utility model.

As shown in fig. 1 and 3, the present invention discloses a test jig for a semiconductor device, comprising: the circuit comprises a PCB (printed circuit board) 7, and a first self-excitation prevention circuit and a second self-excitation prevention circuit which are arranged on the PCB 7; the PCB 8 is provided with a device port, and the device port comprises a device grid port 1 and a device drain port 3; the PCB 7 is also provided with a first grid port 4, a first drain port 6, a radio frequency input port and a radio frequency output port; the radio frequency input port and the first grid port 4 are connected with the grid port 1 of the device through a first self-excitation preventing circuit, and the radio frequency output port and the first drain port 6 are connected with the drain port 3 of the device through a second self-excitation preventing circuit.

Ageing anchor clamps among the prior art are owing to do not set up and prevent that the self excitation circuit consequently can appear the auto excitation phenomenon in semiconductor device's verification process, and then cause the semiconductor device to damage, cause verification failure, and in the technical scheme of the utility model discloses, radio frequency input port and first grid port 4 all are connected with device grid port 1 through first preventing the self excitation circuit, radio frequency output port and first drain port 6 all prevent the self excitation circuit through the second and are connected with device drain port 3, when carrying out semiconductor device's verification, prevent the self excitation problem that the self excitation circuit overcome semiconductor device through first preventing self excitation circuit and second. And the existing solution is that the aging clamp and the test clamp are separated, and after the device is aged, the device is disassembled and then loaded on the test clamp. This process needs repeated dismantlement, loading, and efficiency of software testing is lower, and has the ESD risk in assembling process, because assembly error leads to test environment uniformity relatively poor easily, leads to the test accuracy relatively poor, tests before the reliability experiment, tests after the experiment and need keep test environment unanimous as far as possible. By designing the clamp into the aging and testing integration, the device does not need to be disassembled and assembled when the reliability of the device is verified, the ESD risk in the assembling process is avoided, the problem that the consistency of the testing environment is poor due to the assembling error is avoided, and the testing efficiency is improved.

In this embodiment, the radio frequency input port and the first gate port 4 are respectively connected to a first input port and a second input port of the first self-excitation prevention circuit, and a first output port of the first self-excitation prevention circuit is connected to the device gate port 1. In the prior art, the radio frequency input port and the first grid port 4 are often directly connected with the semiconductor device, so that no corresponding protection circuit is provided when the self-excitation phenomenon occurs, and the self-excitation of the semiconductor chip is inhibited.

In this embodiment, the first self-excitation prevention circuit includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a first resistor; the first port of the first capacitor is connected with the first input port, the second port of the first capacitor is connected with the device grid port 1, the second port of the first capacitor is connected with the first port of the second capacitor, the second port of the second capacitor is grounded, the first port of the second capacitor is connected with the first port of the first resistor, the second port of the first resistor is connected with the second input port, the first port of the third capacitor is connected with the second port of the first resistor, the second port of the third capacitor is grounded, the first port of the fourth capacitor is connected with the second port of the first resistor, and the second port of the fourth capacitor is grounded. In order to ensure that the rf signal is transmitted from the input to the output as efficiently as possible, the circuit at the input needs to be matched accordingly according to the device performance. And the input matching circuit can meet the input matching impedance requirement of the device through the capacitance arrangement of the input end, and signals can be input to the input end of the device from the PCB radio frequency signal input end with smaller loss. And the self-excitation preventing resistor is arranged between the grid port 1 of the grid device and the first grid port 4, so that a feedback signal passing through the internal resistance of the power supply is reduced, and the generation of self-excitation oscillation is avoided.

In this embodiment, all the capacitors adopt high temperature and high voltage resistant capacitors, and meet the HTOL experimental environment.

In this embodiment, the radio frequency output port and the first drain port 6 are respectively connected to a third input port and a fourth input port of a second self-excited-prevention circuit, and a second output port of the second self-excited-prevention circuit is connected to the device drain port 3. In the prior art, the radio frequency output port and the first drain port 6 are often directly connected with a semiconductor device, so that when the device works, a power supply is easy to fluctuate due to external interference, and adverse effects are caused on the device.

In this embodiment, the second self-excited circuit includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, and a twelfth capacitor, a first port of the eighth capacitor is connected to the second output port, a second port of the eighth capacitor is connected to ground, a first port of the ninth capacitor is connected to the second output port, a second output port of the ninth capacitor is connected to the third input port, a first port of the tenth capacitor is connected to the second port of the ninth capacitor, a second port of the tenth capacitor is connected to ground, a first port of the eleventh capacitor is connected to ground, a first port of the twelfth capacitor is connected to the second port of the ninth capacitor, and a second port of the twelfth capacitor is connected to ground, the first port of the fifth capacitor is connected with the second output port, the second port of the fifth capacitor is grounded, the first port of the sixth capacitor is connected with the second output port, the second port of the sixth capacitor is grounded, the first port of the seventh capacitor is connected with the second output port, and the second port of the seventh capacitor is grounded. In order to ensure that the rf signal can be transmitted from the input terminal to the output terminal as efficiently as possible, the circuit at the output terminal needs to be matched according to the performance of the device. And through the capacitor arrangement of the output end, the output matching circuit can meet the output matching impedance requirement of the device, and signals can be output to the radio frequency signal output end of the PCB from the output end of the device with smaller loss. And a capacitor is arranged between the drain port 3 and the first drain port 6 of the device to carry out filtering processing, so that adverse effects on the device caused by fluctuation of a power supply due to external interference are avoided.

In this embodiment, the aging fixture further comprises a structural member 12, the PCB board 7 is disposed on the structural member 12, and the structural member 12 is provided with a first groove matched with the device port. The first groove may be designed accordingly according to a semiconductor device to be verified, and functions to facilitate mounting and connection of the semiconductor device. The PCB 7 is arranged on the structural member 12 made of metal materials, so that each component or port on the PCB 7 can be conveniently grounded, and meanwhile, the structural member 12 is used as a carrier of the PCB 7 and is also used for increasing loads at a radio frequency input port and a radio frequency output port so as to further avoid the self-excitation phenomenon in the reliability experiment process.

In this embodiment, one end of the radio frequency input port, which is far away from the first self-excitation preventing circuit, is connected with a first load 8, and one end of the radio frequency output port, which is far away from the second self-excitation preventing circuit, is connected with a second load 9. The first load 8 and the second load 9 are used to further prevent the self-excitation phenomenon of the semiconductor device from occurring in the burn-in test.

In this embodiment, the radio frequency input port of the structural member 12 is provided with a first SMA head, the radio frequency output port is provided with a second SMA head 11, the first load 8 is connected with the radio frequency input port through a first SMA head 10, and the second load 9 is connected with the radio frequency output port through a second SMA head 11. The first SMA head 10 and the second SMA head 11 can be connected with a load conveniently, one end of the first SMA head 10 or the second SMA head 11 is provided with a screw hole connected with a structural member 13 through a screw and a soldering lug welded with a radio frequency input port or a radio frequency output port, and the other end of the first SMA head 10 or the second SMA head is provided with a thread connected with a first load 8 or a second load 9. The first load 8 and the second load 9 are resistors, and the first load 8 may be screwed to the first SMA head 10, and the second load 9 may be screwed to the second SMA head 11. In the reliability experiment process, the first SMA head 10 and the second SMA head 11 are both connected with a 50 omega load resistor, so that the device is ensured not to be self-excited in the experiment process. When testing is needed after the experiment is finished, the 50 omega load resistors of the first SMA head 10 and the second SMA head 11 are taken down, the first SMA head 10 is connected with the radio frequency input end of the radio frequency testing system, and the second SMA head 11 is connected with the radio frequency output end of the radio frequency testing system. The positive electrode of a grid power supply of the radio frequency test system is connected to the first grid port 4; the positive electrode of a drain power supply of the radio frequency test system is connected to the first drain port 6; the grid electrode and the drain electrode of the radio frequency test system are connected to the first source electrode port 5; after the clamp is connected with the test system, the radio frequency test system is started to test the performance of the device. In this embodiment, the PCB 7 and the structural member 12 are connected by screws, and the PCB 7 is provided with screw holes for matching with the structural member 12. The PCB 7 and the structural member 12 can be more stably connected through screw connection, and meanwhile, the disassembly and the use are convenient. The PCB 7 is further provided with a plurality of screw holes for connecting different ports, such as the connection of the first source port 5 and the first source port 2 of the device.

In this embodiment, the PCB board 7 is further provided with a device source port 2.

In summary, the embodiment of the present invention provides a test fixture for a semiconductor device, which has the following beneficial effects: the radio frequency input port and the first grid port 4 are connected with the grid port 1 of the device through a first self-excitation preventing circuit, the radio frequency output port and the first drain port 6 are connected with the drain port 3 of the device through a second self-excitation preventing circuit, and when the semiconductor device is verified, the self-excitation problem of the semiconductor device is solved through the first self-excitation preventing circuit and the second self-excitation preventing circuit. When the device is subjected to performance test, the performance measurement requirement of the device can be met through the designed matching circuit, the ESD problem and the accuracy problem generated in the measurement process are effectively avoided, and the test efficiency is improved.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and substitutions can be made without departing from the technical principle of the present invention, and these modifications and substitutions should also be regarded as the protection scope of the present invention.

Claims (10)

1. A test jig for a semiconductor device, comprising: the circuit comprises a PCB, and a first self-excitation prevention circuit and a second self-excitation prevention circuit which are arranged on the PCB; the PCB is provided with a device port, and the device port comprises a device grid port and a device drain port; the PCB is also provided with a first grid port, a first drain port, a radio frequency input port and a radio frequency output port; the radio frequency input port and the first grid port are connected with the grid port of the device through the first self-excitation preventing circuit, and the radio frequency output port and the first drain port are connected with the drain port of the device through the second self-excitation preventing circuit.

2. The test fixture of a semiconductor device, as set forth in claim 1, wherein the radio frequency input port and the first gate port are connected to a first input port and a second input port of a first self-excited-prevention circuit, respectively, and the first output port of the first self-excited-prevention circuit is connected to the device gate port.

3. The test fixture of a semiconductor device according to claim 2, wherein the first self-excited-prevention circuit comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a first resistor; the first port of the first capacitor is connected with the first input port, the second port of the first capacitor is connected with the first output port, the second port of the first capacitor is connected with the first port of the second capacitor, the second port of the second capacitor is grounded, the first port of the second capacitor is connected with the first port of the first resistor, the second port of the first resistor is connected with the second input port, the first port of the third capacitor is connected with the second port of the first resistor, the second port of the third capacitor is grounded, the first port of the fourth capacitor is connected with the second port of the first resistor, and the second port of the fourth capacitor is grounded.

4. The test fixture of a semiconductor device as claimed in claim 1, wherein the rf output port and the first drain port are connected to a third input port and a fourth input port of a second self-excited-prevention circuit, respectively, and the second output port of the second self-excited-prevention circuit is connected to the device drain port.

5. The test fixture of a semiconductor device according to claim 4, wherein the second self-excited-prevention circuit comprises a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor and a twelfth capacitor, a first port and a second output port of the eighth capacitor are connected, a second port of the eighth capacitor is connected to ground, a first port and a second output port of the ninth capacitor are connected, a second output port of the ninth capacitor is connected to a third input port, a first port of the tenth capacitor is connected to a second port of the ninth capacitor, a second port of the tenth capacitor is connected to ground, a first port of the eleventh capacitor is connected to a second port of the ninth capacitor, a second port of the eleventh capacitor is connected to ground, and a first port of the twelfth capacitor is connected to a second port of the ninth capacitor, the second port of the twelfth capacitor is grounded, the first port of the fifth capacitor is connected with the second output port, the second port of the fifth capacitor is grounded, the first port of the sixth capacitor is connected with the second output port, the second port of the sixth capacitor is grounded, the first port of the seventh capacitor is connected with the second output port, and the second port of the seventh capacitor is grounded.

6. The jig of claim 1, wherein the burn-in jig further comprises a structural member, the PCB board is disposed on the structural member, and the structural member is provided with a first groove for engaging with the device port.

7. The test fixture of a semiconductor device as claimed in claim 1, wherein a first load is connected to an end of the rf input port remote from the first self-excitation preventing circuit, and a second load is connected to an end of the rf output port remote from the second self-excitation preventing circuit.

8. The test fixture of claim 7, wherein the radio frequency input port of the structural member is provided with a first SMA head, the radio frequency output port is provided with a second SMA head, the first load is connected with the radio frequency input port through the first SMA head, and the second load is connected with the radio frequency output port through the second SMA head.

9. The test fixture for semiconductor devices as claimed in claim 1, wherein the PCB board is connected to the structural member by screws, and the PCB board is provided with screw holes for engaging with the structural member.

10. A test fixture for semiconductor devices according to any one of claims 1 to 9, wherein a device source port is further provided on the PCB.

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