CN215005730U - Power chip's test system - Google Patents
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- CN215005730U CN215005730U CN202023272139.1U CN202023272139U CN215005730U CN 215005730 U CN215005730 U CN 215005730U CN 202023272139 U CN202023272139 U CN 202023272139U CN 215005730 U CN215005730 U CN 215005730U
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Abstract
The utility model discloses a power chip's test system, the system includes: the tested chip load board is used for bearing the tested power supply chip and realizing the connection between the tested power supply chip and the tested chip interface; the control board is respectively connected with the tested chip interface and the at least one resource interface and is used for realizing the electric connection between the tested chip and the testing resource; the test resource is used for outputting a corresponding resource signal to the power supply chip to be tested according to the control instruction sent by the upper computer; the upper computer is used for sending a control instruction to the test resource by calling a drive program of the test resource; the device comprises a power supply chip, a test module and a control module, wherein the power supply chip is used for outputting test information; and the storage equipment is used for storing the driving program, the corresponding information and the test result of the test resource. The utility model discloses can realize switching wantonly under the different test scene, improve the reusability of equipment, improve production efficiency.
Description
Technical Field
The utility model relates to a power chip tests technical field to more specifically, relate to a power chip's test system.
Background
In the test of an integrated circuit, in order to ensure the stability of a power supply chip, various operating parameters of the power supply chip are often tested.
The existing power supply test scheme is mainly applied to mass production test of a high-power switching power supply on a production line, and aiming at the test of a power supply chip, the cost of a complete system is very high, and the configuration of software and hardware is excessive. Therefore, when testing the power supply chip, a manual test method has to be adopted to record the input current and the output voltage while adjusting the input voltage and the load size, which results in a huge workload. Moreover, the manual test is inevitable to cause the condition that partial data is recorded wrongly, and influences on the subsequent data analysis work are caused. Meanwhile, the existing power chip testing system intelligently tests the power chips of single type, and the universality of the testing system is realized by the method.
Therefore, a system capable of testing different types of new power chips is needed.
Disclosure of Invention
The utility model provides a power chip's test system to solve the problem how to test the power chip of different grade type.
In order to solve the above problem, the utility model provides a power chip's test system, the system includes:
the tested chip load board is respectively connected with the tested power supply chip and the tested chip interface and is used for bearing the tested power supply chip and realizing the connection between the tested power supply chip and the tested chip interface;
the control board is respectively connected with the tested chip interface and the at least one resource interface and is used for realizing the electric connection between the tested chip and the testing resource;
the test resources are respectively connected with the resource interface and the upper computer and used for outputting corresponding resource signals to the power supply chip to be tested according to the control instruction sent by the upper computer;
the upper computer is used for sending a control instruction to the test resource by calling a drive program of the test resource; the device comprises a power supply chip, a test module and a control module, wherein the power supply chip is used for outputting test information;
and the storage equipment is connected with the upper computer and is used for storing the driving program of the test resource, the corresponding information and the test result.
Preferably, wherein the test resources include at least one of the following external meters: the device comprises a power supply, a signal generator, an electronic load and a universal meter;
the resource interface comprises at least one of the following interfaces: power source interface, signal generator interface, electronic load interface and universal meter interface.
Preferably, when the test resource is a power supply, the driving interface of the upper computer includes: setting a voltage function, setting a current function, outputting a switch function, reading a voltage function and reading a current function;
when the test resource is signal generator, the drive interface of host computer includes: setting a waveform type function, setting a waveform level function, setting a waveform frequency function and setting a channel switch function;
when the test resource is electronic load, the drive interface of host computer includes: setting a load type function, setting a load parameter function, a channel switch function, a reading current function and a reading voltage function;
when the test resource is the universal meter, the drive interface of host computer includes: a read voltage function and a read current function.
Preferably, the tested chip load board is determined according to the model of the tested power supply chip, and different tested chip load boards use different packaged measuring clamps.
Preferably, the external instruments of different models are connected with the corresponding resource interfaces on the control board through the adapting cables of different models.
Preferably, the external meter is connected with the upper computer through a usb, a network interface and/or an expansion interface.
Preferably, wherein the system further comprises:
the universal meter is used for measuring the voltage output by the power supply chip to be measured; and/or
And the oscilloscope is used for acquiring and displaying the ripple and the rise time output by the power supply chip to be tested.
The utility model provides a test system of power chips, a tested chip load board can bear tested power chips of different models, different customized circuit boards can be replaced according to different tested power chips, different clamps are used, and the purpose that different power chips share one test system is achieved; different test resource interfaces are arranged on the control board, and different test resources are unified into the same calling interface, so that the effect of not developing the software main body again when different test resources are replaced can be achieved; the utility model discloses a user of different test demands provides convenient extension mode, can be very convenient switch wantonly under the test scene of difference such as "on a large scale, low accuracy", "small scale, high accuracy", improved the reusability of equipment, improved production efficiency.
Drawings
A more complete understanding of exemplary embodiments of the present invention may be had by reference to the following drawings:
fig. 1 is a schematic structural diagram of a test system 100 for a power chip according to an embodiment of the present invention;
fig. 2 is a general structural diagram of a test system of a power supply chip according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a software interface according to an embodiment of the present invention;
fig. 4 is a schematic view of a system interface of an upper computer according to an embodiment of the present invention.
Detailed Description
The exemplary embodiments of the present invention will now be described with reference to the accompanying drawings, which, however, may be embodied in many different forms and are not limited to the embodiments described herein, which are provided for the purpose of thoroughly and completely disclosing the present invention and fully conveying the scope of the present invention to those skilled in the art. The terminology used in the exemplary embodiments presented in the accompanying drawings is not intended to be limiting of the invention. In the drawings, the same units/elements are denoted by the same reference numerals.
Unless otherwise defined, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Further, it will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.
Fig. 1 is a schematic structural diagram of a test system 100 for a power chip according to an embodiment of the present invention. As shown in fig. 1, in the testing system of power chips provided by the embodiment of the present invention, the load board of the tested chip can bear the tested power chips of different models, different customized circuit boards can be replaced according to different tested power chips, and different clamps are used, so that different power chips share one testing system; different test resource interfaces are arranged on the control board, and different test resources are unified into the same calling interface, so that the effect of not developing the software main body again when different test resources are replaced can be achieved; the utility model discloses a user of different test demands provides convenient extension mode, can be very convenient switch wantonly under the test scene of difference such as "on a large scale, low accuracy", "small scale, high accuracy", improved the reusability of equipment, improved production efficiency. The utility model discloses embodiment provides a power chip's test system 100, include: a chip load board 101 to be tested, a control board 102, test resources 103, an upper computer 104 and a storage device 105.
Preferably, the tested chip load board 101 is connected to the tested power chip and the tested chip interface, respectively, for bearing the tested power chip and realizing the connection between the tested power chip and the tested chip interface.
Preferably, the tested chip load board is determined according to the model of the tested power supply chip, and different tested chip load boards use different packaged measuring clamps.
Combine fig. 2 to show the utility model discloses in, power chip's test system comprises by being surveyed chip load board, unified chip interface, control panel, unified resource interface, test resource, adaptation cable and host computer of being surveyed. The tested device load board is a circuit board customized according to new tested power supply chips of different models, and the tested chip load board is used for bearing the tested power supply chips and connecting the tested power supply chips with the test resources of the control board, so that the function of adapting the tested power supply chips with the test system is achieved.
The function of the tested chip load board is to provide connection between the tested chip and the unified tested chip interface. Because tested chips are various in types and different in styles, corresponding tested chip load plates are developed for tested power supply chips of different models, and clamps of different packages are used, so that the universality of the test system on the tested chips of different models is achieved. During testing, different tested chip load plates can be replaced according to tested power supply chips of different models, different clamps are used, and the purpose that different tested power supply chips share one testing system is achieved. The tested chip load board provides a uniform standard interface, and when different tested power supply chips are replaced, only the tested power supply chip needs to be designed to be matched with the tested chip load board of the test system. The utility model discloses pass through the chip interface connection under test of this unified standard to the device load board under test with the resource of every kind of instrument external instrument.
Preferably, the control board 102 is connected to the chip interface to be tested and at least one resource interface, respectively, for electrically connecting the chip to be tested and the test resource.
Preferably, wherein the test resources include at least one of the following external meters: the device comprises a power supply, a signal generator, an electronic load and a universal meter;
the resource interface comprises at least one of the following interfaces: power source interface, signal generator interface, electronic load interface and universal meter interface.
Preferably, the external instruments of different models are connected with the corresponding resource interfaces on the control board through the adapting cables of different models.
Preferably, the external meter is connected with the upper computer through a usb, a network interface and/or an expansion interface.
Preferably, the test resource 103 is connected to the resource interface and the upper computer, respectively, and is configured to output a corresponding resource signal to the power supply chip to be tested according to a control instruction sent by the upper computer.
The utility model discloses in, play the effect of being connected to the chip interface under test with various resources through the control panel. The types of resource interfaces provided by the control board include, but are not limited to, power source interfaces, signal generator interfaces, electronic load interfaces, multimeter interfaces, and the like.
The test resource is an external instrument of a third party and can be called according to specific test requirements. Because the application scope of external instrument is limited, can reach the effect of expanding whole coverage through changing the external instrument that is fit for different scopes. All external instruments need to be connected with an upper computer, and the connection modes include but are not limited to usb, network interfaces, expansion interfaces and the like according to external interfaces of the external instruments. And the upper computer software controls the external instruments by calling the driving programs of different external instruments. And classifying the external instruments according to types by adopting an interface-based development mode. Each type of external meter has a uniform interface. Then, for each specific external meter model, an adaptive driver for the external meter and the unified interface is developed. In this way, each different external meter model is unified into the same calling interface. The effect of replacing different external instruments without redeveloping the software main body is achieved.
In a particular implementation, different types of external meters are provided with different standardized interfaces, as different types of external meters may provide different amounts and types of test resources. The adaptation cable that provides through every kind of outside instrument, to the same type, the outside instrument of different models, the different adaptation cable of customization is used for connecting the standardized resource interface on this type outside instrument and the control panel, reaches the outside instrument of the different models of this type of change wantonly, all can guarantee test system normal operating's effect.
Preferably, the upper computer 104 is configured to send a control instruction to the test resource by calling a driver of the test resource; the device is used for acquiring response information output by the tested chip and determining the test result of the tested power supply chip based on the response information. Preferably, the storage device 105 is connected to the upper computer, and is configured to store the driver of the test resource, the corresponding information, and the test result.
Preferably, the storage device 105 is connected to the upper computer, and is configured to store the driver of the test resource, the corresponding information, and the test result.
Preferably, when the test resource is a power supply, the driving interface of the upper computer includes: setting a voltage function, setting a current function, outputting a switch function, reading a voltage function and reading a current function;
when the test resource is signal generator, the drive interface of host computer includes: setting a waveform type function, setting a waveform level function, setting a waveform frequency function and setting a channel switch function;
when the test resource is electronic load, the drive interface of host computer includes: setting a load type function, setting a load parameter function, a channel switch function, a reading current function and a reading voltage function;
when the test resource is the universal meter, the drive interface of host computer includes: a read voltage function and a read current function.
Preferably, wherein the system further comprises:
the universal meter is used for measuring the voltage output by the power supply chip to be measured; and/or
And the oscilloscope is used for acquiring and displaying the ripple and the rise time output by the power supply chip to be tested.
The utility model discloses in, the driver program of host computer software through calling different outside instruments controls outside instrument, adopts the development mode based on the interface, classifies outside instrument according to the kind. Each type of external meter has a uniform interface. Then, for each specific external meter model, an adaptive driver for the external meter and the unified interface is developed. The software interface is shown in fig. 3 and includes: the device comprises a power supply driving interface, a signal generator driving interface, an electronic load driving interface and a multimeter driving interface.
The utility model discloses in, the host computer software realizes the in-process, although the outside instrument of different models, control command probably varies widely, but its function is unanimous. The upper computer software is designed in an interface-based mode. The host computer software body calls the unified interface of the external instrument of the type without paying attention to specific control instructions of different types. On the basis, drive libraries for different models are developed. The driver library meets the unified interface of the type of external instrument defined above on one hand, and on the other hand, is developed for the specific control instruction of the type. The driver library can be used as adaptation software between a specific model and an interface, and plays a role in connecting the software main body with an external instrument of the specific model.
The utility model discloses a power chip test system's advantage lies in, to the outside external instrument of different grade type, has defined a fixed form's physical interface, and this interface satisfies draws this type of outside instrument resource completely. For example, the power source type resource, each power source provides two signal interfaces of positive pole and negative pole. The effect of replacing the test resources as required is realized by standardizing the interfaces of the test resources and unifying the software control interfaces, and the expandability is provided. The universality of the test system is realized through the standard unified interface of the tested chip and the load board of the tested chip.
The utility model discloses an among the real-time mode, measure a 12V and convert 3.3V's power chip into. The specific process comprises the following steps: firstly, a load board of a tested chip is required to be designed, a measuring clamp is customized, the tested chip is fixed on the load board by using the customized measuring clamp, and a load single board is connected with the system through a connector; then, according to the definition sequence of the standard interface, the upper computer drives an external instrument of the power supply to output a 12V power supply, and simultaneously, a universal meter, an oscilloscope and the like are called to measure indexes such as voltage, ripple waves, rise time and the like output by the power supply; and finally, the upper computer software reads the measured result back to the upper computer by calling the interface code, the upper computer further analyzes the read measured result, draws index patterns such as a power curve, ripples, rise time and the like, and outputs the measured analysis result. The system interface is shown in fig. 4. The utility model discloses a system software can select the kind of surveying the power chip of being surveyed, model and sub-model, and it has own test item, test result etc. to correspond every kind of chip.
The invention has been described with reference to a few embodiments. However, other embodiments of the invention than the above disclosed are equally possible within the scope of the invention, as would be apparent to a person skilled in the art, as defined by the appended patent claims.
Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a/an/the [ device, component, etc ]" are to be interpreted openly as referring to at least one instance of said device, component, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents of the embodiments of the invention may be made without departing from the spirit and scope of the invention, which should be construed as falling within the scope of the claims of the invention.
Claims (7)
1. A system for testing a power chip, the system comprising:
the tested chip load board is respectively connected with the tested power supply chip and the tested chip interface and is used for bearing the tested power supply chip and realizing the connection between the tested power supply chip and the tested chip interface;
the control board is respectively connected with the tested chip interface and the at least one resource interface and is used for realizing the electric connection between the tested chip and the testing resource;
the test resources are respectively connected with the resource interface and the upper computer and used for outputting corresponding resource signals to the power supply chip to be tested according to the control instruction sent by the upper computer;
the upper computer is used for sending a control instruction to the test resource by calling a drive program of the test resource; the device is used for acquiring response information output by the tested chip and determining the test result of the tested power supply chip based on the response information.
2. The system of claim 1, wherein the test resources include at least one of the following external meters: the device comprises a power supply, a signal generator, an electronic load and a universal meter;
the resource interface comprises at least one of the following interfaces: power source interface, signal generator interface, electronic load interface and universal meter interface.
3. The system of claim 2, wherein when the test resource is a power supply, the driver interface of the upper computer comprises: setting a voltage function, setting a current function, outputting a switch function, reading a voltage function and reading a current function;
when the test resource is signal generator, the drive interface of host computer includes: setting a waveform type function, setting a waveform level function, setting a waveform frequency function and setting a channel switch function;
when the test resource is electronic load, the drive interface of host computer includes: setting a load type function, setting a load parameter function, a channel switch function, a reading current function and a reading voltage function;
when the test resource is the universal meter, the drive interface of host computer includes: a read voltage function and a read current function.
4. The system of claim 1, wherein the tested chip load board is determined according to the model of the tested power chip, and different tested chip load boards use different packaged measuring jigs.
5. The system of claim 2, wherein different models of external meters are connected to corresponding resource interfaces on the control board via different models of adapter cables.
6. The system according to claim 2, wherein the external meter is connected to the upper computer through a usb, a network interface and/or an expansion interface.
7. The system of claim 1, further comprising:
the universal meter is used for measuring the voltage output by the power supply chip to be measured; and/or
And the oscilloscope is used for acquiring and displaying the ripple and the rise time output by the power supply chip to be tested.
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| CN202023272139.1U CN215005730U (en) | 2020-12-30 | 2020-12-30 | Power chip's test system |
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| CN202023272139.1U CN215005730U (en) | 2020-12-30 | 2020-12-30 | Power chip's test system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114325458A (en) * | 2021-12-17 | 2022-04-12 | 苏州浪潮智能科技有限公司 | Testing method, system, device, equipment and storage medium of switching power supply |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114325458A (en) * | 2021-12-17 | 2022-04-12 | 苏州浪潮智能科技有限公司 | Testing method, system, device, equipment and storage medium of switching power supply |
| CN114325458B (en) * | 2021-12-17 | 2024-02-09 | 苏州浪潮智能科技有限公司 | Test method, system, device, equipment and storage medium of switching power supply |
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