CN213186290U - Ultra-high-definition seamless splicing matrix processor - Google Patents
Ultra-high-definition seamless splicing matrix processor Download PDFInfo
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- CN213186290U CN213186290U CN202021924554.8U CN202021924554U CN213186290U CN 213186290 U CN213186290 U CN 213186290U CN 202021924554 U CN202021924554 U CN 202021924554U CN 213186290 U CN213186290 U CN 213186290U
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Abstract
The utility model discloses a clear seamless concatenation matrix processor of superelevation belongs to concatenation treater field, and clear seamless concatenation matrix processor of superelevation includes backplate and MCU main control board, the MCU main control board through first USART interface with the backplate electricity is connected, still includes matrix switching board and synchronous clock circuit board, the first input interface of matrix switching board with the signal output port electricity of MCU main control board is connected, the second input interface of matrix switching board with the signal output port electricity of synchronous clock circuit board is connected, the signal input port and the signal output port of matrix switching board all with the backplate electricity is connected, the signal input port of synchronous clock circuit board with the backplate electricity is connected, the signal input port of MCU main control board with the backplate electricity is connected. The utility model provides a concatenation matrix processor, it has fused audio frequency and video concatenation function and matrix switching function for a matrix processor can realize two kinds of functions, and the practicality is stronger.
Description
Technical Field
The utility model relates to a concatenation treater field especially relates to a clear seamless concatenation matrix processor of superelevation.
Background
The video splicing controller is a video processing and control device, and has the early main function of dividing a video signal into a plurality of display units and outputting the video signal to a plurality of display terminals for display, and provides more scene applications for multi-screen interaction and splicing gradually in the later period, and is widely applied to monitoring systems and huge advertisements.
Chinese patent publication No. CN204681492U discloses a multi-screen splicing processor with IPC and VNC modules, which includes a control backplane, a master control board, a slave control board, an input board and an output board, wherein the master control board is electrically connected to the control backplane and the slave control board respectively, the input board is electrically connected to the output board, the multi-screen splicing processor includes a normal video input card, a normal video output card, a plurality of individual function interaction cards and control lines, the input board is electrically connected to the normal video input card and the individual function interaction cards, the output board is electrically connected to the normal video output card and the individual function interaction cards respectively, the individual function interaction cards include an IPC module and a VNC module, and the input board and the output board are respectively communicated with the control backplane through the control lines. The multi-screen splicing processor is only controlled by the back panel, can realize the splicing function, and needs to be additionally provided with a matrix switcher for matrix switching if the matrix switching is needed.
SUMMERY OF THE UTILITY MODEL
In order to overcome the defect of the prior art, the utility model aims to solve the technical problem that a clear seamless concatenation matrix processor of superelevation is proposed, it has fused audio frequency and video concatenation function and matrix switching function for a matrix processor can realize two kinds of functions, and the practicality is stronger.
To achieve the purpose, the utility model adopts the following technical proposal:
the utility model provides a clear seamless concatenation matrix processor of superelevation includes backplate and MCU main control board, the MCU main control board through first USART interface with the backplate electricity is connected, still includes matrix switching board and synchronous clock circuit board, the first input interface of matrix switching board with the signal delivery outlet electricity of MCU main control board is connected, the second input interface of matrix switching board with the signal delivery outlet electricity of synchronous clock circuit board is connected, the signal input port and the signal delivery outlet of matrix switching board all with the backplate electricity is connected, the signal input port of synchronous clock circuit board with the backplate electricity is connected, the signal input port of MCU main control board with the backplate electricity is connected.
The utility model discloses preferred technical scheme lies in, still includes the input signal processing board, the input signal processing board with the backplate electricity is connected.
The utility model discloses preferably technical scheme lies in, the input signal processing board contains first FPGA circuit board, first MCU input board and the DDR memory that is used for audio video signal collection, compression and conversion, the signal input port and the signal output mouth of first DDR memory all with first FPGA circuit board electricity is connected, first MCU input board through first I2C bus interface with first FPGA circuit board electricity is connected, first MCU input board through the second USART interface with the backplate electricity is connected, the signal input port and the signal output mouth of first FPGA circuit board all with the backplate electricity is connected.
The utility model discloses preferred technical scheme lies in, still include first interface integrated board and second interface integrated board, first interface integrated board through first RGB interface with first FPGA circuit board electricity is connected, the second interface integrated board through the second RGB interface with first FPGA circuit board electricity is connected, first MCU input board through second I2C bus interface with first interface integrated board electricity is connected.
The utility model discloses preferred technical scheme lies in, first interface integrated board includes in HDMI interface, DVI interface and the VGA interface one or more, second interface integrated board includes in HDMI interface, DVI interface and the VGA interface one or more.
The utility model discloses preferred technical scheme lies in, still includes the output signal processing board, the output signal processing board with the backplate electricity is connected.
The utility model discloses preferably technical scheme lies in, output signal processing board contains second FPGA circuit board, second MCU input board and second DDR memory that is used for audio and video signal to zoom, decompress and convert, the signal input port and the signal output port of second DDR memory all with second FPGA circuit board electricity is connected, the second MCU input board through third I2C bus interface with second FPGA circuit board electricity is connected, the second MCU input board through third USART interface with the backplate electricity is connected, the signal input port and the signal output port of second FPGA circuit board all with the backplate electricity is connected.
The utility model discloses preferred technical scheme lies in, still include third interface integrated board and fourth interface integrated board, the third interface integrated board through the third RGB interface with second FPGA circuit board electricity is connected, the fourth interface integrated board through the fourth RGB interface with second FPGA circuit board electricity is connected, the second MCU input board through fourth I2C bus interface with third interface integrated board electricity is connected.
The utility model discloses preferred technical scheme lies in, third interface integrated board includes in HDMI interface, DVI interface and the VGA interface one kind or multiple, fourth interface integrated board includes in HDMI interface, DVI interface and the VGA interface one kind or multiple.
The utility model discloses preferred technical scheme lies in, the master control chip model configuration of matrix switch board is STC11L16 XE.
The utility model has the advantages that:
the utility model provides a clear seamless concatenation matrix processor of superelevation makes matrix switching board can switch the signal interaction with the backplate through setting up matrix switching board, MCU main control board and synchronous clock circuit board for matrix processor can enough realize the matrix switching function, also can realize audio frequency and video concatenation function, thereby reaches the purpose of merging into an equipment with matrix switching function and concatenation processor.
Drawings
FIG. 1 is a block diagram of a seamless tiled matrix processor provided in an embodiment of the present invention;
FIG. 2 is a flow diagram of a seamless tiled matrix processor provided in an embodiment of the present invention;
fig. 3 is a circuit diagram of a matrix switch board according to an embodiment of the present invention.
In the figure:
1. a back plate; 2. an MCU main control board; 3. a matrix switching board; 4. a synchronous clock circuit board; 5. an input signal processing board; 51. a first FPGA circuit board; 52. a first MCU input board; 53. a first DDR memory; 54. a first interface integration board; 55. a second interface integration board; 6. an output signal processing board; 61. a second FPGA circuit board; 62. a second MCU input board; 63. a second DDR memory; 64. a third interface integration board; 65. and a fourth interface integration board.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments with reference to the accompanying drawings.
Example one
As shown in fig. 1 and fig. 3, the ultra high definition seamless splicing matrix processor provided in this embodiment includes a backplane 1, an MCU main control board 2, a matrix switching board 3 and a synchronous clock circuit board 4, where the MCU main control board 2 is electrically connected to the backplane 1 through a first USART interface, a first input interface of the matrix switching board 3 is electrically connected to a signal output port of the MCU main control board 2, a second input interface of the matrix switching board 3 is electrically connected to a signal output port of the synchronous clock circuit board 4, both the signal input port and the signal output port of the matrix switching board 3 are electrically connected to the backplane 1, a signal input port of the synchronous clock circuit board 4 is electrically connected to the backplane 1, and a signal input port of the MCU main control board 2 is electrically connected to the backplane 1. The back plate 1 is used for controlling the display to display, the back plate 1 and the matrix switch plate 3 are both controlled by the MCU main control plate 2, and the model of the main control chip of the matrix switch plate 3 is configured as STC11L16 XE. The synchronous clock circuit board 4 and the matrix switch board 3 can realize the matrix switching function, the matrix switch board 3 can transmit one or more video and audio signals to one or more displays respectively, and the synchronous clock circuit board 4 can ensure that the multi-output of the matrix switch board 3 is synchronous. Therefore, the ultra-high definition seamless splicing matrix processor provided by the embodiment can realize the matrix switching function and the audio and video splicing function, and combines the matrix switching function and the splicing processor function into one device.
In order to facilitate the optimization processing of the input signal of the backplane 1, further, the ultra-high definition seamless splicing matrix processor further comprises an input signal processing board 5, and the input signal processing board 5 is electrically connected with the backplane 1. The input signal is collected, compressed, converted and the like by the input signal processing board 5 and then is transmitted to the backboard 1. Further preferably, the input signal processing board 5 includes a first FPGA circuit board 51, a first MCU input board 52 and a first DDR memory 53, which are used for acquiring, compressing and converting the audio/video signal, a signal input port and a signal output port of the first DDR memory 53 are electrically connected to the first FPGA circuit board 51, the first MCU input board 52 is electrically connected to the first FPGA circuit board 51 through a first I2C bus interface, the first MCU input board 52 is electrically connected to the backplane 1 through a second USART interface, and the signal input port and the signal output port of the first FPGA circuit board 51 are electrically connected to the backplane 1 to perform audio/video type interaction with the backplane 1. The first MCU input board 52 is used for controlling the audio/video signal acquisition, compression and conversion of the first FPGA circuit board 51, the first FPGA circuit board 51 has the audio/video signal acquisition, compression and conversion functions, and the first DDR memory 53 is used for data caching.
The ultra-high-definition seamless splicing matrix processor further comprises a first interface integration board 54 and a second interface integration board 55, the first interface integration board 54 is electrically connected with the first FPGA circuit board 51 through a first RGB interface, the second interface integration board 55 is electrically connected with the first FPGA circuit board 51 through a second RGB interface, and the first MCU input board 52 is electrically connected with the first interface integration board 54 through a second I2C bus interface. The first interface integration board 54 and the second interface integration board 55 both include a plurality of different types of peripheral interfaces, and can be used for externally connecting devices such as a computer and a projector. It is further preferable that the first interface integration board 54 includes one or more of an HDMI interface, a DVI interface, and a VGA interface, and the second interface integration board 55 includes one or more of an HDMI interface, a DVI interface, and a VGA interface. The HDMI, DVI and VGA interfaces are common audio and video peripheral interfaces, and have good universality and use convenience.
In order to facilitate the optimization processing of the output signals of the backplane 1, further, the ultra-high definition seamless splicing matrix processor further comprises an output signal processing board 6, and the output signal processing board 6 is electrically connected with the backplane 1. The output signal is collected, compressed, converted and the like by the output signal processing board 6 and then is sent to the back board 1. Further preferably, the output signal processing board 6 includes a second FPGA circuit board 61, a second MCU input board 62 and a second DDR memory 63 for scaling, decompressing and converting the audio/video signal, a signal input port and a signal output port of the second DDR memory 63 are electrically connected to the second FPGA circuit board 61, the second MCU input board 62 is electrically connected to the second FPGA circuit board 61 through a third I2C bus interface, the second MCU input board 62 is electrically connected to the backplane 1 through a third USART interface, and a signal input port and a signal output port of the second FPGA circuit board 61 are electrically connected to the backplane 1. Since the output signal processing board 6 and the input signal processing board 5 are basically similar in composition, detailed functions of the circuit boards will not be described herein.
The ultra-high-definition seamless splicing matrix processor further comprises a third interface integration board 64 and a fourth interface integration board 65, the third interface integration board 64 is electrically connected with the second FPGA circuit board 61 through a third RGB interface, the fourth interface integration board 65 is electrically connected with the second FPGA circuit board 61 through a fourth RGB interface, and the second MCU input board 62 is electrically connected with the third interface integration board 64 through a fourth I2C bus interface. The third interface integration board 64 and the fourth interface integration board 65 both include a plurality of different types of peripheral interfaces, and can be used for externally connecting devices such as a computer and a projector. It is further preferable that the third interface integration board 64 includes one or more of an HDMI interface, a DVI interface, and a VGA interface, and the fourth interface integration board 65 includes one or more of an HDMI interface, a DVI interface, and a VGA interface.
When the ultra-high-definition seamless splicing matrix processor provided in the embodiment is used specifically, as shown in fig. 2, the signal switching is realized through the matrix switching board 3 according to the steps of starting, signal inputting, signal switching, data caching, signal outputting, ending and the like, and when image processing such as compression or superposition and the like is required, the DDR frame caching and image processing steps are performed through the FPGA circuit board and the DDR memory, and then the output is performed through the signal outputting step. Through setting up matrix switch board, MCU master control board and synchronous clock circuit board and make matrix switch board can carry out switching signal interaction with the backplate to make matrix processor can enough realize the matrix switching function, also can realize audio frequency and video concatenation function.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the invention. The present invention is not to be limited by the specific embodiments disclosed herein, and other embodiments that fall within the scope of the claims of the present application are intended to be within the scope of the present invention.
Claims (10)
1. The ultra-high-definition seamless splicing matrix processor comprises a back plate (1) and an MCU (microprogrammed control unit) main control board (2), wherein the MCU main control board (2) is electrically connected with the back plate (1) through a first USART (Universal Serial bus test) interface, and is characterized in that:
the device also comprises a matrix switching board (3) and a synchronous clock circuit board (4);
a first input interface of the matrix switching board (3) is electrically connected with a signal output port of the MCU main control board (2), a second input interface of the matrix switching board (3) is electrically connected with a signal output port of the synchronous clock circuit board (4), and the signal input port and the signal output port of the matrix switching board (3) are electrically connected with the back board (1);
the signal input port of the synchronous clock circuit board (4) is electrically connected with the back plate (1);
and a signal input port of the MCU main control board (2) is electrically connected with the back board (1).
2. The ultra high definition seamless splice matrix processor of claim 1, wherein:
further comprising an input signal processing board (5);
the input signal processing board (5) is electrically connected with the back board (1).
3. The ultra high definition seamless splice matrix processor of claim 2, wherein:
the input signal processing board (5) comprises a first FPGA circuit board (51) for audio and video signal acquisition, compression and conversion, a first MCU input board (52) and a first DDR memory (53);
a signal input port and a signal output port of the first DDR memory (53) are electrically connected with the first FPGA circuit board (51), and the first MCU input board (52) is electrically connected with the first FPGA circuit board (51) through a first I2C bus interface;
the first MCU input board (52) is electrically connected with the backboard (1) through a second USART interface;
and the signal input port and the signal output port of the first FPGA circuit board (51) are electrically connected with the back plate (1).
4. The ultra high definition seamless splice matrix processor of claim 3, wherein:
the connector also comprises a first interface integration board (54) and a second interface integration board (55);
the first interface integration board (54) is electrically connected with the first FPGA circuit board (51) through a first RGB interface;
the second interface integration board (55) is electrically connected with the first FPGA circuit board (51) through a second RGB interface;
the first MCU input board (52) is electrically connected with the first interface integration board (54) through a second I2C bus interface.
5. The ultra high definition seamless splice matrix processor of claim 4, wherein:
the first interface integration board (54) includes one or more of an HDMI interface, a DVI interface, and a VGA interface, and the second interface integration board (55) includes one or more of an HDMI interface, a DVI interface, and a VGA interface.
6. The ultra high definition seamless splice matrix processor of claim 1, wherein:
also comprises an output signal processing board (6);
the output signal processing board (6) is electrically connected with the back board (1).
7. The ultra high definition seamless splice matrix processor of claim 6, wherein:
the output signal processing board (6) comprises a second FPGA circuit board (61) for scaling, decompressing and converting audio and video signals, a second MCU input board (62) and a second DDR memory (63);
a signal input port and a signal output port of the second DDR memory (63) are electrically connected with the second FPGA circuit board (61), and the second MCU input board (62) is electrically connected with the second FPGA circuit board (61) through a third I2C bus interface;
the second MCU input board (62) is electrically connected with the backboard (1) through a third USART interface;
and a signal input port and a signal output port of the second FPGA circuit board (61) are electrically connected with the back plate (1).
8. The ultra high definition seamless splice matrix processor of claim 7, wherein:
the connector also comprises a third interface integration board (64) and a fourth interface integration board (65);
the third interface integration board (64) is electrically connected with the second FPGA circuit board (61) through a third RGB interface;
the fourth interface integration board (65) is electrically connected with the second FPGA circuit board (61) through a fourth RGB interface;
the second MCU input board (62) is electrically connected with the third interface integration board (64) through a fourth I2C bus interface.
9. The ultra high definition seamless splice matrix processor of claim 8, wherein:
the third interface integration board (64) comprises one or more of an HDMI interface, a DVI interface and a VGA interface, and the fourth interface integration board (65) comprises one or more of an HDMI interface, a DVI interface and a VGA interface.
10. The ultra high definition seamless splice matrix processor of claim 1, wherein:
the model of the main control chip of the matrix switching board (3) is configured to be STC11L16 XE.
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| CN202021924554.8U CN213186290U (en) | 2020-09-03 | 2020-09-03 | Ultra-high-definition seamless splicing matrix processor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114339106A (en) * | 2022-01-07 | 2022-04-12 | 北京格非科技股份有限公司 | Ultrahigh-definition SDI (Serial digital interface) and IP (Internet protocol) multi-picture signal processor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114339106A (en) * | 2022-01-07 | 2022-04-12 | 北京格非科技股份有限公司 | Ultrahigh-definition SDI (Serial digital interface) and IP (Internet protocol) multi-picture signal processor |
| CN114339106B (en) * | 2022-01-07 | 2023-06-09 | 北京格非科技股份有限公司 | Ultra-high definition SDI (serial digital interface) and IP (Internet protocol) multi-picture signal processor |
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