CN114339106B

CN114339106B - Ultra-high definition SDI (serial digital interface) and IP (Internet protocol) multi-picture signal processor

Info

Publication number: CN114339106B
Application number: CN202210015791.XA
Authority: CN
Inventors: 鲍放; 赵贵华; 蔺飞; 徐停停; 袁旭稚; 孙培; 姜斌
Original assignee: BEIJING GEFEI TECHNOLOGY CO LTD
Current assignee: BEIJING GEFEI TECHNOLOGY CO LTD
Priority date: 2022-01-07
Filing date: 2022-01-07
Publication date: 2023-06-09
Anticipated expiration: 2042-01-07
Also published as: CN114339106A

Abstract

The invention discloses an ultra-high definition SDI, IP multi-picture signal processor, comprising: an SDI signal input interface, an SDI signal output interface and an IP signal input/output module for inputting the SDI signal, the IP signal and outputting a display picture; the scheduling matrix module is used for scheduling different signals to different display picture windows and scheduling the display pictures to corresponding output interfaces; the main FPGA is used for converting the serial SDI signals into parallel data and carrying out unified clock synchronization processing; synthesizing an output picture according to the first scaling data returned from the FPGA; and superposing the output picture and the second display element returned from the FPGA to obtain a display picture. The invention can be directly accessed to ultra-high definition signals, reduces intermediate processing links, and simplifies system scheme design and construction cost.

Description

Ultra-high definition SDI (serial digital interface) and IP (Internet protocol) multi-picture signal processor

Technical Field

The invention relates to the technical field of multi-picture display processors, in particular to an ultrahigh definition SDI (serial digital interface) and IP (Internet protocol) multi-picture signal processor.

Background

With the rapid development of the ultra-high definition video industry, 4K/8K ultra-high definition signals provide higher requirements on transmission bandwidth; aiming at the problems of multiple cables, difficult maintenance, limited transmission distance and the like of the ultra-high definition signal SDI transmission mode, the characteristics of high bandwidth, high concurrency and bidirectional transmission of the IP technology become the technical evolution direction of the ultra-high definition signal technical solution.

At present, a domestic broadcasting and television system is in a transition stage from an SDI framework to an IP framework, and the coexistence of an SDI signal and an IP signal in the system is a normal state for constructing a broadcasting and television system. The multi-picture display processor performs scaling processing on the multi-channel signals through a compression technology, and then synthesizes a combined picture to be output to a monitor so as to achieve the effect of monitoring the multi-channel pictures at the same time; in addition to simultaneous display of multiple channels of pictures, there is a general demand for displaying characters such as a name (UMD), a taly, a sound column (Audio Bar), etc. of each channel.

The traditional multi-picture signal processor has poor signal format compatibility, can only access SDI signals or IP signals, and can complete the monitoring of the IP signals only by matching with an IP gateway when accessing the IP signals; the method does not support direct access of 4K ultra-high definition video signals, the picture display layout is not flexible enough, the window is small in shrinkage and enlargement, and the position cannot be controlled at will.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides an ultrahigh definition SDI and IP multi-picture signal processor.

The invention discloses an ultra-high definition SDI, IP multi-picture signal processor, comprising:

an SDI signal input interface and an SDI signal output interface for inputting SDI signals and outputting display pictures;

the IP signal input/output module is used for inputting IP signals and outputting display pictures;

the scheduling matrix module is connected with the SDI signal input interface, the SDI signal output interface and the IP signal input/output module and is used for scheduling different signals to different display picture windows and scheduling display pictures to corresponding output interfaces;

the main FPGA is connected with the scheduling matrix module and is used for converting serial SDI signals into parallel data and carrying out unified clock synchronization processing; synthesizing an output picture according to the first scaling data returned from the FPGA; and superposing the output picture and the display element to obtain the display picture;

the first slave FPGAs are connected with the master FPGA through an I2C module and used for scaling the data subjected to unified clock synchronization processing in different resolutions, and returning the scaled data to the master FPGA;

the second slave FPGA is connected with the master FPGA and is used for converting the audio data after the unified clock synchronization processing and returning the converted display elements to the master FPGA.

As a further improvement of the present invention, there is also included: ARM and singlechip;

the ARM is connected with the scheduling matrix module, the master FPGA and the I2C module through the singlechip and is connected with the second slave FPGA and used for:

the user controls the dispatching matrix module through the ARM, selects signals to be displayed and dispatches different signals to different display picture windows;

the scheduling matrix module schedules the picture to a corresponding output interface according to the output format instruction sent by the ARM;

the first slave FPGA performs scaling with different resolutions according to the control instruction transmitted by the ARM;

the second slave FPGA converts the characters input by the user through the ARM into key signals and filling signals, and forms dynamic sound column images and texts according to the PCM volume and the number of audio channels, and finally converts the dynamic sound column images and texts into display elements.

As a further improvement of the invention, an HTTP protocol stack is established in the ARM, a WEBserverver is configured, and the control equipment completes the configuration of the positions, the sizes and the characters needing to be overlapped of different channel pictures through a WEB page.

As a further improvement of the present invention, the first slave FPGA writes the received data into the DDR to perform the completion screen scaling process.

As a further improvement of the present invention, the main FPGA includes:

the serial-parallel conversion module is used for converting an input serial SDI signal into 20-bit parallel data;

the synthesizing module is used for synthesizing an output picture according to the first scaling data returned from the FPGA;

and the superposition module is used for superposing the output picture and the display element to obtain the display picture.

As a further improvement of the invention, the number of the first slave FPGAs is 4, and the 4 slave FPGAs can realize the processing of the maximum 8 paths of 4K ultra-high definition signals.

Compared with the prior art, the invention has the beneficial effects that:

according to the invention, by configuring different interface modules, the ultra-high definition signal can be directly accessed, the intermediate processing links are reduced, and the design and construction cost of a system scheme are simplified.

Drawings

Fig. 1 is a block diagram of an ultra high definition SDI, IP multi-picture signal processor according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The invention is described in further detail below with reference to the attached drawing figures:

as shown in fig. 1, the present invention provides an ultra-high definition SDI, IP multi-picture signal processor, comprising: the system comprises an SDI signal input interface, an SDI signal output interface, an IP signal input/output module, a scheduling matrix module, a master FPGA, an I2C module, 4 first slave FPGAs, 1 second slave FPGA, DDR, ARM and a singlechip;

the connection relation of each module is as follows:

the SDI signal input interface, the SDI signal output interface and the IP signal input/output module are connected with the scheduling matrix module, the scheduling matrix module is connected with the main FPGA, the main FPGA is connected with the I2C module, the I2C module is connected with the 4 first slave FPGAs and the 1 second slave FPGAs, and the 4 first slave FPGAs and the 1 second slave FPGAs are connected with DDRs; ARM is connected with the scheduling matrix module, the main FPGA and the I2C module through the singlechip, and ARM is connected with the second slave FPGA.

The functions of each module are as follows:

the IP signal input/output module is used for inputting 4K ultra-high definition IP signals and outputting display pictures;

the scheduling matrix module is used for enabling a user to control the scheduling matrix module through the ARM, selecting signals to be displayed and scheduling different signals to different display picture windows; the picture is scheduled to a corresponding SDI signal output interface and IP signal input/output module according to the output format instruction transmitted by the ARM;

a main FPGA for: the internal serial-parallel conversion module converts an input serial SDI signal into 20-bit parallel data and realizes unified clock synchronization; and the internal synthesis module synthesizes the output picture according to the first scaling data returned from the FPGA; and the internal superposition module finishes superposition of the output picture and the display element and then sends the superposition to the scheduling matrix module;

the first slave FPGA is used for writing the data content into the DDR to complete the picture scaling processing, scaling with different resolutions is realized according to the control instruction transmitted by the ARM, and then the scaled data is returned to the synthesis module in the main FPGA through the I2C;

the second slave FPGA is used for realizing image-text processing, and converting the image-text processing into key signals and filling signals according to characters input by a user through the ARM; forming dynamic sound column graphics and texts according to the PCM volume and the number of audio channels by the audio; and uniformly transmitting the converted display elements to a main FPGA character superposition module.

Further, an HTTP protocol stack is established in the ARM, WEBserver is configured, and the control device completes the configuration of the positions, the sizes and the characters needing to be overlapped of different channel pictures through the WEB page.

Further, 4 slave FPGAs can realize the processing of maximum 8 paths of 4K ultra-high definition signals.

The invention relates to a use method of an ultra-high definition SDI (serial digital interface) and IP (Internet protocol) multi-picture signal processor, which comprises the following steps:

step 1, accessing signals through an SDI input interface and an IP input interface into a scheduling matrix module; the user can control the scheduling matrix module through the ARM, select signals to be displayed, and schedule different signals to different display picture windows;

step 2, the signals after being subjected to the matrix scheduling module enter a main FPGA after being balanced, a serial-parallel conversion module in the main FPGA converts the input serial SDI signals into 20-bit parallel data, and unified clock synchronization processing is realized;

step 3, the main FPGA sends the video and audio data processed by the unified clock to 4 first slave FPGAs and 1 second slave FPGA through the I2C module;

step 4, 4 slave FPGAs write data content into DDR to perform picture scaling processing, and scaling with different resolutions is realized according to control instructions transmitted by ARM; then returning the scaled data to a synthesis module in the main FPGA through the I2C module, and synthesizing an output picture by the main FPGA;

step 5, writing the data content into the DDR from the FPGA to perform image-text processing: converting the characters input by the user through the ARM into key signals and filling signals; forming dynamic sound column graphics and texts according to the PCM volume and the number of audio channels by the audio; the graphic information is uniformly sent to a main FPGA character superposition module, and is sent to a scheduling matrix module after superposition of an output picture and display elements is completed;

and 6, the scheduling matrix module schedules the picture to the corresponding output interface according to the output format instruction transmitted by the ARM.

The invention has the advantages that:

the multi-picture signal processor is of modularized design, provides an access 4K ultra-high definition IP signal interface, and can also be optionally matched with an SDI interface; the interface can be replaced according to the need, and can be directly connected with an uncompressed IP signal, so that the SDI and IP signals are mixed and connected;

the multi-picture signal processor reduces intermediate processing links, simplifies system scheme design and construction cost; the single machine can process 8 channels of 4K ultra-high definition picture display processing, the picture position and the size can be randomly adjusted, characters can be randomly input, and the superposition position can be adjusted.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An ultra-high definition SDI, IP multi-picture signal processor comprising:

2. The ultra-high definition SDI, IP multi-picture signal processor of claim 1 further comprising: ARM and singlechip;

3. The ultra-high definition SDI, IP multi-picture signal processor of claim 2 wherein an HTTP protocol stack is built in the ARM, a WEBserver is configured, and the control device completes the configuration of the position, size, and character to be superimposed of the different channel pictures through the WEB page.

4. The ultra-high definition SDI, IP multi-picture signal processor of claim 1 wherein the first slave FPGA writes the received data into the DDR for completion of the picture scaling process.

5. The ultra-high definition SDI, IP multi-picture signal processor of claim 1 wherein the main FPGA comprises:

6. The ultra-high definition SDI, IP multi-picture signal processor of claim 2 wherein the number of first slave FPGAs is 4, the 4 slave FPGAs being capable of processing a maximum of 8-way 4K ultra-high definition signal.