CN204350147U - Mixed video control device and display device - Google Patents

Abstract

The utility model discloses mixed video control device and display device, its mixed video control device, comprise the control board of base plate, tablet, output board, matrix plate and the work for control inputs plate, output board, matrix plate, described tablet, output board, matrix plate are connected with base plate with control board; Described serial video signal switches on output board according to video source by described matrix plate, and described serial video signal unstrings by described output board, decode, convert video standard signal to after convergent-divergent process and export.The utility model, by tablet, output board, matrix plate being connected with base plate with control board, making each plate separate, convenient for installation and maintenance, and reduces the volume of mixed video control device.

Description

Mixed video control device and display device

Technical field

The utility model relates to video and to window control technology, particularly a kind of mixed video control device and display device.

Background technology

Various different resolution, form, Interface Video equipment can use by mixed video technology together, the core processing device that current mixed video control device uses is mostly dedicated video process chip, this type of chip height is integrated, secures the analog video input of several roads and a few railway digital video input; Process chip supports the input of many data bit widths, video format conversion, analog-to-digital conversion, video storage, video frame rate conversion, and the function such as picture-in-picture.

Although the fixed mode of special chip simplifies designing requirement, be easy to realize the function that chip specifies, shorten the deadline of project.But, because special chip is fixing pattern, be also changeless to the requirement of the rear end, front end of periphery, lack flexibility, requiring the simple application places of function, waste resource, increase cost, be difficult to promote, and in the more application places of some functional requirements, special chip is used to be difficult to again realize, such as, realize the mixed video control device of 72 road video inputs and 72 road video frequency output, because special chip is HDMI or DVI input and output standard channel, HDMI and DVI is 4 pairs of differential pair transmission video datas, when being intersected by matrix after special chip Video processing, matrix needs to realize the interleaving function of 72*4=288 to differential lines, begin this many quantity to chip matrix itself, the wiring space of PCB and the isometric line requirement of same road video, all difficult with the framework of complete machine.

Traditional mixed video control device comprises stimulus part, signal processing, matrix plate and segment signal output, various piece hardware circuit is complicated, and concentrate on one piece of circuit block, make computer board panel large, when keeping in repair, need detect whole device, when changing faulty components, complete machine cabinet need be torn open.And above-mentioned matrix of having discussed needs to realize the interleaving function of 72*4=288 to differential lines, minimumly on the matrix plate of the controller that makes to window require 4 chips, cost compare is high.

Thus prior art need to improve.

Utility model content

In view of above-mentioned the deficiencies in the prior art part, the purpose of this utility model is to provide a kind of mixed video control device and display device, tablet, output board, matrix plate is connected with base plate with control board, thus makes each plate separate, is convenient to installation and maintenance.

In order to achieve the above object, the utility model takes following technical scheme:

A kind of mixed video control device, it comprises the control board of base plate, tablet, output board, matrix plate and the work for control inputs plate, output board, matrix plate, and described tablet, output board, matrix plate are connected with base plate with control board;

Described tablet Gather and input vision signal, and convert described incoming video signal to serial video signal and transfer on base plate, described serial video signal switches on output board according to video source by described matrix plate, and described serial video signal unstrings by described output board, decode, convert video standard signal to after convergent-divergent process and export.

In described mixed video control device, described tablet is SDI tablet, HDMI tablet, DVI tablet, CVBS tablet, VGA plate or web tablets.

In described mixed video control device, described DVI tablet comprises: a DVI daughter board, the 2nd DVI daughter board, a FPGA process daughter board, the 2nd FPGA process daughter board and the first attachment plug, described base plate is provided with the first gang socket, a described DVI daughter board connects described first attachment plug by a FPGA process daughter board, described 2nd DVI daughter board connects described first attachment plug, described first attachment plug and the first gang socket grafting by the 2nd FPGA process daughter board.

In described mixed video control device, a described DVI daughter board is provided with the first clamping plate type PCI_E seat, the 2nd DVI daughter board is provided with the second clamping plate type PCI_E seat; A described FPGA process daughter board is electrically connected with a DVI daughter board by described first clamping plate type PCI_E seat, and described 2nd FPGA process daughter board is electrically connected with the 2nd DVI daughter board by described second clamping plate type PCI_E seat.

In described mixed video control device, a described DVI daughter board comprises a DVI and inputs seat, the 2nd DVI input seat, a DVI interface chip and the 2nd DVI interface chip; A described DVI is inputted seat and is connected with a FPGA process daughter board by a DVI interface chip, and described 2nd DVI is inputted seat and is connected with a FPGA process daughter board by the 2nd DVI interface chip.

In described mixed video control device, a described FPGA process daughter board comprises the first fpga chip, flash chip and two DDR3 cache chips, and described first fpga chip connects two DDR3 cache chips, flash chip, a DVI interface chip and the 2nd DVI interface chip.

In described mixed video control device, described DVI tablet is provided with the first single-chip microcomputer, the first clock chip, the first crystal oscillator, described first crystal oscillator connects the first single-chip microcomputer by the first clock chip, and described first single-chip microcomputer connects the 3rd DVI interface chip, the 4th DVI interface chip and the second fpga chip on a DVI interface chip, the 2nd DVI interface chip, the first fpga chip and the 2nd DVI daughter board.

In described mixed video control device, described output board comprises at least one output daughter board, described output daughter board comprises the second attachment plug, a FPGA processing module, the 2nd FPGA processing module, the 5th DVI interface chip, the 6th DVI interface chip, the 7th DVI interface chip, the 8th DVI interface chip, a DVI exports seat, the 2nd DVI exports seat, the 3rd DVI exports seat and the 4th DVI exports seat, described base plate is provided with the second gang socket; A described DVI exports seat and connects a FPGA processing module by the 5th DVI interface chip, described 2nd DVI exports seat and connects a FPGA processing module by the 6th DVI interface chip, described 3rd DVI exports seat and connects the 2nd FPGA processing module by the 7th DVI interface chip, described 4th DVI exports seat and connects the 2nd FPGA processing module by the 8th DVI interface chip, a described FPGA processing module and the 2nd FPGA processing module are all electrically connected with the second attachment plug, described second attachment plug and the second gang socket grafting.

In described mixed video control device, described output daughter board also comprises: second clock chip, the 3rd clock chip, the second crystal oscillator, the 3rd crystal oscillator, serial port level conversion module, serial ports and second singlechip; Described second clock chip is connected with the second crystal oscillator and a FPGA processing module, described 3rd clock chip is connected with the 3rd crystal oscillator and the 2nd FPGA processing module, described second singlechip connects the 3rd DVI interface chip, the 4th DVI interface chip, the 5th DVI interface chip, the 6th DVI interface chip, serial port level conversion module, a FPGA processing module and the 2nd FPGA processing module, described serial port level conversion model calling serial ports.

A kind of display device, comprise display screen and mixed video control device, described display screen is connected with mixed video control device.

Compared to prior art, the mixed video control device that the utility model provides and display device, by tablet, output board, matrix plate being connected with base plate with control board, make each plate separate, convenient for installation and maintenance, and reduce the volume of mixed video control device.

Accompanying drawing explanation

The structured flowchart of the mixed video control device that Fig. 1 provides for the utility model;

The schematic diagram of the Application Example of the mixed video control device that Fig. 2 provides for the utility model;

The structured flowchart of DVI tablet in the mixed video control device that Fig. 3 provides for the utility model;

The structured flowchart of output board in the mixed video control device that Fig. 4 provides for the utility model;

The structured flowchart of power panel in the mixed video control device that Fig. 5 provides for the utility model.

Embodiment

The utility model provides a kind of mixed video control device and display device, based on FPGA framework, not only makes system be more than miniaturization, integrated and high reliability, and there is user-programmable characteristic, these advantages will shorten the system cycle, reduce design cost, reduce design risk.FPGA(Field Programmable Gate Array, field programmable gate array) not only make system compact, integrated and reliability raising as programmable logic device, and there is user-programmable characteristic, these advantages will shorten the system cycle, reduce design cost, reduce design risk.

Moreover, part of devices has outside user-programmable ability, also has simple online programmable ability.Wherein, FPGA programming then seems more flexible, and such as, a slice fpga chip is alternative several even tens normal component just, user can IO number of pins nearly hundreds of.Visible, a slice fpga chip just can realize the very complicated logical block of a logic function even Miniature digital system.

FPGA mixed signal controller of windowing integrates the high-end image processing functions such as high resolution video signal collective, the Digital Image Processing of Real-time High Resolution rate, three-dimensional high-order digital filtering, has powerful signal handling capacity.

For making the purpose of this utility model, technical scheme and effect clearly, clearly, referring to the accompanying drawing embodiment that develops simultaneously, the utility model is further described.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.

Mixed video control device of the present utility model, output image is clear, the control such as can realize video superimpose, window.Refer to Fig. 1, described mixed video control device, comprise base plate 1, tablet 2, output board 3, matrix plate 4 and control board 5, described tablet 2, output board 3, matrix plate 4 and control board 5 are all electrically connected with base plate 1, during installation, tablet 2, output board 3, matrix plate 4 and control board 5 all can grafting vertical with base plate 1, to save the area of power panel 6, reduce the volume of mixed video control device.

Described tablet 2 Gather and input vision signal, and described incoming video signal is converted to serial video signal and transfer on base plate 1, serial video signal switches on output board 3 according to video source by described matrix plate 4, and described serial video signal unstrings by described output board 3, decode, convert video standard signal to after convergent-divergent process and exported video superimpose or window display.Described control board 5 is for the operating state of control inputs plate 2, output board 3 and matrix plate 4.

See also Fig. 2 and Fig. 3, described tablet 2 is SDI tablet 21, HDMI tablet 22, DVI tablet 23, CVBS tablet 24, VGA plate 25 or web tablets 26, and output board 3 comprises two and exports daughter board 31.

Due to described matrix plate 4 maximum support 34 road video enter, 34 road videos go out.Therefore, each tablet 2 has at most 4 tunnel vision signals to enter matrix plate 4 by base plate 1, so input has at most 8 pieces of tablets 2,32 road input video.Chip matrix in matrix plate 4 selects the M21121 model of Mindspeed company, is simple and easy to use.Matrix plate 4 controls in real time to be switched to arbitrary output to input signal by control board 5, and chip matrix M21121 has 34 and enters 34 and go out passage, and arbitrary output channel can be the wherein road in 34 road input videos.

Wherein, SDI tablet 21 is four road SDI tablets 21, can input 4 pairs of differential lines, often pair of transmission 1080P video; HDMI tablet 22 is that 4 road HDMI tablets 22 can input 4 pairs of differential lines, often pair of transmission 1080P video DVI tablet 23 is 4 road DVI tablets 23, can input 4 pairs of differential lines, often pair of transmission 1080P video; CVBS tablet 24 is 16 road CVBS tablets 24, can input 4 pairs of differential lines, often pair of transmission 4 picture 1080P video (CVBS tablet 24 transfers 4 road video frequency output to 16 road analog videos, and each exports separately has four analog videos to be formed by stacking); VGA tablet 2 is 4 road VGA tablets 2, can input 4 pairs of differential lines, often pair of transmission 1080P video; Web tablets 26 is 2 road web tablets 26, can input 4 pairs of differential lines, often pair of transmission 1080P video.Base plate 1 inputs differential pair 8 tunnel, 4*8 road vision signal to output board 3.Each output daughter board 31 receives differential pair 8 tunnel, 2*8 road vision signal, and its output board 3 unstrings, decode, convert video standard signal to after convergent-divergent process, exports in the 1080P vision signal to display screen of 2*2 road and plays.

During embody rule, various types of tablet 2 can be selected, and also can use the tablet 2 that polylith is of the same type; The incoming video signal of final all tablets 2 all transfers high speed serialization vision signal to, and the chip matrix being connected to matrix plate 4 by base plate 1 is mutual arbitrarily.Arbitrary independent high speed serialization vision signal adopts a pair differential pair transmission, and flank speed reaches 2.97 G/S.Single output board 3 receives 16 pairs of high speed serialization vision signals from the output of matrix plate 4, and output board 3 can be chosen arbitrarily 16 tunnel vision signals or superposes and window, final output 4 tunnel vision signals; Maximum 4 pieces of output boards 3 have the 16 independent video frequency output in road, and each output video of each output board 3 can be a wherein road of 32 video source or the superposition of several roads video.The interface chip that control board 5 mainly begins on firstization tablet 2 and output board 3, the chip matrix on configuring matrix plate 4 and in real time switching channel, with main-machine communication etc.

See also Fig. 3, described DVI tablet 23 comprises: a DVI daughter board 231, the 2nd DVI daughter board 232, FPGA process daughter board the 233, the 2nd FPGA process daughter board 234 and first attachment plug 235, described base plate 1 is provided with the first gang socket (not shown), a described DVI daughter board 231 connects described first attachment plug 235 by a FPGA process daughter board 233, described 2nd DVI daughter board 232 connects described first attachment plug 235 by the 2nd FPGA process daughter board 234, described first attachment plug 235 and the first gang socket grafting.Described first attachment plug 235 and the first gang socket grafting pin type connectors, first attachment plug 235 is positioned at one end of a DVI daughter board 231, on the front that first gang socket is positioned at, after the first attachment plug 235 and the first gang socket grafting, make DVI tablet 23 hang down with base plate 1, thus by same connected mode, output board 3, matrix plate 4 and control board 5 are all vertical with base plate 1, thus save the volume of control device.

Corresponding for each daughter board different video type by each tablet 2 is divided into two daughter boards, and is divided into the input processing daughter board of input interface daughter board and band fpga chip by the utility model, and each several part is separate is convenient to detection to equipment and maintenance.

Wherein, a described DVI daughter board 231 is provided with the first clamping plate type PCI_E seat (not shown), the 2nd DVI daughter board 232 is provided with the second clamping plate type PCI_E seat (not shown); A described FPGA process daughter board 233 is electrically connected with a DVI daughter board 231 by described first clamping plate type PCI_E seat, and described 2nd FPGA process daughter board 234 is electrically connected with the 2nd DVI daughter board 232 by described second clamping plate type PCI_E seat.The utility model connects two pieces of daughter boards by clamping plate type PCI_E seat, makes input daughter board connect into one piece of circuit board.

Please continue to refer to Fig. 1 and Fig. 3, a described DVI daughter board 231 comprises a DVI and inputs seat 2311, the 2nd DVI input seat 2312, a DVI interface chip 2313 and the 2nd DVI interface chip 2314.A described DVI is inputted seat 2311 and is connected with a FPGA process daughter board 233 by a DVI interface chip 2313, and described 2nd DVI is inputted seat 2312 and is connected with a FPGA process daughter board 233 by the 2nd DVI interface chip 2314.

A described FPGA process daughter board 233 comprises the first fpga chip 2331, flash chip 2332 and two DDR3 cache chips 2333, and described first fpga chip 2331 connects two DDR3 cache chips 2333, flash chip 2332, a DVI interface chip 2313 and the 2nd DVI interface chip 2314.

A described DVI interface chip 2313 adopts model to be EP9351 chip, one DVI daughter board 231 receives two DVI vision signals, respectively by EP9351 chip, the TTL vision signal being 24bit DVI video signal conversion exports in the first fpga chip 2331.Certainly, interface chip also can receive other vision signal, as VGA(Video Graphics Array) signal, HDMI(HDMI (High Definition Multimedia Interface)) signal, CVBS(Composite Video Baseband Signal) signal etc.

Fpga chip adopts the LEF3-17EA-6FN484C chip of LATTICE company, fpga chip as the kernel processor chip of tablet 2, embedded hardware serdes(parallel converters) High Speed Serial, its price is also more cheap; After FPGA suitably processes TTL signal, incite somebody to action and go here and there switching coding and export high speed serialization vision signal, whole tablet 2 is by high-speed interface (i.e. the first attachment plug 235) output 4 pairs of high-speed-differential vision signals.

Because the 2nd DVI daughter board 232 is identical with a FPGA process daughter board 233 with a DVI daughter board 231 with working method with the structure of the 2nd FPGA process daughter board 234, do not repeat herein.

Please continue to refer to Fig. 3, described DVI tablet 23 is provided with the first single-chip microcomputer 2334, first clock chip 2335, first crystal oscillator 2336, described first crystal oscillator 2336 connects the first single-chip microcomputer 2334 by the first clock chip 2335, and described first single-chip microcomputer 2334 connects the 3rd DVI interface chip 2315, the 4th DVI interface chip 2316 and the second fpga chip 2341 on a DVI interface chip 2313, the 2nd DVI interface chip 2314, first fpga chip 2331 and the 2nd DVI daughter board 232.

Wherein, the model of the first single-chip microcomputer is STM32F103RBT6, and the model of clock chip is IDT5V49EE902.Because the video source being input to fpga chip is many, and be with roomy, the utility model adopts the DDR3 cache chip of plug-in 2 the 1G bit of each fpga chip, and the buffer area of composition 32bit carrys out buffer memory multi-frame video.Due to the reference clock source that fpga chip needs multiple requirement strict, as special clock chip can provide 4 differential clocks and a single ended clock, wherein, two differential clocks are used for two serdes High Speed Serials, and another two differential clocks are used for two DDR3 cache chips and control core reference clock.

See also Fig. 1 and Fig. 4, described output board 3 comprises at least one output daughter board 31, described output daughter board 31 comprises the second attachment plug 32, a FPGA processing module 331, the 2nd FPGA processing module 332, the 5th DVI interface chip 341, the 6th DVI interface chip 342, the 7th DVI interface chip 343, the 8th DVI interface chip 344, a DVI exports seat 351, the 2nd DVI exports seat 352, the 3rd DVI exports seat 353 and the 4th DVI exports seat 354, and described base plate 1 is provided with the second gang socket.

A described DVI exports seat 351 and connects a FPGA processing module 331 by the 5th DVI interface chip 341, described 2nd DVI exports seat 352 and connects a FPGA processing module 331 by the 6th DVI interface chip 342, described 3rd DVI exports seat 353 and connects the 2nd FPGA processing module 332 by the 7th DVI interface chip 343, described 4th DVI exports seat 354 and connects the 2nd FPGA processing module 332 by the 8th DVI interface chip 344, a described FPGA processing module 331 and the 2nd FPGA processing module 332 are all electrically connected with the second attachment plug 32, described second attachment plug 32 and the second gang socket grafting.

Wherein, DVI interface chip adopts model to be the interface chip of EP952K, all adopts model to be the fpga chip of LEF3-70EA-8FN672C in the FPGA processing module on each output daughter board 31.

Described output daughter board 31 also comprises: second clock chip 3311, the 3rd clock chip 3312, second crystal oscillator 3313, the 3rd crystal oscillator 3314, serial port level conversion module 355, serial ports 356 and second singlechip 3317.Described second clock chip 3311 is connected with the second crystal oscillator 3313 and a FPGA processing module 331, described 3rd clock chip 3312 is connected with the 3rd crystal oscillator 3314 and the 2nd FPGA processing module 332, described second singlechip 3317 connects the 5th DVI interface chip 341, the 6th DVI interface chip 342, the 7th DVI interface chip 343, the 8th DVI interface chip 344, serial port level conversion module 355, a FPGA processing module 331 and the 2nd FPGA processing module 332, and described serial port level conversion module 355 connects serial ports 356.Wherein, the 5th DVI interface chip adopts model to be the interface chip of EP952K to the 8th DVI interface chip.

For DIV signal, as Figure 1-Figure 4, export daughter board 31 by the second attachment plug from matrix plate 4 or base plate 1 real-time reception 16 tunnel vision signal, every road vision signal is by a pair high-speed-differential line transmission, each fpga chip receives 8 tunnel vision signals of 8 pairs of differential lines transmission separately, FPGA unstrings to 8 tunnel vision signals, after decoding, its video format is RGB or YCBCR, then suitable conversion or filtering process is done, as requested convergent-divergent process is done to a certain road video (maximum 8 road videos) again, finally be superimposed upon in 8 road videos, optional at most 4 tunnel video superimpose output on EP952K interface chip.Interface chip just transfers the TTL signal of 24 to the DVI video of standard, certainly, and also can by replacing interface chip, the HDMI video of final outputting standard.

Because the video source being input to fpga chip is many and be with roomy, each fpga chip needs the DDR3 cache chip of plug-in 4 1G bit, form the buffer area of 2 respective independently 32bit, for buffer memory multi-frame video.On output board 3, the reference clock source that fpga chip needs multiple requirement strict, each fpga chip configures a special clock chip and provides 4 differential clocks and a single ended clock; Wherein, two differential clocks are used for two serdes High Speed Serials, and another two differential clocks are used for two DDR3 cache chips and control core reference clock.The model of the DDR3 cache chip on tablet and output board is MT41J64M16JT-15E, and flash chip adopts model to be M25P64.

See also Fig. 1 and Fig. 5, described base plate 1 is also provided with the power panel 6 for powering to tablet 2, output board 3, matrix plate 4 and control board 5, described power panel 6 is connected with described base plate 1.Wherein, described power panel 6 comprises multiple DC-DC unit and multiple LDO unit, exports 12V voltage, and 12V voltage is carried out step-down, export each module work required voltage.Wherein, described DC-DC unit adopts the DC-DC chip of TPS54386, and LDO unit adopts the LDO chip of AP1117-3.3, AP1117-1.8, LDO29302T5, LDO2998.12V voltage can be become 5V or 1.2V by described DC-DC core, and 5V voltage step-down is given the power supplies such as DDR3 cache chip 2333, fpga chip, flash chip 2332 to 3.3V, 1.8V, 1.5V.1.2V, 0.75V etc. by each LDO chip by 5V voltage afterwards.

In mixed video control device of the present utility model, fpga chip on tablet and output board is the LatticeECP3 FPGA series that Lattice company produces, it combines high-performance FPGA structure, high-performance I/O and reaches the embedded parallel converters (SERDES) of 16 passages with corresponding Physical Coding Sublayer (Physical Coding Sublayer, PCS) logic.PCS logic configurable for support a lot of industrywide standard, high-speed serial data host-host protocol.Each passage of PCS logic comprises special transmission and receives SERDES, can be used for high speed, the full duplex serial data transmission up to 3.2 G bps.The PCS logic of each passage supports a series of conventional data protocol by configuration.In addition, the logic based on agreement can be walked around in many configurations wholly or in part, thus makes user have greater flexibility when designing the high speed interface of oneself.PCS also provides bypass mode (bypass mode), allows use 8 or 10 interfaces that SERDES is directly connected to fpga logic.Each SERDES pin independently can also be implemented direct-current coupling and allow to support at a high speed and tick-over on same SERDES pin simultaneously, is applicable to as application such as serial digital videos.

The utility model adopts high-capacity and high-speed FPGA and CrossPoint(crosspoint) treatment mechanism of digital multibus data route switching, fundamentally ensure to carry out full process and data consistency in real time to all input signal sources, image without delay, without discretization, not frame losing, the perfection achieving image presents.Multiple signal source input pattern supported by FPGA processor, comprises analog video, composite video (DVD or camera signals), pcs signal (VGA or DVI signal), high-definition digital signal (HDMI or high-resolution DVI signal) etc.To computer video signal, compatiblely can support various common resolution, and self-defined unconventional resolution can be realized.The exportable DVI-I signal of splicing device or twisted-pair feeder digital signal, support RGB(simulation)/DVI(numeral) export simultaneously, this means while large-screen normally shows, signal backup to be exported to another group large-screen.In addition, control board can also be the large base map of static state of each group of large-size screen monitors configuration ultrahigh resolution, with the obvious advantage by the mixed signal of FPGA framework controller of windowing, powerful.

Below in conjunction with Fig. 1 to Fig. 5, for DVI video input and DVI video frequency output, mixed video control device of the present utility model is described in detail:

DVI tablet 23 is combined into one piece of complete tablet a DVI daughter board 231, the 2nd DVI daughter board 232 respectively by a clamping plate type PCI_E seat and FPGA process daughter board the 233, a 2nd FPGA process daughter board 234, by two EP9351 interface chips, the TTL vision signal (also can be the YCBCR vision signal of 16bit) that DVI video signal conversion is 24bit is imported in FPGA process daughter board the 233, a 2nd FPGA process daughter board 234 of rear end in DVI tablet 23.The fpga chip of the LEF3-17EA series on FPGA process daughter board as the kernel processor chip of DVI tablet 23, embedded hardware serdes High Speed Serial.Tablet 2, output board 3 are replied by cable behind the door, first single-chip microcomputer 2334 is by multiple I2C bus initialization total interface chip and clock chip, make EP9351 interface chip normally work and configure corresponding resolution, after clock chip initialization, export two pairs of differential clocks, be for a pair 74.25M clock to the HSSI High-Speed Serial Interface kernel of fpga chip inside as with reference to clock, another to for 100M clock to DDR3 cache chip 2333 kernel of fpga chip as reference clock.First single-chip microcomputer 2334 can the instruction of real-time reception control board by serial ports 356, changes the video format of interface chip and the resolution of support thereof, also can change clock chip in real time and export different reference clock.DVI tablet 23 has 2 fpga chips, each FPGA receives the TTL vision signal of 2 tunnel 24 bit wides, fpga chip, to 2 road videos independent process separately, first carries out asynchronous clock conversion vision signal stored in DDR3 cache chip 2333, also can carry out frame rate conversion as requested; Then the stone SERDES of fpga chip inside is converted into the parallel video signal of 24 serial video signal of a pair differential pair transmission, and the Physical Coding Sublayer of stone SERDES inside is configured to 8B/10B pattern and transmits encoding video signal; The transmission bandwidth of HSSI High-Speed Serial Interface is 2G/S, the resolution of different video source and frame per second are carried out and go here and there transform after need the bandwidth restriction of guaranteeing to exceed HSSI High-Speed Serial Interface.Whole tablet 2 exports 4 road high-speed-differentials to vision signal by high-speed interface, and then the input of matrix plate 4 is connected at the high-speed interconnect socket (i.e. the first gang socket) of base plate 1, matrix plate 4 controls input signal to be switched to arbitrary output by control board 5 in real time, and arbitrary output channel can be the wherein road in 34 road input videos.Switch out after required video source through matrix plate 4 and be connected to output board 3 through base plate 1 high-speed interconnect socket (i.e. the second gang socket) equally, single output board 3 at most can real-time reception 16 tunnel vision signal, and every road vision signal is by a pair high-speed-differential line transmission; Each output daughter board 31 also has the fpga chip of the LFE3-70EA series of 2 the same models, and the fpga chip exporting daughter board 31 requires more resource, stone SERDES passage and IO pin etc. than the fpga chip of tablet 2; Each fpga chip of output board 3 receives 8 tunnel vision signals of 8 pairs of differential lines transmission separately, then after first fpga chip unstrings to 8 tunnel vision signals, decodes, video format transfers RGB or YCBCR to, first vision signal after recovery can carry out the shearing of resolution, luminance raising, setting contrast etc.; According to demand, convergent-divergent process is done to a certain road video or multi-channel video (maximum 8 road videos) more afterwards, zoom function module uses the convergent-divergent IP of LATTICE company to realize, convergent-divergent algorithm adopts heterogeneous benefit to taste algorithm, chooses 4 taps 64 carry out filtering convergent-divergent mutually to horizontal vertical direction; Need add frame buffer in Zoom module front end when amplifying process, otherwise likely Zoom module process is not come, cause enlarged image flower screen; Need add frame buffer in Zoom module rear end when process is reduced to video, otherwise Zoom module can not meet the timing requirements of rear end laminating module; Last laminating module optional 1 to 4 road videos in 8 road videos superpose, and selected maximum 4 road videos are superimposed as a road video between two, and laminating module realizes windowing of video, mobile, the functions such as roaming.FPGA exports the TTL vision signal of 24bit to EP952K interface chip after carrying out last overlap-add procedure to video, EP952K interface chip transfers the DVI video of standard to the TTL signal of 24, the most finally DVI video point has shielded the whole transmission of video, conversion, process, realizes required function etc.; Certainly, the utility model also can by replacing interface chip, the HDMI video of final outputting standard.

The utility model is also corresponding provides a kind of display device, and comprise display screen and mixed video control device, described display screen is connected with mixed video control device.The vision signal exported by the tablet Receiving Host of mixed video control device, is shown by display screen after mixed video control device handles accordingly.

The utility model, by tablet, output board, matrix plate and control board and base plate are adopted card insert type design, adopts plate card type design flexibly, is convenient to maintenance, when replacing faulty components without the need to taking complete machine cabinet apart between tablet.Further, tablet, output board all adopt fpga chip as kernel processor chip, the powerful disposal ability of FPGA, promote the definition of video image, can compatible various types of input and output video, the superposition of many video images can be realized, window.The mixed video control device of FPGA framework for the huge many application of input and output number of videos provide can embodiment.

Meanwhile, the HSSI High-Speed Serial Interface that the utility model utilizes fpga chip embedded, transfers the vision signal of 24BIT to the serial signal of differential pair form, saves transmission space and the data wire of vision signal, reduces the designing requirement of matrix plate.In addition, mixed video control device of the present utility model only needs one to the chip matrix on matrix plate, and traditional controller matrix chip of windowing requires four, provides cost savings.

Mixed video control device of the present utility model is pure hardware structure, high performance video image processing workstations without operating system, can multiple dynamic menu be presented at above multiple screen, realize the function of multiwindow splicing, for the occasion of the multiple picture of high-quality display designs, especially be applicable to the flexible control to dissimilar screen and resolution, be applicable to use in the industries such as education and scientific research, government notice, Information publishing, administration, military commanding, display and demonstration, safety monitoring, household appliance sale.

Be understandable that; for those of ordinary skills; can be equal to according to the technical solution of the utility model and utility model design thereof and replace or change, and all these change or replace the protection range that all should belong to the claim appended by the utility model.

Claims (10)

1. a mixed video control device, is characterized in that, comprise the control board of base plate, tablet, output board, matrix plate and the work for control inputs plate, output board, matrix plate, described tablet, output board, matrix plate are connected with base plate with control board;

Described tablet Gather and input vision signal, and convert described incoming video signal to serial video signal and transfer on base plate, described serial video signal switches on output board according to video source by described matrix plate, and described serial video signal unstrings by described output board, decode, convert video standard signal to after convergent-divergent process and export.

2. mixed video control device according to claim 1, is characterized in that, described tablet is SDI tablet, HDMI tablet, DVI tablet, CVBS tablet, VGA plate or web tablets.

3. mixed video control device according to claim 2, it is characterized in that, described DVI tablet comprises: a DVI daughter board, the 2nd DVI daughter board, a FPGA process daughter board, the 2nd FPGA process daughter board and the first attachment plug, described base plate is provided with the first gang socket, a described DVI daughter board connects described first attachment plug by a FPGA process daughter board, described 2nd DVI daughter board connects described first attachment plug, described first attachment plug and the first gang socket grafting by the 2nd FPGA process daughter board.

4. mixed video control device according to claim 3, is characterized in that, a described DVI daughter board is provided with the first clamping plate type PCI_E seat, the 2nd DVI daughter board is provided with the second clamping plate type PCI_E seat; A described FPGA process daughter board is electrically connected with a DVI daughter board by described first clamping plate type PCI_E seat, and described 2nd FPGA process daughter board is electrically connected with the 2nd DVI daughter board by described second clamping plate type PCI_E seat.

5. mixed video control device according to claim 3, is characterized in that, a described DVI daughter board comprises a DVI and inputs seat, the 2nd DVI input seat, a DVI interface chip and the 2nd DVI interface chip; A described DVI is inputted seat and is connected with a FPGA process daughter board by a DVI interface chip, and described 2nd DVI is inputted seat and is connected with a FPGA process daughter board by the 2nd DVI interface chip.

6. mixed video control device according to claim 5, it is characterized in that, a described FPGA process daughter board comprises the first fpga chip, flash chip and two DDR3 cache chips, and described first fpga chip connects two DDR3 cache chips, flash chip, a DVI interface chip and the 2nd DVI interface chip.

7. mixed video control device according to claim 6, it is characterized in that, described DVI tablet is provided with the first single-chip microcomputer, the first clock chip, the first crystal oscillator, described first crystal oscillator connects the first single-chip microcomputer by the first clock chip, and described first single-chip microcomputer connects the 3rd DVI interface chip, the 4th DVI interface chip and the second fpga chip on a DVI interface chip, the 2nd DVI interface chip, the first fpga chip and the 2nd DVI daughter board.

8. mixed video control device according to claim 1, it is characterized in that, described output board comprises at least one output daughter board, described output daughter board comprises the second attachment plug, a FPGA processing module, the 2nd FPGA processing module, the 5th DVI interface chip, the 6th DVI interface chip, the 7th DVI interface chip, the 8th DVI interface chip, a DVI exports seat, the 2nd DVI exports seat, the 3rd DVI exports seat and the 4th DVI exports seat, described base plate is provided with the second gang socket; A described DVI exports seat and connects a FPGA processing module by the 5th DVI interface chip, described 2nd DVI exports seat and connects a FPGA processing module by the 6th DVI interface chip, described 3rd DVI exports seat and connects the 2nd FPGA processing module by the 7th DVI interface chip, described 4th DVI exports seat and connects the 2nd FPGA processing module by the 8th DVI interface chip, a described FPGA processing module and the 2nd FPGA processing module are all electrically connected with the second attachment plug, described second attachment plug and the second gang socket grafting.

9. mixed video control device according to claim 8, is characterized in that, described output daughter board also comprises: second clock chip, the 3rd clock chip, the second crystal oscillator, the 3rd crystal oscillator, serial port level conversion module, serial ports and second singlechip; Described second clock chip is connected with the second crystal oscillator and a FPGA processing module, described 3rd clock chip is connected with the 3rd crystal oscillator and the 2nd FPGA processing module, described second singlechip connects the 3rd DVI interface chip, the 4th DVI interface chip, the 5th DVI interface chip, the 6th DVI interface chip, serial port level conversion module, a FPGA processing module and the 2nd FPGA processing module, described serial port level conversion model calling serial ports.

10. a display device, comprises display screen, it is characterized in that, also comprise the mixed video control device as described in claim 1-9 any one, described display screen is connected with mixed video control device.