CN213069627U - Low quiescent current LDO circuit based on buffer impedance attenuation - Google Patents
Low quiescent current LDO circuit based on buffer impedance attenuation Download PDFInfo
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Abstract
The utility model provides a low quiescent current LDO circuit based on buffer impedance attenuation, through the dynamic adjustment MOS diode who sets up buffer and self-adaptation load current, adopt the parallelly connected feedback of dynamic bias in order to reduce its output resistance in the buffer to under the condition that does not consume big quiescent current, push away the high frequency with the grid pole of power tube. Meanwhile, the current change of the self-adaptive dynamic regulation MOS tube follows the change of the load current, and only a single pole point is generated in the unit gain bandwidth of the regulation loop by adopting current buffer compensation, so that the phase margin of more than 65 degrees is achieved in the full range of the load current. The loop stability of the LDO is realized under the condition that no low-frequency zero is used; also during load transients, the maximum output voltage can be minimized even with a small output capacitance. An LDO with an adaptive load dynamic regulation quiescent current of an impedance attenuation buffer is realized in a 65 nanometer SOI process.
Description
Technical Field
The utility model belongs to the technical field of the analog integrated circuit power supply, specifically speaking relates to a low quiescent current LDO circuit based on attenuator impedance attenuation.
Background
A Low Drop Out Regulator (LDO) is an integrated power supply that outputs a regulated voltage. The basic function of the power supply is to ensure stable output voltage in a certain input voltage variation range and load variation range, and the power supply has high voltage stability, a good transient response process and excellent power supply ripple noise suppression characteristics. It is often used in analog and radio frequency circuit chips as a stable and low noise power supply. In the application of the LDO, a load module of the LDO usually has a plurality of operating modes, such as standby, no-load, or full-load, and corresponding to different operating mode switching, the load module needs the load current provided by the LDO to change, and the load current with different magnitude is equivalent to the LDO connected to a load resistor with different resistance, so that the change of the load resistor causes the pole corresponding to the output end to change, and the pole of the output end is usually the dominant pole of the LDO loop, and this pole causes the stability problem of the loop along with the change of the load.
Fig. 1 shows a basic structure of an LDO and its components, where the basic structure of the LDO is composed of four modules, namely, a voltage reference source (VREF), an Error Amplifier (EA), a voltage difference adjusting tube (MP), and a resistor (RFB1, RFB2) voltage division feedback network. The voltage reference source provides high-precision reference voltage for the error amplifier, and the error amplifier, the differential pressure adjusting tube and the feedback resistor form a control loop for stabilizing output voltage. The off-chip load Resistance (RL) and load Capacitance (CL) have a significant effect on the frequency response and operating point variation of the LDO, and are an indispensable part of LDO loop stability.
The feedback regulation and stable output voltage process of the LDO comprises the following steps:
LDO is a typical application of operational amplifiers and closed-loop negative feedback systems, and the negative feedback loop adjusts itself to maintain a stable output voltage even when the input voltage or load current changes. As shown in FIG. 1, the auxiliary circuit is not considered for the moment, and when the load RL at the output end is reduced, the current flowing through the load is unchanged (when negative feedback analysis is performed, the VCR relationship of voltage, current and impedance assumes one of the quantities unchanged) The output end voltage VOUT is reduced, so that the feedback voltage VF is also reduced, the feedback voltage VF is added to the non-inverting input end of the error amplifier and is compared with the reference voltage VREF added to the inverting input end of the error amplifier to adjust and reduce the output voltage VEA of the error amplifier correspondingly, and therefore the gate-source voltage | V of the adjusting tube MP is reduced correspondinglyGSPIncreasing | drives the adjusting tube to provide more current externally, and raises the output voltage of the LDO.
It has the problems that:
in the basic structure of the LDO, the PMOS transistor is used as an output power transistor, and the output power transistor is usually required to be large in size to provide a large current driving capability (between several milliamperes and several hundred milliamperes) for a load. The larger size of the output power transistor means larger gate capacitance, and the frequency of the pole generated at the gate is lower due to the larger gate capacitance. And usually, when the load of the LDO is small, the frequency of a pole generated at the output end is also low, the pole is usually the dominant pole of the LDO loop, and the pole generated at the gate of the power tube is a secondary pole. When the LDO needs to provide a large load current, the power tube needs to be large, which results in a low frequency of the secondary pole at the gate of the power tube, and further the secondary pole is too close to the primary pole of the output end, which reduces the phase margin of the LDO loop, and finally affects the stability of the LDO loop.
To ensure the stability of the LDO loop, there are two conventional frequency compensations: firstly, through the great load capacitance of output plus to further reduce the frequency of the produced dominant pole of output, thereby draw the distance of dominant pole and secondary pole, guarantee the stability of LDO loop. However, the external load capacitance at the output end is insufficient, so that the unit gain bandwidth of the system is reduced, and the capacitance additionally occupies the chip area. And secondly, an LHP zero point is generated through an ESR equivalent series resistor of the output end load capacitor, and the low-frequency LHP zero point provides positive phase shift to compensate the phase margin to stabilize the loop. However, accurate cancellation of the LDO regulation loop at zero pole pair in the unity gain frequency range is difficult to achieve over the entire load current range, and incomplete zero pole pair cancellation may otherwise cause LDO instability in the worst case. Worse still, if the ESR zero method is used, the resistance will cause a large output voltage overshoot in a large load current step change.
SUMMERY OF THE UTILITY MODEL
The utility model discloses to prior art's above-mentioned shortcoming, provided a low quiescent current LDO circuit based on buffer impedance decay, through addding buffer and self-adaptation dynamic adjustment MOS pipe, adopt the parallelly connected feedback of dynamic biasing in order to reduce its output resistance in the buffer to under the condition that does not consume big quiescent current, push away the high frequency with the grid pole of power tube. Meanwhile, the current change of the self-adaptive dynamic regulation MOS tube follows the change of the load current, and only a single pole point is generated in the unit gain bandwidth of the regulation loop by adopting current buffer compensation, so that the phase margin of more than 65 degrees is achieved in the full range of the load current. The loop stability of the LDO is realized under the condition that no low-frequency zero is used; also during load transients, the maximum output voltage can be minimized even with a small output capacitance. An LDO with an adaptive load dynamic regulation quiescent current of an impedance attenuation buffer is realized in a 65 nanometer SOI process.
The utility model discloses specifically realize the content as follows:
the utility model provides a low quiescent current LDO circuit based on buffer impedance attenuation, including power reference source VREFThe voltage-dividing feedback circuit comprises an error amplifier, an auxiliary circuit, a voltage difference adjusting power tube M0, a voltage-dividing feedback network module, a source follower MOS tube used as a buffer and a compensation MOS diode used for self-adaptively compensating load current;
the power reference source VREFThe voltage division feedback network module is connected with the error amplifier and the differential pressure adjusting power tube M0;
the power reference source VREFThe sources of the error amplifier and the voltage difference adjusting power tube M0 are respectively connected with an input power supply VIN, and the output ends of the error amplifier, the auxiliary circuit and the voltage difference adjusting power tube M0 are connected to form the output end of the low quiescent current LDO circuit;
the grid electrode of the voltage difference adjusting power tube M0 is connected with the error amplifier and the auxiliary circuit, and the source follower MOS tube M10 is arranged between the grid electrode of the voltage difference adjusting power tube M0 and the error amplifier;
the compensation MOS tube M20 is arranged behind the source follower MOS tube M10 and is connected with the pressure difference adjusting power tube M0 in parallel, the source electrode of the compensation MOS tube M20 is connected with an input power supply VIN, the grid electrode of the compensation MOS tube M20 is connected with the grid electrode of the pressure difference adjusting power tube M0 and then is connected with the source electrode of the source follower MOS tube M10, and the drain electrode of the compensation MOS tube M20 is also connected with the source electrode of the source follower MOS tube M10.
In order to better realize the utility model, further, the error amplifier comprises a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a MOS transistor M7, a MOS transistor M8, and a MOS transistor M9;
the grid electrode of the MOS transistor M1 is connected with the power reference source VREF; the grid electrode of the MOS tube M2 is connected with the voltage division feedback network module; the grid electrode of the MOS tube M3 is connected with an auxiliary circuit, and the source electrode is grounded; the source electrodes of the MOS transistor M1 and the MOS transistor M2 are connected with the drain electrode of the MOS transistor M3;
the grid electrode of the MOS tube M8 is connected with an auxiliary circuit, the source electrode is connected with an input power VIN, and the drain electrode is connected with the source electrode of the MOS tube M6 and the drain electrode of the MOS tube M2; the grid electrode of the MOS tube M6 is connected with an auxiliary circuit, and the drain electrode is sequentially connected with the drain electrode of the MOS tube M4, the grid electrode of the MOS tube M5; the sources of the MOS transistor M4 and the MOS transistor M5 are grounded;
the source electrode of the MOS transistor M9 is connected with an input power VIN, the grid electrode of the MOS transistor M8 and the grid electrode of the MOS transistor M are connected with an auxiliary circuit together, and the drain electrode of the MOS transistor M1 and the source electrode of the MOS transistor M7 are connected; the grid electrode of the MOS tube M7 and the grid electrode of the MOS tube M6 are connected with an auxiliary circuit together, and the drain electrode of the MOS tube M7 is connected with the grid electrode of the source follower MOS tube M10 and the drain electrode of the MOS tube M5 respectively; the source of the MOS transistor M5 is grounded.
In order to better realize the utility model, further, the auxiliary circuit comprises a MOS transistor M11, a MOS transistor M12, a MOS transistor M13, a MOS transistor M14, a MOS transistor M15, a MOS transistor M16, a MOS transistor M17, and a MOS transistor M18;
the drain electrode of the MOS tube M15 is connected with a reference current Iref, and the source electrode is respectively connected with the drain electrode and the grid electrode of the MOS tube M14, the drain electrode of the MOS tube M16, the grid electrode of the MOS tube M13 and the grid electrode of the MOS tube M3; the source electrode of the MOS transistor M14, the source electrode of the MOS transistor M16, the source electrode of the MOS transistor M13 and the source electrode of the MOS transistor M3 are grounded;
the source electrode of the MOS transistor M11 is connected with an input power VIN, the drain electrode of the MOS transistor M12 is connected with the source electrode of the MOS transistor M12, and the grid electrodes of the MOS transistor M8 and the MOS transistor M9 are respectively connected with the grid electrodes; the grid electrode and the drain electrode of the MOS tube M11 are also connected through a lead;
the drain electrode of the MOS tube M12 is connected with the drain electrode of the MOS tube M13, and the grid electrodes of the MOS tube M3578 and the MOS tube M6 are respectively connected with the grid electrodes of the MOS tube M7;
the gate of the MOS transistor M15 is connected with the gate of the MOS transistor M17; the source electrode of the MOS tube M17 is connected with an input power VIN, and the drain electrode is lapped between the grid electrode of the source follower MOS tube M10 and the drain electrode of the MOS tube M7;
the gate of the MOS transistor M16 is connected to the gate of the MOS transistor M18, and the drain of the MOS transistor M18 is overlapped between the output end of the low quiescent current LDO circuit and the voltage division feedback network module.
In order to better implement the present invention, further, the voltage dividing feedback network module includes an inductor RFB1 and an inductor RFB2 connected in series to ground, and the gate of the MOS transistor M2 of the error amplifier is connected between the inductor RFB1 and the inductor RFB2 of the voltage dividing feedback network module.
In order to better implement the present invention, further, the auxiliary circuit further includes a capacitor C1, and the capacitor C1 is connected between the drain of the MOS transistor M7 and the output end of the low quiescent current LDO circuit.
Compared with the prior art, the utility model have following advantage and beneficial effect:
1. the utility model discloses a LDO circuit of dynamic buffer impedance decay owing to adopted buffer impedance decay technique, greatly reduced the resistance to ground of pressure differential power tube grid, the non-dominant pole that makes here produce is extrapolated outside the unit gain bandwidth frequency to do not need the ESR zero compensation of output load electric capacity and resistance just can guarantee the stability of LDO loop. The load requirement of the output end of the LDO is reduced; meanwhile, LDO zero compensation is not used, so that the LDO has better transient response performance.
2. Due to the adoption of the dynamic impedance attenuation technology, the LDO keeps a phase margin of more than 65 degrees in a wider load current range (the load current can reach 200mA), and the stability of an LDO loop is ensured in the wide load range.
3. The buffer current follows the dynamic regulation process of the load current, so that the LDO only consumes a few microamperes of static current when no load exists, and the LDO has better current efficiency.
Drawings
FIG. 1 is a block diagram of a prior art LDO;
FIG. 2 is a schematic diagram of an LDO circuit of the present invention improved based on the prior art;
FIG. 3 is a diagram showing the LDO loop stability simulation results with a 10mA load.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the described embodiments are only some embodiments of the present invention, but not all embodiments, and therefore should not be considered as limitations to the scope of protection. Based on the embodiments in the present invention, all other embodiments obtained by the staff of ordinary skill in the art without creative work belong to the protection scope of the present invention.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1:
a low quiescent current LDO circuit based on buffer impedance attenuation is disclosed, as shown in FIG. 2 and FIG. 3, comprising a power reference source VREF, an error amplifier, an auxiliary circuit, a voltage difference adjusting power tube M0, a voltage division feedback network module, a source follower MOS tube used as a buffer and a compensation MOS diode used for self-adaptively compensating load current;
the power supply reference source VREF is connected with the negative electrode input end of the error amplifier, and the voltage division feedback network module is connected with the error amplifier and the differential pressure adjusting power tube M0;
the power reference source VREFThe sources of the error amplifier and the voltage difference adjusting power tube M0 are respectively connected with an input power supply VIN, and the output ends of the error amplifier, the auxiliary circuit and the voltage difference adjusting power tube M0 are connected to form the output end of the low quiescent current LDO circuit;
the grid electrode of the voltage difference adjusting power tube M0 is connected with the error amplifier and the auxiliary circuit, and the source follower MOS tube M10 is arranged between the grid electrode of the voltage difference adjusting power tube M0 and the error amplifier;
the compensation MOS tube M20 is arranged behind the source follower MOS tube M10 and is connected with the pressure difference adjusting power tube M0 in parallel, the source electrode of the compensation MOS tube M20 is connected with an input power supply VIN, the grid electrode of the compensation MOS tube M20 is connected with the grid electrode of the pressure difference adjusting power tube M0 and then is connected with the source electrode of the source follower MOS tube M10, and the drain electrode of the compensation MOS tube M20 is also connected with the source electrode of the source follower MOS tube M10.
The working principle is as follows: in the application of LDO, usually its load module has multiple mode, like standby, empty load, or full load etc., switch corresponding to different mode, load module needs the load current that LDO provided size also to change, load current of different sizes is equivalent to LDO and connects the load resistance of different resistances, therefore, the change of load resistance brings the pole that the output corresponds also to change, and the output pole is the dominant pole of LDO loop usually, this pole will cause the stability problem of loop along with the change of load, so this scheme provides a circuit structure who stabilizes the LDO loop.
In the prior art:
firstly, through the output terminal additional great load capacitance to further reduce the frequency of the produced dominant pole of output, thereby draw the distance of dominant pole and secondary pole, guarantee the stability of LDO loop. However, the method has the defects that the load capacitor is additionally arranged at the output end, so that the unit gain bandwidth of the system is reduced, and the capacitor additionally occupies the chip area;
and secondly, a proper zero is generated to offset a secondary pole in a unit gain bandwidth frequency range to stabilize the loop. However, in the whole load current range, the regulation loop of the LDO is difficult to generate an appropriate zero point in the unit gain frequency range, so that accurate cancellation of the zero point pair is difficult to achieve. Worse still, if the ESR zero method is used, the resistance will cause a large output voltage overshoot in a large load current step change.
The larger size of the output power tube means larger gate capacitance, and the larger gate capacitance causes the frequency of the pole generated at the gate to be lower. If the capacitance of the grid of the power tube cannot be reduced, the resistance from the grid to the ground is reduced, and the effective method is to insert a buffer in front of the power tube for impedance attenuation.
Therefore, in the present invention, the source follower has a low output impedance, and can be used as a voltage buffer to drive the output power transistor, so as to reduce the resistance from the gate of the power transistor to the ground, thereby increasing the frequency of the second-order pole at the gate of the power transistor. However, if the LDO needs to provide a larger load current (e.g., 100 ma or more), a larger power tube is needed, the gate capacitance increases with the size, and the output resistance at the gate of the power tube needs to be further reduced to maintain the stability of the loop. For the source follower, the output resistance is about the reciprocal of the transconductance, and to reduce the output resistance, the transconductance needs to be increased, and the increase of the transconductance needs to increase the current of the tube.
In the dynamic change range of the LDO load, the current of the buffer is required to be large when the load is large, the frequency of the main pole of the LDO output end reaches the minimum when the load is no, the secondary pole of the grid of the power tube is far away from the main pole, and the LDO loop can be stabilized without increasing the current of the buffer to reduce the output impedance of the LDO loop.
Therefore, according to the situation that the dominant pole changes due to the change of the load current, the attenuation of the buffer impedance needs to be correspondingly dynamically adjusted, so that the buffer current is increased during heavy load, and the buffer current is reduced during no load, thereby reducing the quiescent current consumed by the buffer and improving the current efficiency of the LDO.
As shown in fig. 2, the circuit structure of the present invention is mainly improved by two points on the basis of the basic structure:
firstly, a source follower MOS transistor M10, also called a Buffer (Buffer), is inserted in front of the gate of the output power transistor M0. The buffer mainly has the function of reducing the total resistance at the grid electrode of the power tube by utilizing the low output resistance of the buffer and the grid electrode resistance of the power tube in parallel, so that the frequency of a secondary pole point generated at the grid electrode of the power tube is increased, and the secondary pole point is extrapolated far away from a main pole point, so that an LDO loop is stable.
The other is that a MOS Diode (MOS Diode) M20 for self-adaptive compensation of load current is connected in parallel behind the buffer. The MOS diode grid voltage mirrors the power tube grid voltage, the current of the MOS diode is increased when the load current is increased, and then the current flowing through the buffer is also increased synchronously, the transconductance of the buffer is increased and the output resistance is reduced (the output resistance of the buffer is the reciprocal of the transconductance), so that the frequency of a secondary pole generated at the grid electrode of the power tube is increased, namely the MOS diode adaptively compensates and increases the buffer current when the load current is increased and the frequency of the secondary pole at the grid electrode of the power tube is increased, and therefore an LDO loop is stabilized when the load current is large. In addition, the MOS diode M20 is connected to the output end of the buffer M10 in a parallel feedback mode, and the parallel feedback also plays a role in reducing the output resistance of the buffer. Therefore, the MOS diode reduces the output resistance of the buffer in the aspects of current and structure, so that the output resistance of the error amplifier is attenuated, the total resistance at the grid of the power tube is smaller, the frequency of the secondary pole of the grid of the power tube is greatly increased, and the stability of the loop of the LDO in the full load current range is ensured. When the load is in no load or the required current is small, the current flowing through the buffer is reduced by the self-adaptive compensation structure, and the static power consumption of the LDO circuit is reduced while the loop is stabilized.
The schematic diagram of the LDO loop stability simulation result with 10mA load of the utility model is shown in figure 3.
Example 2:
on the basis of the foregoing embodiment 1, in order to better implement the present invention, further, the error amplifier includes a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a MOS transistor M7, a MOS transistor M8, and a MOS transistor M9;
the grid electrode of the MOS transistor M1 is connected with the power reference source VREF; the grid electrode of the MOS tube M2 is connected with the voltage division feedback network module; the grid electrode of the MOS tube M3 is connected with an auxiliary circuit, and the source electrode is grounded; the source electrodes of the MOS transistor M1 and the MOS transistor M2 are connected with the drain electrode of the MOS transistor M3;
the grid electrode of the MOS tube M8 is connected with an auxiliary circuit, the source electrode is connected with an input power VIN, and the drain electrode is connected with the source electrode of the MOS tube M6 and the drain electrode of the MOS tube M2; the grid electrode of the MOS tube M6 is connected with an auxiliary circuit, and the drain electrode is sequentially connected with the drain electrode of the MOS tube M4, the grid electrode of the MOS tube M5; the sources of the MOS transistor M4 and the MOS transistor M5 are grounded;
the source electrode of the MOS transistor M9 is connected with an input power VIN, the grid electrode of the MOS transistor M8 and the grid electrode of the MOS transistor M are connected with an auxiliary circuit together, and the drain electrode of the MOS transistor M1 and the source electrode of the MOS transistor M7 are connected; the grid electrode of the MOS tube M7 and the grid electrode of the MOS tube M6 are connected with an auxiliary circuit together, and the drain electrode of the MOS tube M7 is connected with the grid electrode of the source follower MOS tube M10 and the drain electrode of the MOS tube M5 respectively; the source of the MOS transistor M5 is grounded.
In order to better realize the utility model, further, the auxiliary circuit comprises a MOS transistor M11, a MOS transistor M12, a MOS transistor M13, a MOS transistor M14, a MOS transistor M15, a MOS transistor M16, a MOS transistor M17, and a MOS transistor M18;
the drain electrode of the MOS tube M15 is connected with a reference current Iref, and the source electrode is respectively connected with the drain electrode and the grid electrode of the MOS tube M14, the drain electrode of the MOS tube M16, the grid electrode of the MOS tube M13 and the grid electrode of the MOS tube M3; the source electrode of the MOS transistor M14, the source electrode of the MOS transistor M16, the source electrode of the MOS transistor M13 and the source electrode of the MOS transistor M3 are grounded;
the source electrode of the MOS transistor M11 is connected with an input power VIN, the drain electrode of the MOS transistor M12 is connected with the source electrode of the MOS transistor M12, and the grid electrodes of the MOS transistor M8 and the MOS transistor M9 are respectively connected with the grid electrodes; the grid electrode and the drain electrode of the MOS tube M11 are also connected through a lead;
the drain electrode of the MOS tube M12 is connected with the drain electrode of the MOS tube M13, and the grid electrodes of the MOS tube M3578 and the MOS tube M6 are respectively connected with the grid electrodes of the MOS tube M7;
the gate of the MOS transistor M15 is connected with the gate of the MOS transistor M17; the source electrode of the MOS tube M17 is connected with an input power VIN, and the drain electrode is lapped between the grid electrode of the source follower MOS tube M10 and the drain electrode of the MOS tube M7;
the gate of the MOS transistor M16 is connected to the gate of the MOS transistor M18, and the drain of the MOS transistor M18 is overlapped between the output end of the low quiescent current LDO circuit and the voltage division feedback network module.
In order to better implement the present invention, further, the voltage dividing feedback network module includes a resistor RFB1 and a resistor RFB2 connected in series to ground, and the gate of the MOS transistor M2 of the error amplifier is connected between the inductor RFB1 and the inductor RFB2 of the voltage dividing feedback network module.
In order to better implement the present invention, further, the auxiliary circuit further includes a capacitor C1, and the capacitor C1 is connected between the drain of the MOS transistor M7 and the output end of the low quiescent current LDO circuit.
Other parts of this embodiment are the same as those of embodiment 1, and thus are not described again.
The above is only the preferred embodiment of the present invention, not to the limitation of the present invention in any form, all the technical matters of the present invention all fall into the protection scope of the present invention to any simple modification and equivalent change of the above embodiments.
Claims (5)
1. A low quiescent current LDO circuit based on buffer impedance attenuation comprises a power reference source VREFThe voltage-difference adjusting power tube M0 and the voltage-dividing feedback network module are characterized by also comprising a source follower MOS tube used as a buffer and a source follower MOS tube used for self-adaptive compensationA compensation MOS diode for compensating the load current;
the power reference source VREFThe voltage division feedback network module is connected with the error amplifier and the differential pressure adjusting power tube M0;
the power reference source VREFThe sources of the error amplifier and the voltage difference adjusting power tube M0 are respectively connected with an input power supply VIN, and the output ends of the error amplifier, the auxiliary circuit and the voltage difference adjusting power tube M0 are connected to form the output end of the low quiescent current LDO circuit;
the grid electrode of the voltage difference adjusting power tube M0 is connected with the error amplifier and the auxiliary circuit, and the source follower MOS tube M10 is arranged between the grid electrode of the voltage difference adjusting power tube M0 and the error amplifier;
the compensation MOS tube M20 is arranged behind the source follower MOS tube M10 and is connected with the pressure difference adjusting power tube M0 in parallel, the source electrode of the compensation MOS tube M20 is connected with an input power supply VIN, the grid electrode of the compensation MOS tube M20 is connected with the grid electrode of the pressure difference adjusting power tube M0 and then is connected with the source electrode of the source follower MOS tube M10, and the drain electrode of the compensation MOS tube M20 is also connected with the source electrode of the source follower MOS tube M10.
2. The buffer impedance attenuation-based low quiescent current LDO circuit as recited in claim 1 wherein said error amplifier comprises MOS transistor M1, MOS transistor M2, MOS transistor M3, MOS transistor M4, MOS transistor M5, MOS transistor M6, MOS transistor M7, MOS transistor M8, MOS transistor M9;
the grid electrode of the MOS transistor M1 is connected with the power reference source VREF; the grid electrode of the MOS tube M2 is connected with the voltage division feedback network module; the grid electrode of the MOS tube M3 is connected with an auxiliary circuit, and the source electrode is grounded; the source electrodes of the MOS transistor M1 and the MOS transistor M2 are connected with the drain electrode of the MOS transistor M3;
the grid electrode of the MOS tube M8 is connected with an auxiliary circuit, the source electrode is connected with an input power VIN, and the drain electrode is connected with the source electrode of the MOS tube M6 and the drain electrode of the MOS tube M2; the grid electrode of the MOS tube M6 is connected with an auxiliary circuit, and the drain electrode is sequentially connected with the drain electrode of the MOS tube M4, the grid electrode of the MOS tube M5; the sources of the MOS transistor M4 and the MOS transistor M5 are grounded;
the source electrode of the MOS transistor M9 is connected with an input power VIN, the grid electrode of the MOS transistor M8 and the grid electrode of the MOS transistor M are connected with an auxiliary circuit together, and the drain electrode of the MOS transistor M1 and the source electrode of the MOS transistor M7 are connected; the grid electrode of the MOS tube M7 and the grid electrode of the MOS tube M6 are connected with an auxiliary circuit together, and the drain electrode of the MOS tube M7 is connected with the grid electrode of the source follower MOS tube M10 and the drain electrode of the MOS tube M5 respectively; the source of the MOS transistor M5 is grounded.
3. The buffer impedance attenuation-based low quiescent current LDO circuit as recited in claim 2 wherein said auxiliary circuit comprises MOS transistor M11, MOS transistor M12, MOS transistor M13, MOS transistor M14, MOS transistor M15, MOS transistor M16, MOS transistor M17, MOS transistor M18;
the drain electrode of the MOS tube M15 is connected with a reference current Iref, and the source electrode is respectively connected with the drain electrode and the grid electrode of the MOS tube M14, the drain electrode of the MOS tube M16, the grid electrode of the MOS tube M13 and the grid electrode of the MOS tube M3; the source electrode of the MOS transistor M14, the source electrode of the MOS transistor M16, the source electrode of the MOS transistor M13 and the source electrode of the MOS transistor M3 are grounded;
the source electrode of the MOS transistor M11 is connected with an input power VIN, the drain electrode of the MOS transistor M12 is connected with the source electrode of the MOS transistor M12, and the grid electrodes of the MOS transistor M8 and the MOS transistor M9 are respectively connected with the grid electrodes; the grid electrode and the drain electrode of the MOS tube M11 are also connected through a lead;
the drain electrode of the MOS tube M12 is connected with the drain electrode of the MOS tube M13, and the grid electrodes of the MOS tube M3578 and the MOS tube M6 are respectively connected with the grid electrodes of the MOS tube M7;
the gate of the MOS transistor M15 is connected with the gate of the MOS transistor M17; the source electrode of the MOS tube M17 is connected with an input power VIN, and the drain electrode is lapped between the grid electrode of the source follower MOS tube M10 and the drain electrode of the MOS tube M7;
the gate of the MOS transistor M16 is connected to the gate of the MOS transistor M18, and the drain of the MOS transistor M18 is overlapped between the output end of the low quiescent current LDO circuit and the voltage division feedback network module.
4. The buffer impedance degeneration-based low quiescent current LDO circuit as claimed in claim 2 or 3, wherein said voltage dividing feedback network module comprises a resistor R connected in series to groundFB1And a resistance RFB2M of the error amplifierThe grid electrode of the OS tube M2 is connected with the resistor R of the voltage division feedback network moduleFB1And a resistance RFB2In the meantime.
5. The buffer impedance degeneration-based low quiescent current LDO circuit of claim 3, wherein said auxiliary circuit further comprises a capacitor C1, said capacitor C1 is connected between the drain of MOS transistor M7 and the output of said low quiescent current LDO circuit.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113311902A (en) * | 2021-06-03 | 2021-08-27 | 兰州大学 | Low-power-consumption voltage stabilizer with small quiescent current and no off-chip capacitor and high transient response |
| CN113849033A (en) * | 2021-09-27 | 2021-12-28 | 电子科技大学 | Linear voltage stabilizer with impedance attenuation compensation |
| WO2023097965A1 (en) * | 2021-12-03 | 2023-06-08 | 深圳飞骧科技股份有限公司 | Low dropout linear regulator having fast transient response, chip, and electronic device |
| CN117075673A (en) * | 2023-10-16 | 2023-11-17 | 深圳前海深蕾半导体有限公司 | Nested loop low-dropout linear voltage regulator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113311902A (en) * | 2021-06-03 | 2021-08-27 | 兰州大学 | Low-power-consumption voltage stabilizer with small quiescent current and no off-chip capacitor and high transient response |
| CN113849033A (en) * | 2021-09-27 | 2021-12-28 | 电子科技大学 | Linear voltage stabilizer with impedance attenuation compensation |
| CN113849033B (en) * | 2021-09-27 | 2022-10-04 | 电子科技大学 | Linear voltage stabilizer with impedance attenuation compensation |
| WO2023097965A1 (en) * | 2021-12-03 | 2023-06-08 | 深圳飞骧科技股份有限公司 | Low dropout linear regulator having fast transient response, chip, and electronic device |
| CN117075673A (en) * | 2023-10-16 | 2023-11-17 | 深圳前海深蕾半导体有限公司 | Nested loop low-dropout linear voltage regulator |
| CN117075673B (en) * | 2023-10-16 | 2024-01-05 | 深圳前海深蕾半导体有限公司 | Nested loop low-dropout linear voltage regulator |
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