CN105652946A - Adaptive-bias low-load-regulation low dropout linear voltage stabilizer - Google Patents

Abstract

The invention discloses an adaptive-bias low-load-regulation low dropout linear voltage stabilizer. Voltage is output through an LDO output end. The adaptive-bias low-load-regulation low dropout linear voltage stabilizer is characterized in that the linear voltage stabilizer comprises a control voltage generating unit, a first-stage amplifier, a second-stage amplifier, a frequency compensation unit, a main power pipe, a subsidiary power pipe and an adaptive-bias and load regulation optimizing circuit. According to the low dropout linear voltage stabilizer, the adaptive-bias and load regulation optimizing circuit is added, a lower no-load current is achieved, a better effect is achieved, the bandwidth of the linear voltage stabilizer under the medium load is improved, and meanwhile the function of improving output load regulation is also achieved.

Description

A kind of adaptive-biased low-load regulation low pressure difference linear voltage regulator

Technical field

The present invention relates to field of power management, more particularly, to a kind of adaptive-biased low-load regulation low pressure difference linear voltage regulator.

Background technology

Low pressure difference linear voltage regulator has output voltage stabilization, output ripple and low, the feature of low noise, also has encapsulation volume little, the feature that outward element is few. Due to its these advantages, low pressure difference linear voltage regulator is widely used in portable electric appts, automobile electronics, industry and medical instruments and equipment etc.

For without off-chip capacitor type linear voltage regulator, with conventional linear manostat the difference is that, its dominant pole is typically in the grid of power tube, and the limit of outfan is generally time limit, when underloading or zero load, output impedance is relatively big, and non-dominant pole moves to low frequency, namely move to GBW (gain bandwidth product) direction, cause that phase margin diminishes; And when heavy duty, non-dominant pole is to high-frequency mobile, also just to moving away from GBW direction, phase margin will increase relatively. Therefore, for different loading conditions, it is necessary to study new scheme and ensure the work without off-chip capacitor type linear voltage regulator loop stability.

A kind of efficient mode is to adopt adaptive-biased technology, and namely amplifier bias current changes accordingly according to the change of load. When load is less, bias current is also smaller, and GBW value is relatively small, thus ensureing enough phase margins; Relatively big in load, non-dominant pole is when high frequency, and bigger bias current has expanded the bandwidth of system, thus enhancing the transient response of linear voltage regulator. Adaptive-biased technology due to its high current utilization rate and flexibly bandwidth adjustment mode and obtain a wide range of applications under study for action.

In the application of linear voltage regulator, the situation of load current change is very common, it is intended that manostat remains to maintain stable output when load changes, and load regulation is more low, output voltage is more little by load disturbance, more can suppress the steady state output voltage change caused by load change. Therefore, the linear voltage regulator studying low-load regulation is also a focus.

Summary of the invention

The present invention overcomes at least one defect described in above-mentioned prior art, it is provided that a kind of adaptive-biased low-load regulation low pressure difference linear voltage regulator.The present invention, by adding adaptive bias circuit at low pressure difference linear voltage regulator, improves its bandwidth under middle loading condition, also plays a part to improve output loading regulation simultaneously.

For solving above-mentioned technical problem, technical scheme is as follows:

A kind of adaptive-biased low-load regulation low pressure difference linear voltage regulator, by LDO outfan output voltage, described linear voltage regulator includes controlling voltage generating unit, first order amplifier, second level amplifier, frequency compensation unit, main power tube, secondary power tube and adaptive-biased and load regulation optimization unit, described control voltage generating unit is used for producing to control voltage Vctrl and by controlling voltage output end output, the first input end of described first order amplifier electrically connects with LDO outfan, second input is connected with the outfan controlling voltage generating unit, the outfan of first order amplifier respectively with the input of second level amplifier, the grid electrical connection of the first end of frequency compensation unit and secondary power tube, the grid of main power tube electrically connects with second level amplifier out, the source electrode of main power tube and secondary power tube connects power supply, main power tube and the secondary drain electrode of power tube and the second end of frequency compensation unit electrically connect with LDO outfan, main power tube according to load be automatically opened or closed

Described adaptive-biased and load regulation optimizes unit and first and amplifier and electrically connects, and its effect is to provide adaptive bias for first order amplifier, acts the effect optimizing LDO load regulation simultaneously.

In the preferred scheme of one, described control voltage generating unit includes PMOS MA1, MA2, MA5, MA6 and NMOS tube MA3, MA4, MB3, MB4 and electric capacity Ca, described MA1 and MA2 connects with current-mirror structure, the i.e. drain electrode of MA2, the grid of grid and MA1 connects, the source electrode of MA2 and MA1 connects power supply, the drain electrode of MA3 is connected with the drain electrode of MA1, the grid of MA3 meets reference voltage V ref, the drain electrode of MA4 is connected with the drain electrode of MA2, the grid of MA4 is connected with the drain electrode of MA5, the source electrode of MA3 and MA4 is connected with the drain electrode of MB3, the source ground of MB3 and MB4, the grid of MB3 and MB4 connect after as the first bias current sources and export bias voltage Nbias, the grid of MA6, drain electrode is connected with the drain electrode of MB4, as the control voltage output end controlling voltage generating unit, the drain electrode of MA5 is connected with the source electrode of MA6, the grid of MA5 is connected with the drain electrode of MA1, the source electrode of MA5 connects power supply, the drain electrode of the one termination MA3 of electric capacity Ca, the drain electrode of another termination MA5.

In the preferred scheme of one, described first order amplifier includes PMOS M1 and MB2, NMOS tube M2 and MB1; The source electrode of described M1 is connected with LDO outfan as first input end, M1 grid controls the control voltage output end of voltage generating unit as the second input termination, M2 source electrode is connected with M1 drain electrode, M2 grid meets bias voltage Vbias, MB1 drain electrode is connected with M1 drain electrode, MB1 source ground, MB1 grid meets bias voltage Nbias, MB2 drain electrode drains with M2 and is connected and as the outfan of first order amplifier, MB2 source electrode connects power supply, MB2 grid meets bias voltage Pbias, MB1 and MB2 all as bias current sources.

In the preferred scheme of one, described second level amplifier includes PMOS M3, M7 and M8, NMOS tube M4, M5 and M6; Described M3 grid is connected with the outfan of first order amplifier, and M3 source electrode connects power supply, and M3 drain electrode is connected with M4 drain electrode, M4 and M5 connects with current-mirror structure, i.e. M4 drain electrode, grid are connected with M5 grid, the source ground of M4 and M5, and M6 grid is connected with M1 drain electrode, M6 source ground, M6 drain electrode is connected with M7 drain electrode, and M7 and M8 connects with current-mirror structure, i.e. M7 drain electrode, grid are connected with M8 grid, the source electrode of M7 and M8 connects power supply, and M8 drain electrode is connected and as second level amplifier out with M5 drain electrode.

In the preferred scheme of one, described frequency compensation unit includes miller compensation electric capacity Cm and described M2, Cm first and terminates M2 source electrode, the second termination LDO outfan, plays frequency compensation effect.

In the preferred scheme of one, described adaptive-biased and load regulation optimizes unit and includes PMOS ML1, NMOS tube ML2, ML3 and ML4; The grid of ML1 is connected with MB2 drain electrode, ML1 source electrode connects power supply, ML1 drain electrode is connected with ML2 drain electrode, ML2, ML3 and ML4 connect with current-mirror structure, namely ML2 grid, ML2 drain electrode are connected with ML3 grid, ML4 grid, ML2 source electrode, ML3 source electrode and ML4 source ground, ML3 drain electrode is connected with M1 drain electrode, and ML4 drain electrode is connected with MA6 drain electrode.

ML1 pipe replicates the electric current of secondary power tube MP1 in proportion, provides adaptive-biased for first order amplifier, acts the effect optimizing load regulation simultaneously.

Compared with prior art, technical solution of the present invention provides the benefit that: a kind of adaptive-biased low-load regulation low pressure difference linear voltage regulator of disclosure, by LDO outfan output voltage, it is characterized in that, described linear voltage regulator includes controlling voltage generating unit, first order amplifier, second level amplifier, frequency compensation unit, main power tube, secondary power tube and adaptive-biased and load regulation optimization circuit. The low pressure difference linear voltage regulator of the present invention adds adaptive-biased and load regulation optimization circuit, there is more low no-load electric current, achieve more excellent effect, and improve linear voltage regulator bandwidth under middle loading condition, also play a part to improve output loading regulation simultaneously.

Accompanying drawing explanation

Fig. 1 is low dropout linear regulator structure schematic diagram of the present invention;

Fig. 2 is low differential voltage linear voltage stabilizer circuit of the present invention;

Fig. 3 is low pressure difference linear voltage regulator load regulation principle of optimality figure of the present invention;

Detailed description of the invention

Accompanying drawing being merely cited for property explanation, it is impossible to be interpreted as the restriction to this patent; To those skilled in the art, in accompanying drawing, some known features and explanation thereof are likely to omission and will be understood by.

Below in conjunction with drawings and Examples, technical scheme is described further.

Embodiment 1

A kind of adaptive-biased low-load regulation low pressure difference linear voltage regulator, by LDO outfan output voltage, described linear voltage regulator includes controlling voltage generating unit, first order amplifier, second level amplifier, frequency compensation unit, main power tube, secondary power tube and adaptive-biased and load regulation optimization unit, described control voltage generating unit is used for producing to control voltage Vctrl and by controlling voltage output end output, the first input end of described first order amplifier electrically connects with LDO outfan, second input is connected with the outfan controlling voltage generating unit, the outfan of first order amplifier respectively with the input of second level amplifier, the grid electrical connection of the first end of frequency compensation unit and secondary power tube, the grid of main power tube electrically connects with second level amplifier out, the source electrode of main power tube and secondary power tube connects power supply, main power tube and the secondary drain electrode of power tube and the second end of frequency compensation unit electrically connect with LDO outfan, main power tube according to load be automatically opened or closed

Described adaptive-biased and load regulation optimizes unit and first and amplifier and electrically connects, and its effect is to provide adaptive bias for first order amplifier, acts the effect optimizing LDO load regulation simultaneously.

As in figure 2 it is shown, described control voltage generating unit includes PMOS MA1, MA2, MA5, MA6 and NMOS tube MA3, MA4, MB3, MB4 and electric capacity Ca, described MA1 and MA2 connects with current-mirror structure, the i.e. drain electrode of MA2, the grid of grid and MA1 connects, the source electrode of MA2 and MA1 connects power supply, the drain electrode of MA3 is connected with the drain electrode of MA1, the grid of MA3 meets reference voltage V ref, the drain electrode of MA4 is connected with the drain electrode of MA2, the grid of MA4 is connected with the drain electrode of MA5, the source electrode of MA3 and MA4 is connected with the drain electrode of MB3, the source ground of MB3 and MB4, the grid of MB3 and MB4 connect after as the first bias current sources and export bias voltage Nbias, the grid of MA6, drain electrode is connected with the drain electrode of MB4, as the control voltage output end controlling voltage generating unit, the drain electrode of MA5 is connected with the source electrode of MA6, the grid of MA5 is connected with the drain electrode of MA1, the source electrode of MA5 connects power supply, the drain electrode of the one termination MA3 of electric capacity Ca, the drain electrode of another termination MA5.

Controlling the amplifier that voltage generating unit main body is a unit gain, Vref is reference voltage source, V_SGA6For the source gate voltage of MA6, by the known Vctrl=Vref-V of circuit connecting relation_SGA6��

As in figure 2 it is shown, described first order amplifier includes PMOS M1 and MB2, NMOS tube M2 and MB1; The source electrode of described M1 is connected with LDO outfan as first input end, M1 grid controls the control voltage output end of voltage generating unit as the second input termination, M2 source electrode is connected with M1 drain electrode, M2 grid meets bias voltage Vbias, MB1 drain electrode is connected with M1 drain electrode, MB1 source ground, MB1 grid meets bias voltage Nbias, MB2 drain electrode drains with M2 and is connected and as the outfan of first order amplifier, MB2 source electrode connects power supply, MB2 grid meets bias voltage Pbias, MB1 and MB2 all as bias current sources. The collapsible grid level amplifier altogether of M1 and M2 composition, as first order amplifier.

By circuit connecting relation it can be seen that the output Vout=Vctrl+V of LDO_SG1, adjust bias current and the breadth length ratio of M1 and MA6 so that V_SG1=V_SGA6, thus there being Vout=Vref.

As in figure 2 it is shown, described second level amplifier includes PMOS M3, M7 and M8, NMOS tube M4, M5 and M6; Described M3 grid is connected with the outfan of first order amplifier, and M3 source electrode connects power supply, and M3 drain electrode is connected with M4 drain electrode, M4 and M5 connects with current-mirror structure, i.e. M4 drain electrode, grid are connected with M5 grid, the source ground of M4 and M5, and M6 grid is connected with M1 drain electrode, M6 source ground, M6 drain electrode is connected with M7 drain electrode, and M7 and M8 connects with current-mirror structure, i.e. M7 drain electrode, grid are connected with M8 grid, the source electrode of M7 and M8 connects power supply, and M8 drain electrode is connected and as second level amplifier out with M5 drain electrode.

As in figure 2 it is shown, described frequency compensation unit includes miller compensation electric capacity Cm and M2, Cm noted earlier first terminates M2 source electrode, the second termination LDO outfan, plays frequency compensation effect.

As in figure 2 it is shown, described main power tube MP2 grid connects second level amplifier out, source electrode connects power supply, and drain electrode connects LDO outfan.

As in figure 2 it is shown, described secondary power tube MP1 grid connects first order amplifier out, source electrode connects power supply, and drain electrode connects LDO outfan.

The breadth length ratio of MP2 is tens times of MP1, and time unloaded, MP2 is in off state, and LDO is considered as dual-stage amplifier structure; Along with load is gradually increased, second level amplifier and main power tube MP2 start to activate, and when load current is more than threshold value Ion, LDO becomes third stage amplifier structure.

As in figure 2 it is shown, described adaptive-biased and load regulation optimizes unit includes PMOS ML1, NMOS tube ML2, ML3 and ML4; The grid of ML1 is connected with MB2 drain electrode, ML1 source electrode connects power supply, ML1 drain electrode is connected with ML2 drain electrode, ML2, ML3 and ML4 connect with current-mirror structure, namely ML2 grid, ML2 drain electrode are connected with ML3 grid, ML4 grid, ML2 source electrode, ML3 source electrode and ML4 source ground, ML3 drain electrode is connected with M1 drain electrode, and ML4 drain electrode is connected with MA6 drain electrode.

ML1 replicates the electric current of secondary power tube MP1 in proportion, in dual-stage amplifier state, all of load current is all provided by secondary power tube MP1, and when load current increases, first order amplifier bias current also and then increases, along with load current increases, LDO becomes third stage amplifier state, and at this moment first order amplifier bias current is substantially stationary, because unnecessary electric current is provided by main power tube MP2, the electric current of secondary power tube MP1 is basically unchanged, and ML1 electric current is also basically unchanged. ML1-ML3 introduces a positive feedback passage, but owing to the negative feedback that here ML4, MA6, M1 are formed is bigger than the ML3 positive feedback formed, so the stability of system is unaffected.

First order amplifier input pipe mutual conductance is

$g_{m1}=\sqrt{2{\mathrm{\μ}}_p{C}_{OX}(W/L)I_D}---\left(1\right)$

Wherein �� is carrier mobility, and COX is gate oxide capacitance, and W/L is pipe breadth length ratio. LDO is when two-stage or third stage amplifier state, and its GBW is

$GBW=\frac{g_{m1}}{C_m}---\left(2\right)$

When middle load, the situation of relatively light load, due to the effect of adaptive bias, gm1 and GBW increases to some extent, thus enhancing the transient response of linear voltage regulator.

Circuit connecting relation according to Fig. 2, the output Vout=Vref-V of LDO_SGA6+V_SG1, remember �� V_SG=V_SG1-V_SGA6, have Vout=Vref+ �� V_SG, when load current changes greatly, �� V_SGAlso changing, Vout also has the change of �� V, if �� V can be reduced according to loading condition_SGVariable quantity, then �� V also can reduce, and the load regulation of LDO is thus also improving.

Fig. 3 is low pressure difference linear voltage regulator load regulation principle of optimality figure of the present invention. As shown in Fig. 3 (a), at steady statue T1, Vout no better than Vref, �� V_SGAlmost nil, when load current increases suddenly, after experience transient state T2, enter again steady statue T3, Vout less �� V1 than T1 under T3 state, �� V_SGAlso less than in T1 state, LRI circuit reduces �� V according to loading condition_SGVariable quantity, increase under T3 state �� V_SGValue, Vout also increases, and adds after LRI, and the load regulation that the variable quantity of Vout is also reduced to �� V2, LDO by �� V1 improves. When load current suddenly from large to small time, situation is also similar, and as shown in Fig. 3 (b), after adding LRI, under T1 ' state, �� VSG increases to some extent, and the variable quantity of Vout is also reduced to �� V2 ' by �� V1 '.

Theoretical according to adjustment of load, the output of LDO can be expressed as:

V_out=V_ref-I_LR_{load_reg}(3)

Wherein,

$R_{load\_reg}=\frac{{\mathrm{\ΔV}}_{out}}{{\mathrm{\ΔI}}_{out}}=\frac{R_O}{1+A_{OL}}---\left(4\right)$

Wherein, Rload_reg is load regulation, RO is power tube output resistance, AOL is open-loop gain, in order to reduce the variable quantity �� V of output voltage Vout when load changes, can increasing AOL, when heavy duty, LDO is operated in third stage amplifier state, AOL is sufficiently large, so load regulation is better, when load current is less, LDO is operated in dual-stage amplifier state, AOL is also little, therefore LRI should be able to compensate the Section 2 in (3) formula, and after adding LRI, the expression formula form of Vout is:

V_out=V_ref+I_L(R��_{load_reg}-R_{load_reg})(5)

As shown in Figure 2, when LDO is operated in dual-stage amplifier state, almost all of load current is all provided by secondary power tube MP1, ML1 replicates the electric current in MP1 with the ratio of 1:M, the current mirror consisting of 1:N1:N2 ML2-ML4 can obtain adaptive bias Ia1=N1 �� IL/M, Ia2=N2 �� IL/M, Ia1 and Ia2 change V respectively_SG1And V_SGA6Value, thus dynamically control the value of output voltage Vout according to loading condition, improve the load regulation of LDO.

Assume that load current is zero, time namely Ia1 and Ia2 is zero, the source gate voltage respectively V of M1 and MA6_SG1And V_SGA6, when load current is IL, the source gate voltage of M1 and MA6 has changed �� V respectively_SG1With �� V_SGA6, have

$I_{b1}=\frac{1}{2}{\mathrm{\μC}}_{OX}{\left(\frac{W}{L}\right)}_1{(V_{GS1}-V_{TH1})}^2---\left(6\right)$

$I_{b1}+I_{a1}=\frac{1}{2}{\mathrm{\μC}}_{OX}{\left(\frac{W}{L}\right)}_1{(V_{GS1}+{\mathrm{\ΔV}}_{GS1}-V_{TH1})}^2---\left(7\right)$

By (6)-(7), have

$I_{a1}={\mathrm{\μC}}_{OX}{\left(\frac{W}{L}\right)}_{1\left(8\right)}(V_{GS1}-V_{TH1}+\frac{{\mathrm{\ΔV}}_{GS1}}{2}){\mathrm{\ΔV}}_{GS1}---\left(8\right)$

Wherein, I_b1For the quiescent bias current of M1, V_THIt it is the threshold voltage of metal-oxide-semiconductor.

In like manner have

$I_{a2}={\mathrm{\μC}}_{OX}{\left(\frac{W}{L}\right)}_{A6}(V_{GSA6}-V_{THA6}+\frac{{\mathrm{\ΔV}}_{GSA6}}{2}){\mathrm{\ΔV}}_{GSA6}---\left(9\right)$

By (8)-(9), obtain

${\mathrm{\ΔV}}_{GS1}-{\mathrm{\ΔV}}_{GSA6}\≈\frac{(N_1-N_2)\×I_L}{M\sqrt{2{\mathrm{\μC}}_{OX}{\left(\frac{W}{L}\right)}_1{I}_{b1}}}---\left(10\right)$

So in formula (5)

$R_{load\_reg}^{\′}-=\frac{(N_1-N_2)}{M\sqrt{2{\mathrm{\μC}}_{OX}{\left(\frac{W}{L}\right)}_1{I}_{b1}}}---\left(11\right)$

Adjusting the value of N1, N2, M so that the difference of R ' load_reg and Rload_reg is as far as possible little, the variable quantity �� V of Vout during load change can being reduced, thus improving the load regulation of LDO.

From analyzing above, the low pressure difference linear voltage regulator of the present invention is by adding adaptive bias circuit, realize more low no-load electric current and more excellent effect, and improve linear voltage regulator bandwidth under middle loading condition, also play a part to improve output loading regulation simultaneously.

Obviously, the above embodiment of the present invention is only for clearly demonstrating example of the present invention, and is not the restriction to embodiments of the present invention. For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description. Here without also cannot all of embodiment be given exhaustive. All any amendment, equivalent replacement and improvement etc. made within the spirit and principles in the present invention, should be included within the protection domain of the claims in the present invention.

Claims (6)

1. low-load regulation low pressure difference linear voltage regulator one kind adaptive-biased, by LDO outfan output voltage, it is characterized in that, described linear voltage regulator includes controlling voltage generating unit, first order amplifier, second level amplifier, frequency compensation unit, main power tube, secondary power tube and adaptive-biased and load regulation optimization unit, described control voltage generating unit is used for producing to control voltage Vctrl and by controlling voltage output end output, the first input end of described first order amplifier electrically connects with LDO outfan, second input is connected with the outfan controlling voltage generating unit, the outfan of first order amplifier respectively with the input of second level amplifier, the grid electrical connection of the first end of frequency compensation unit and secondary power tube, the grid of main power tube electrically connects with second level amplifier out, the source electrode of main power tube and secondary power tube connects power supply, main power tube and the secondary drain electrode of power tube and the second end of frequency compensation unit electrically connect with LDO outfan, main power tube according to load be automatically opened or closed

Described adaptive-biased and load regulation optimizes unit and first and amplifier and electrically connects, and its effect is to provide adaptive bias for first order amplifier, acts the effect optimizing LDO load regulation simultaneously.

2. adaptive-biased low-load regulation low pressure difference linear voltage regulator according to claim 1, it is characterized in that, described control voltage generating unit includes PMOS MA1, MA2, MA5, MA6 and NMOS tube MA3, MA4, MB3, MB4 and electric capacity Ca, described MA1 and MA2 connects with current-mirror structure, the i.e. drain electrode of MA2, the grid of grid and MA1 connects, the source electrode of MA2 and MA1 connects power supply, the drain electrode of MA3 is connected with the drain electrode of MA1, the grid of MA3 meets reference voltage V ref, the drain electrode of MA4 is connected with the drain electrode of MA2, the grid of MA4 is connected with the drain electrode of MA5, the source electrode of MA3 and MA4 is connected with the drain electrode of MB3, the source ground of MB3 and MB4, the grid of MB3 and MB4 connect after as the first bias current sources and export bias voltage Nbias, the grid of MA6, drain electrode is connected with the drain electrode of MB4, as the control voltage output end controlling voltage generating unit, the drain electrode of MA5 is connected with the source electrode of MA6, the grid of MA5 is connected with the drain electrode of MA1, the source electrode of MA5 connects power supply,The drain electrode of the one termination MA3 of electric capacity Ca, the drain electrode of another termination MA5.

3. adaptive-biased low-load regulation low pressure difference linear voltage regulator according to claim 2, it is characterised in that described first order amplifier includes PMOS M1 and MB2, NMOS tube M2 and MB1; The source electrode of described M1 is connected with LDO outfan as first input end, M1 grid controls the control voltage output end of voltage generating unit as the second input termination, M2 source electrode is connected with M1 drain electrode, M2 grid meets bias voltage Vbias, MB1 drain electrode is connected with M1 drain electrode, MB1 source ground, MB1 grid meets bias voltage Nbias, MB2 drain electrode drains with M2 and is connected and as the outfan of first order amplifier, MB2 source electrode connects power supply, MB2 grid meets bias voltage Pbias, MB1 and MB2 all as bias current sources.

4. adaptive-biased low-load regulation low pressure difference linear voltage regulator according to claim 3, it is characterised in that described second level amplifier includes PMOS M3, M7 and M8, NMOS tube M4, M5 and M6; Described M3 grid is connected with the outfan of first order amplifier, and M3 source electrode connects power supply, and M3 drain electrode is connected with M4 drain electrode, M4 and M5 connects with current-mirror structure, i.e. M4 drain electrode, grid are connected with M5 grid, the source ground of M4 and M5, and M6 grid is connected with M1 drain electrode, M6 source ground, M6 drain electrode is connected with M7 drain electrode, and M7 and M8 connects with current-mirror structure, i.e. M7 drain electrode, grid are connected with M8 grid, the source electrode of M7 and M8 connects power supply, and M8 drain electrode is connected and as second level amplifier out with M5 drain electrode.

5. adaptive-biased low-load regulation low pressure difference linear voltage regulator according to claim 3, it is characterized in that, described frequency compensation unit includes miller compensation electric capacity Cm and described M2, Cm first and terminates M2 source electrode, second termination LDO outfan, plays frequency compensation effect.

6. adaptive-biased low-load regulation low pressure difference linear voltage regulator according to claim 3, it is characterised in that described adaptive-biased and load regulation optimizes unit and includes PMOS ML1, NMOS tube ML2, ML3 and ML4; The grid of ML1 is connected with MB2 drain electrode, ML1 source electrode connects power supply, ML1 drain electrode is connected with ML2 drain electrode, ML2, ML3 and ML4 connect with current-mirror structure, namely ML2 grid, ML2 drain electrode are connected with ML3 grid, ML4 grid, ML2 source electrode, ML3 source electrode and ML4 source ground, ML3 drain electrode is connected with M1 drain electrode, and ML4 drain electrode is connected with MA6 drain electrode.