CN212659300U

CN212659300U - Low-voltage starting circuit for buzzer

Info

Publication number: CN212659300U
Application number: CN201922032907.7U
Authority: CN
Inventors: 张怀东
Original assignee: Wuxi Shiding Electronic Technology Co ltd
Current assignee: Wuxi Shiding Electronic Technology Co ltd
Priority date: 2019-11-22
Filing date: 2019-11-22
Publication date: 2021-03-05
Anticipated expiration: 2029-11-22

Abstract

The utility model provides a be used for bee calling organ low voltage starting circuit, including diode D1, PMOS pipe P1, PMOS pipe control circuit, power-on reset circuit, oscillator, frequency divider. The positive electrode of D1 is connected with power supply VDD, the negative electrode is connected with signal line VCC, the grid electrode of P1 is connected with output G1 of PMOS tube control circuit, the source electrode is connected with power supply VDD, the drain electrode is connected with signal line VCC, signal line VCC supplies power for PMOS tube control circuit, power-on reset circuit, oscillator and frequency divider, the output of power-on reset circuit is respectively connected with the input of PMOS tube control circuit, oscillator and frequency divider, the output of oscillator is connected with the input of frequency divider, output G2 of frequency divider is connected with the input of PMOS tube control circuit, and output G3 of frequency divider is connected with the grid electrode of buzzer driving tube. The PMOS pipe P1 is opened when the buzzer driving pipe is cut off, the circuit plays a role of starting the circuit at low voltage, and the circuit has the advantages of low cost and low working voltage.

Description

Low-voltage starting circuit for buzzer

Technical Field

The utility model relates to a buzzer circuit field, concretely relates to be used for buzzer low-voltage starting circuit and buzzer driver chip.

Background

As shown in fig. 6, in the conventional driving circuit for the buzzer, in order to prevent the electromagnetic coil from excessively reducing the power supply inside the chip when conducting, a diode D1 is added between the power supply and the power supply signal line VCC of the internal circuit, the power supply of the circuit needs to pass through a diode D1, the diode D1 can be regarded as a starting device of the buzzer circuit, the power supply has a relatively large voltage drop through the diode, which is about 0.5-0.7V, the general buzzer requires to operate when the power supply is below 1.5V, when the power supply is at 1.5V, the power supply voltage of the oscillator and other circuits is about 1V after the power supply is reduced through the diode, and under the voltage, the oscillator is difficult to operate or is not normal to operate.

SUMMERY OF THE UTILITY MODEL

The utility model provides a be used for bee calling organ low voltage starting circuit, when mains voltage is lower to solve the problem that the oscillator is difficult to normal work.

In order to solve the above technical problem, the utility model provides a be used for bee calling organ low voltage starting circuit, as shown in fig. 1, including diode D1, PMOS pipe P1, PMOS pipe control circuit, go up electric reset circuit, oscillator, frequency divider. The positive electrode of the diode D1 is connected with a power supply VDD, the negative electrode of the diode D1 is connected with a signal line VCC, the grid electrode of a PMOS tube P1 is connected with a PMOS tube control circuit output G1, the source electrode of a PMOS tube P1 is connected with the power supply VDD, the drain electrode of the PMOS tube P1 is connected with the signal line VCC, the substrate of a PMOS tube P1 is suspended or selectively connected with the signal line VCC with higher voltage in the power supply VDD, or the substrate of a PMOS tube P1 is connected with the signal line VCC, the signal line VCC supplies power to the PMOS tube control circuit, a power-on reset circuit, an oscillator and a frequency divider, the output P of the power-on reset circuit is respectively connected with the inputs of the PMOS tube control circuit, the oscillator and the frequency divider, the output F of the oscillator is connected with the input of the frequency divider, the output G2 is connected with the input of.

As shown in fig. 1, when the circuit is just powered on, the power-on reset circuit outputs signal P to make the divider output G3 be at low level, the divider output G3 be at low level to make the buzzer driving tube turn off, the power-on reset circuit outputs signal P also makes the PMOS transistor control circuit output signal G1 be at low level, the PMOS transistor control circuit outputs signal G1 be at low level to make the PMOS transistor P1 be turned on, so as to reduce the voltage drop across diode D1, reduce the voltage drop across diode D1, and increase the VCC voltage of the signal line, which is helpful for the normal operation of the oscillator and the divider. Before the buzzer driving tube is conducted from power-on, the PMOS tube P1 can be conducted all the time or conducted for a period of time to complete charging of the signal line VCC, after the buzzer driving tube is conducted once, the PMOS tube P1 can be closed all the time, the PMOS tube P1 can be conducted when the buzzer driving tube is cut off by the PMOS tube control circuit output G1, the PMOS tube P1 is cut off when the buzzer driving tube is conducted by the PMOS tube control circuit output G1, and the buzzer driving tube works for a plurality of periods or works all the time, and is specifically determined by an application environment.

Preferably, there is at least one diode.

Preferably, the oscillator may not be controlled by the power-on reset circuit output P.

Preferably, the divider output G2 and the divider output G3 may be the same signal line.

Preferably, the oscillator frequency is such that, when appropriate, the divider can be eliminated and both the divider output G2 and the divider output G3 are oscillator outputs.

Preferably, the substrate of the PMOS transistor P1 is connected to the signal line VCC or selectively connected to the higher voltage potential of the signal line VCC and the power supply VDD, or floating.

The utility model discloses the beneficial effect who brings: the utility model provides a pair of be used for bee calling organ low-voltage starting circuit through opening the PMOS pipe between power cord and the inside power supply signal line when bee calling organ drive tube ends to improve the supply voltage of internal circuit module, play the effect that the circuit low-voltage starts and normally works. The circuit has the advantages of low cost and low working voltage.

Drawings

Fig. 1 is a schematic structural diagram of the low-voltage starting circuit for the buzzer of the present invention.

Fig. 2 is a schematic diagram of a low-voltage starting circuit for a buzzer according to a first embodiment of the present invention.

Fig. 3 is a schematic timing diagram of a low voltage start circuit for a buzzer according to a first embodiment of the present invention.

Fig. 4 is a schematic diagram of a low voltage start circuit for a buzzer according to a second embodiment of the present invention.

Fig. 5 is a timing diagram of a low voltage start circuit for a buzzer according to a second embodiment of the present invention.

Fig. 6 is a schematic diagram of the background art.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.

As shown in fig. 1, the utility model provides a pair of be used for bee calling organ low voltage starting circuit, including diode D1, PMOS pipe P1, PMOS pipe control circuit, power-on reset circuit, oscillator, frequency divider. The diode D1 has an anode connected to a power supply VDD, a cathode connected to a signal line VCC, a gate of a PMOS transistor P1 connected to the output G of the PMOS transistor control circuit, a source connected to the power supply VDD, a drain connected to the signal line VCC, the signal line VCC supplies power to the PMOS transistor control circuit, a power-on reset circuit, an oscillator and a frequency divider, the output P of the power-on reset circuit is connected to the inputs of the PMOS transistor control circuit, the oscillator and the frequency divider respectively, the output F of the oscillator is connected to the input of the frequency divider, the output G2 of the frequency divider is connected to the input of the PMOS transistor control circuit, and the output G3 of the frequency divider is connected to. In practical application, the oscillator may not be controlled by the output P of the power-on reset circuit, the divider output G2 and the divider output G3 may be the same signal line, and the substrate of the PMOS transistor P1 is connected to the signal line VCC or selectively connected to the higher voltage potential of the signal line VCC and the power supply VDD, or floating.

The first embodiment of the present invention, as shown in fig. 2: the power-on reset circuit comprises a diode D1, a PMOS tube P1, a PMOS tube control circuit, a power-on reset circuit, an oscillator and a frequency divider. The positive electrode of the diode D1 is connected with a power supply VDD, the negative electrode of the diode D1 is connected with a signal line VCC, the grid electrode of a PMOS tube P1 is connected with the output G of the PMOS tube control circuit, the source electrode of a PMOS tube P1 is connected with the power supply VDD, the drain electrode of the PMOS tube P1 is connected with the signal line VCC, the substrate of the PMOS tube P1 is connected with the signal line VCC, the signal line VCC supplies power to the PMOS tube control circuit, the power-on reset circuit, the oscillator and the frequency divider, the output P of the power-on reset circuit is respectively connected with the inputs of the PMOS tube control circuit, the oscillator and the frequency divider, the output F of the oscillator is connected with the input of the frequency divider, the output G2 of the frequency divider is connected with the input. The signal wire VCC is externally connected with a capacitor C1, and the other end of the external capacitor C1 is connected with the ground wire.

A working sequence of the second embodiment of the present invention is shown in fig. 3, with reference to fig. 2, when the power supply VDD is powered on, the power supply VDD charges the signal line VCC through a diode D1, the power-on reset circuit starts working, the power-on reset circuit output P is high level, the power-on reset circuit output P resets the oscillator and the frequency divider, the frequency divider output G2 is low level, the PMOS transistor control circuit output G1 is low level when the power-on reset circuit output P is high level, so that the PMOS transistor P1 is turned on, the PMOS transistor P1 charges the external capacitor C1, the signal line VCC potential further rises to provide high enough voltage for the internal circuits such as the oscillator and the frequency divider to ensure the normal operation of the circuit, after a period of time, the power-on reset circuit output P is changed from high level to low level, the PMOS transistor control circuit output G1 keeps low level unchanged, the oscillator and the frequency divider start working, and after a period of time, the output G2 of the frequency divider is at a high level, the high level of the output G2 of the frequency divider enables the output G1 of the MOS tube control circuit to be inverted to be at a high level, the P1 of the PMOS tube is cut off, and after a period of time, the output G3 of the frequency divider is at a high level, and the buzzer driving tube starts to work.

The utility model discloses an among other working sequences of first embodiment, it can be the low level during power-on reset output P resets, and not necessarily be the high level during power-on reset output P resets as shown in fig. 3, frequency divider output G2 can be the high level during resetting, and not necessarily be the low level during resetting as shown in fig. 3 frequency divider output G2, but the effect that plays is the same when, power-on reset during PMOS pipe P1 switches on promptly, PMOS pipe P1 switches on when the buzzer driving tube switches on and ends.

The second embodiment of the present invention is shown in fig. 4: the power-on reset circuit comprises a diode D1, a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube control circuit, a power-on reset circuit, an oscillator and a frequency divider. Wherein, the anode of the diode D1 is connected to the power VDD, the cathode of the diode D1 is connected to the signal line VCC, the gate of the PMOS tube P1 is connected to the PMOS tube control circuit output G, the source of the PMOS tube P1 is connected to the power VDD, the drain of the PMOS tube P1 is connected to the signal line VCC, the substrate of the PMOS tube P1 is connected to the signal line b1, the gate of the PMOS tube P2 is connected to the signal line VCC, the source of the PMOS tube P2 is connected to the power VDD, the drain of the PMOS tube P2 is connected to the signal line b1, the substrate of the PMOS tube P2 is connected to the signal line b1, the gate of the PMOS tube P3 is connected to the power VDD, the source of the PMOS tube P3 is connected to the signal line VCC, the drain of the PMOS tube P3 is connected to the signal line b1, the substrate of the PMOS tube P3 is connected to the signal line b1, the signal line VCC is used for powering the PMOS tube control circuit, the power supply to the power supply, the divider output G2 is connected to the buzzer driver gate. The signal wire VCC is externally connected with a capacitor C1, and the other end of the external capacitor C1 is connected with the ground wire.

The utility model discloses a second embodiment a work time sequence wherein is shown in fig. 5, combine fig. 4, reset cycle means power-on reset cycle in the picture, reset cycle on power-on, the PMOS pipe control circuit output G1 is the low level, PMOS pipe P1 switches on, PMOS pipe P1 charges to outer hanging electric capacity C1, signal line VCC electric potential further rises, for the oscillator, internal circuits such as frequency divider provide enough high voltage in order to guarantee the normal work of circuit, in frequency divider working period, when frequency divider output G2 is the low level, PMOS pipe P1 switches on, PMOS pipe P1 charges to outer hanging electric capacity C1, when frequency divider output G2 is the high level, PMOS pipe P1 ends, so reciprocal.

The utility model discloses an among other working sequences of second embodiment, at the frequency divider working period, PMOS pipe P1 can only switch on when frequency division work first cycle frequency divider output G2 is the low level, also can only switch on when a plurality of cycle frequency divider output G2 is the low level before the frequency division work, specifically depending on electric capacity size and application condition.

To sum up, the utility model provides a pair of be used for bee calling organ low voltage starting circuit, through the on-time of the PMOS pipe between control and power cord and the inside power supply signal line, reduce the voltage difference between power cord and the inside power supply signal line for bee calling organ can normally work under the voltage than low, the utility model discloses the circuit has operating voltage low, advantage with low costs.

The above description is only an example of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. The utility model provides a be used for buzzer low voltage starting circuit, characterized in that, including diode D1, PMOS pipe P1, PMOS pipe control circuit, power-on reset circuit, the oscillator, the frequency divider, wherein, diode D1 positive pole is connected power VDD, diode D1 negative pole connects signal line VCC, PMOS pipe P1 grid connection PMOS pipe control circuit output G1, PMOS pipe P1 source connection power VDD, PMOS pipe P1 drain electrode connects signal line VCC, signal line VCC gives PMOS pipe control circuit, power-on reset circuit, the oscillator, the power supply of frequency divider, power-on reset circuit output P connects the input of PMOS pipe control circuit, oscillator, frequency divider respectively, oscillator output F is connected to the input of frequency divider, frequency divider output G2 connects the input of PMOS pipe control circuit, frequency divider output G3 is connected to the buzzer drive tube grid.

2. The low voltage start-up circuit for buzzer of claim 1, wherein said PMOS transistor control circuit output G1 turns on PMOS transistor P1 when the buzzer driving transistor is turned off, and PMOS transistor control circuit output G1 turns off PMOS transistor P1 when the buzzer driving transistor is turned on.

3. The low voltage start-up circuit for buzzer of claim 1, wherein said PMOS transistor P1 has three substrate connections: the connecting signal line VCC, the selective connecting signal line VCC and the higher voltage potential of the power supply VDD are suspended.

4. The low voltage start circuit for a buzzer as claimed in claim 1, wherein said diode D1 is at least one.

5. The low voltage start circuit for a buzzer of claim 1, wherein said oscillator may not be controlled by a power-on-reset circuit output P.