CN209625154U - A kind of SOC electric power management circuit - Google Patents
A kind of SOC electric power management circuit Download PDFInfo
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- CN209625154U CN209625154U CN201920625786.4U CN201920625786U CN209625154U CN 209625154 U CN209625154 U CN 209625154U CN 201920625786 U CN201920625786 U CN 201920625786U CN 209625154 U CN209625154 U CN 209625154U
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- power supply
- nmos tube
- electricity consumption
- phase inverter
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The utility model discloses a kind of SOC electric power management circuits, including register cell, driving unit, wherein the input of the output Q connection driving unit of register cell；Enable signal EN outside the input connection of register cell, when enable signal EN is high level, the output Q of register cell is high level, and driving unit controls VDDA power supply to electricity consumption module for power supply；Register cell receives the SHUTDOWN signal of electricity consumption module output, and when enable signal EN is low level, SHUTDOWN signal is high level, output Q is low level, and driving unit control VDDA power supply stops to electricity consumption module for power supply.The utility model issues the power supply of signal-off itself using the electricity consumption module of SOC system, and power consumption is effectively reduced.
Description
Technical field
The utility model belongs to chip technology field, more specifically to a kind of SOC electric power management circuit.
Background technique
In SOC design, since chip-scale constantly becomes larger, line width constantly becomes smaller, and leakage current becomes very considerable.Together
When, due to increasing for functional module, the module that wouldn't be used also becomes very much, can also consume many electric currents, super low-power consumption is allowed to set
Meter becomes difficult.How the module that wouldn't be used reliably easily is opened and closed, and be allowed to least in power-consuming, becomes increasingly to weigh
It wants.
If publication date is on July 4th, 2012, Publication No. " CN102545574A ", patent name is a kind of " SOC chip
Low-power dissipation power supply network design method " patent propose a kind of solution, by control power supply apparatus, complete chip not
With the control that electric power network is switched on and off, to reduce chip reset electric current.
For another example publication date is on May 29th, 2018, and Publication No. " CN108089689A ", patent name is " a kind of small-sized
The patent of SOC super low-power consumption control circuit and method " proposes another solution, is existed by the way that low power consumption control module is arranged
When SOC system needs to enter idle state, pass through low power consumption control module on hardware for the electricity of logic circuitry feeder ear
Pressure value is reduced to the data mode that can only be kept in logic circuitry, simultaneously closes off the clock source in logic circuitry, from
And logic dynamic power consumption is eliminated, and electricity leakage power dissipation is preferably minimized.
Different from above-mentioned solution, the problem excessive for power consumption in SOC system, the utility model provides another
The solution of kind thinking.
Summary of the invention
1. to solve the problems, such as
For the excessive problem of the power consumption of SOC system in the prior art, the utility model provides a kind of SOC power management
Circuit.
2. technical solution
To solve the above-mentioned problems, technical solution used by the utility model is as follows: a kind of SOC electric power management circuit,
For controlling the power supply of electricity consumption module, including register cell, driving unit, wherein the output Q connection of the register cell
The input of driving unit；
Enable signal EN outside the input connection of the register cell, when enable signal EN is high level, deposit
The output Q of device unit is high level, and the driving unit controls VDDA power supply to electricity consumption module for power supply；Register cell, which receives, to be used
The SHUTDOWN signal of electric module output, when enable signal EN is low level, SHUTDOWN signal is high level, output Q is
Low level, the driving unit control VDDA power supply stop to electricity consumption module for power supply.
When opening electricity consumption module, external enable signal EN is high level, and the output Q of register cell is high level, should
Output signal Q VDDA after over-drive unit is powered, and is electricity consumption module for power supply；
When closing electricity consumption module, external enable signal EN is low level, and the output Q of register cell keeps high level shape
State, at this moment electricity consumption module generates SHUTDOWN signal, the output Q of register cell is become low level, low level is through overdriving
Power vd DA is become into low level, the power-off of electricity consumption module after unit.
Further, the utility model further includes reset unit, and the reset unit is used to compare the voltage of VDDA power supply
With the size of reference voltage, when the voltage of VDDA power supply is lower than reference voltage, reset unit generates reset signal and gives electricity consumption mould
Block, the electricity consumption module resets；After the voltage of VDDA power supply is higher than reference voltage, reset unit not output reset signal is used
Electric module enters normal operating conditions.
Further, the reset unit includes voltage comparator C, the input connection VDDA electricity of the voltage comparator C
Source and reference voltage module, output connection electricity consumption module.When just starting power supply, VDDA starts output voltage but voltage is in
When ramp-up period, the voltage of VDDA output is lower than reference voltage, and VDDA is unable to normal power supply at this time, and voltage comparator C output is multiple
Position signal resets it to electricity consumption module；When the voltage of VDDA be in stabilization can normal power supply state when, the electricity of VDDA
Pressure is higher than reference voltage, and just no longer output reset signal, electricity consumption module start normal working condition to voltage comparator C at this time.
Further, the register cell includes filtering wave by prolonging time circuit BUF1, phase inverter INV2 and INV3, NMOS tube N2
And N3, the input terminal of external enable signal EN connection filtering wave by prolonging time circuit BUF1, the output end connection of filtering wave by prolonging time circuit BUF1
The grid of NMOS tube N3, the source electrode ground connection of NMOS tube N3, drain electrode meet input and the phase inverter INV3 of phase inverter INV2 respectively
On the one hand output, the output of phase inverter INV2 connect the input of phase inverter INV3, on the other hand go back while connecting the leakage of NMOS tube N2
The input of pole and driving unit, the source electrode ground connection of NMOS tube N2, grid receive the SHUTDOWN signal of electricity consumption module output.
When opening electricity consumption module, enable signal EN sets high level, beats NMOS tube N3 by filtering wave by prolonging time circuit BUF1
Open, the drain electrode of NMOS tube N3 exports low level, then passes through phase inverter INV2, and the output Q of INV2 is high level, then using
The NOT gate of phase inverter INV4 and PMOS tube P1 and NMOS tube N1 composition, output high level open power vd DA, power vd DA
Voltage comparator C is given simultaneously with the voltage of reference voltage module, when just having started power supply, VDDA is begun at voltage but voltage
When ramp-up period, the voltage of VDDA output is lower than reference voltage, and VDDA is unable to normal power supply, voltage comparator C output at this time
Reset signal resets it to electricity consumption module；When the voltage of VDDA be in stabilization can normal power supply state when, VDDA's
Voltage is higher than reference voltage, and just no longer output reset signal, electricity consumption module start the shape that normally works to voltage comparator C at this time
State.
After closing electricity consumption module completion corresponding function, the power supply of oneself can be closed by SHUTDOWN signal, reach drop
The effect of low-power consumption.Detailed process are as follows: enable signal EN first sets low level, exports after filtering wave by prolonging time circuit BUF1 at this time
Signal or low level, NMOS tube N3 are closed, and for phase inverter INV3 since its register functions still exports low level signal, this is low
Level signal exports Q or high level after phase inverter INV2；At this moment electricity consumption module generates SHUTDOWN signal, NMOS tube N2
Conducting, the output Q of INV2 are forced to become low level, and low level successively passes through phase inverter INV4 and PMOS tube P1 and NMOS tube N1
Low level is exported after the NOT gate of composition, power vd DA is closed, the power-off of electricity consumption module.
In the present invention, phase inverter INV2 and INV3 is the weaker phase inverter of output driving, in this way in phase inverter
It, can be strong by the output Q of INV2 since drain electrode output is low level after NMOS tube N2 conducting when the output Q of INV2 is high level
System becomes low level, and when enable signal EN is high level, NMOS tube N3 can force the output phase inverter INV3 to drag down；When
When cut-off signals SHUTDOWN is high level, NMOS tube N2 can force the output phase inverter INV2 to drag down, if phase inverter
The stronger words of INV2 and INV3 output driving, not only cannot achieve the function of needs, but also will lead to device failure.
Further, the driving unit includes phase inverter INV4, PMOS tube P1 and NMOS tube N1, wherein PMOS tube P1
Source electrode connect power supply, the source electrode ground connection of NMOS tube N1, the grid of output connection the PMOS tube P1 and NMOS tube N1 of phase inverter INV4,
Driving signal after PMOS tube P1 is connected with the drain electrode of NMOS tube N1, as VDDA power supply；The output Q of the register cell connects
Connect the input of phase inverter INV4.When the output of driving unit is high level, VDDA has power supply output；Otherwise, non-transformer exports.
Further, the driving unit includes phase inverter INV4, PMOS tube P1 and NMOS tube N1, wherein PMOS tube P1
Source electrode connect power supply, the source electrode ground connection of NMOS tube N1, the grid of output connection the PMOS tube P1 and NMOS tube N1 of phase inverter INV4,
Driving signal after PMOS tube P1 is connected with the drain electrode of NMOS tube N1, as VDDA power supply；The output Q of the register cell connects
Connect the input of phase inverter INV4.
In the present invention, electricity consumption module refer in a circuit system power supply in need operational module.
3. beneficial effect
(1) the utility model can issue the power supply of signal-off itself using the electricity consumption module of SOC system, be effectively reduced
The power consumption of entire SOC system；
(2) the utility model structure is simple, and design is rationally, easily fabricated.
Detailed description of the invention
Fig. 1 is the module frame chart of the utility model；
Fig. 2 is the operating status schematic diagram of the utility model.
Specific embodiment
The utility model is further described below combined with specific embodiments below.
As depicted in figs. 1 and 2, the utility model specifically includes that register cell, driving unit and reset unit, wherein
Register cell includes phase inverter INV2 and INV3, filtering wave by prolonging time circuit BUF1, NMOS tube N2 and N3, external enable signal EN company
Connect the input terminal of filtering wave by prolonging time circuit BUF1, the grid of the output end connection NMOS tube N3 of filtering wave by prolonging time circuit BUF1, NMOS tube
The source electrode of N3 is grounded, and drain electrode meets the input of phase inverter INV2 and the output of phase inverter INV3, one side of output of phase inverter INV2
Face connects the input of phase inverter INV3, on the other hand also while the drain electrode for connecting NMOS tube N2 and the phase inverter in driving unit
The input of INV4, the source electrode ground connection of NMOS tube N2, grid connect the SHUTDOWN signal of electricity consumption module output.
Driving unit includes phase inverter INV4, PMOS tube P1 and NMOS tube N1, wherein the leakage of PMOS tube P1 and NMOS tube N1
Extremely it is connected, grid is also connected, and the source electrode of PMOS tube P1 connects power supply, and the source electrode ground connection of NMOS tube N1 forms a NOT gate, phase inverter
The grid of output connection the PMOS tube P1 and NMOS tube N1 of INV4, the drain electrode of PMOS tube P1 and NMOS tube N1 are as driving unit
Output end carrys out output signal control power vd DA to electricity consumption module for power supply or power-off.
Reset unit includes voltage comparator C, and the output of voltage comparator connects electricity consumption module, and power vd DA connects voltage ratio
Compared with the input terminal of device C, the voltage of itself and the output of reference voltage module is compared by voltage comparator C, and then output resets letter
Number it is connected to electricity consumption module.
Specific workflow are as follows: when opening electricity consumption module, enable signal EN sets high level, by filtering wave by prolonging time circuit
BUF1 opens NMOS tube N3, and the drain electrode of NMOS tube N3 exports low level, then passes through phase inverter INV2, and the output Q of INV2 becomes
For high level, the NOT gate then formed using phase inverter INV4 and PMOS tube P1 and NMOS tube N1 exports high level, control
Power vd DA is opened, and the reference voltage of power vd DA and the generation of reference voltage module gives voltage comparator C simultaneously, just starts to power
When, when the voltage of power vd DA is in ramp-up period, the voltage of VDDA output is lower than reference voltage, and VDDA cannot be at this time
Electricity consumption module normal power supply, voltage comparator C output reset signal reset it to electricity consumption module；At the voltage of VDDA
In stabilization can normal power supply state when, the voltage of VDDA is higher than reference voltage, and just no longer output resets voltage comparator C at this time
Signal, electricity consumption module start normal working condition.
After electricity consumption module completes corresponding function, the power supply of oneself can be closed by SHUTDOWN signal, reach reduction function
The effect of consumption.At this point, enable signal EN first sets low level, the signal that is exported after filtering wave by prolonging time circuit BUF1 at this time or low
Level, NMOS tube N3 are closed, and phase inverter INV3 is since its register functions exports low level signal, and the low level signal is by anti-
Q or high level are exported after phase device INV2；Electricity consumption module generates SHUTDOWN signal, NMOS tube N2 conducting, the output Q quilt of INV2
Pressure becomes low level, and low level successively passes through phase inverter INV4 and PMOS tube P1 and the NOT gate of NMOS tube N1 composition exports later
Low level turns off power vd DA, and electricity consumption module realizes that power supply is closed.
In the present invention, phase inverter INV2 and INV3 is the weaker phase inverter of output driving, in this way in phase inverter
It is low level since its drain electrode is output to Q after NMOS tube N2 conducting when the output Q of INV2 is high level, it can be by INV2's
Output Q pressure becomes low level；When enable signal EN is high level, regardless of the output of original INV3 is high or low, NMOS tube
N3 can force the output phase inverter INV3 to drag down；When cut-off signals SHUTDOWN is high level, regardless of original INV2
Output be it is high or low, NMOS tube N2 can force the output phase inverter INV2 to drag down, if phase inverter INV2 and INV3 is defeated
Stronger words are driven out, then cannot achieve the function of needs, and will lead to device failure.
The utility model also provides a kind of power output control method simultaneously, comprising the following steps:
When enable signal EN is high level, register cell exports high level signal to driving unit, and the driving is single
Member controls VDDA power supply to electricity consumption module for power supply；VDDA supply voltage and reference voltage are compared by reset unit, if VDDA
Supply voltage is lower than reference voltage, then output reset signal gives electricity consumption module, electricity consumption module resets.
After electricity consumption module completes work, register cell receives the SHUTDOWN signal of electricity consumption module output, when enabled
When signal EN is low level, register cell exports low level to driving unit, and the driving unit control VDDA power supply stops
To electricity consumption module for power supply.
Electricity consumption module is that patent provides the target of power supply in this patent, refers to that institute is in need in a circuit system
The operational module of power supply, it does not include providing cut-off signals SHUTDOWN in patent.
Schematically the utility model is created above and embodiments thereof are described, description is not limiting,
Without departing substantially from the spirit or essential characteristics of the utility model, it can realize that this is practical new in other specific forms
Type.Shown in the drawings is also one of the embodiments of the present invention, and actual structure is not limited to this, claim
In any appended drawing reference should not limit the claims involved.So if those skilled in the art are opened by it
Show, in the case where not departing from this creation objective, not inventively design frame mode similar with the technical solution and
Embodiment should belong to the protection scope of this patent.In addition, one word of " comprising " is not excluded for other elements or step, before the component
"one" word be not excluded for including " multiple " element.The multiple element stated in claim to a product can also be by a member
Part is implemented through software or hardware.The first, the second equal words are used to indicate names, and are not offered as any specific suitable
Sequence.
Claims (6)
1. a kind of SOC electric power management circuit, for controlling the power supply of electricity consumption module, it is characterised in that: including register cell, drive
Moving cell, wherein the input of the output Q connection driving unit of the register cell；
Enable signal EN outside the input connection of the register cell, when enable signal EN is high level, register list
The output Q of member is high level, and the driving unit controls VDDA power supply to electricity consumption module for power supply；Register cell receives electricity consumption mould
The SHUTDOWN signal of block output, when enable signal EN is low level, SHUTDOWN signal is high level, output Q is low electricity
Flat, the driving unit control VDDA power supply stops to electricity consumption module for power supply.
2. SOC electric power management circuit according to claim 1, it is characterised in that: further include reset unit, the reset is single
Member, when the voltage of VDDA power supply is lower than reference voltage, is resetted for comparing the voltage of VDDA power supply and the size of reference voltage
Unit generates reset signal and gives electricity consumption module, the electricity consumption module resets；It is multiple after the voltage of VDDA power supply is higher than reference voltage
Output reset signal, electricity consumption module do not enter normal operating conditions to bit location.
3. SOC electric power management circuit according to claim 2, it is characterised in that: the reset unit includes that voltage compares
The input connection VDDA power supply and reference voltage module of device C, the voltage comparator C, output connection electricity consumption module.
4. SOC electric power management circuit according to claim 1,2 or 3, it is characterised in that: the register cell includes prolonging
When filter circuit BUF1, phase inverter INV2 and INV3, NMOS tube N2 and N3, external enable signal EN connection filtering wave by prolonging time circuit
The input terminal of BUF1, the grid of the output end connection NMOS tube N3 of filtering wave by prolonging time circuit BUF1, the source electrode ground connection of NMOS tube N3,
Drain electrode connects the input of phase inverter INV2 and the output of phase inverter INV3 respectively, on the one hand the output of phase inverter INV2 connects phase inverter
On the other hand the input of INV3 goes back while connecting the drain electrode of NMOS tube N2 and the input of driving unit, the source electrode of NMOS tube N2
Ground connection, grid receive the SHUTDOWN signal of electricity consumption module output.
5. SOC electric power management circuit according to claim 1,2 or 3, it is characterised in that: the driving unit includes reverse phase
Device INV4, PMOS tube P1 and NMOS tube N1, wherein the source electrode of PMOS tube P1 connects power supply, the source electrode ground connection of NMOS tube N1, phase inverter
The grid of output connection the PMOS tube P1 and NMOS tube N1 of INV4, after PMOS tube P1 is connected with the drain electrode of NMOS tube N1, as
The driving signal of VDDA power supply；The input of the output Q connection phase inverter INV4 of the register cell.
6. SOC electric power management circuit according to claim 4, it is characterised in that: the driving unit includes phase inverter
INV4, PMOS tube P1 and NMOS tube N1, wherein the source electrode of PMOS tube P1 connects power supply, the source electrode ground connection of NMOS tube N1, phase inverter
The grid of output connection the PMOS tube P1 and NMOS tube N1 of INV4, after PMOS tube P1 is connected with the drain electrode of NMOS tube N1, as
The driving signal of VDDA power supply；The input of the output Q connection phase inverter INV4 of the register cell.
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| CN201920625786.4U CN209625154U (en) | 2019-05-05 | 2019-05-05 | A kind of SOC electric power management circuit |
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| CN201920625786.4U CN209625154U (en) | 2019-05-05 | 2019-05-05 | A kind of SOC electric power management circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021036227A1 (en) * | 2019-08-23 | 2021-03-04 | 深圳市零点智联科技有限公司 | Power saving method for smart vehicle key, and system |
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- 2019-05-05 CN CN201920625786.4U patent/CN209625154U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021036227A1 (en) * | 2019-08-23 | 2021-03-04 | 深圳市零点智联科技有限公司 | Power saving method for smart vehicle key, and system |
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Effective date of registration: 20230106 Address after: 215000 Floor 3, R&D Building, No. 1699, Zuchongzhi South Road, Yushan Town, Kunshan City, Suzhou, Jiangsu Province Patentee after: Suzhou Shengbang Yuanrong Information Security Technology Co.,Ltd. Address before: 215347 South Building B1-203, No. 99, Yudai West Road, Yushan Town, Kunshan City, Suzhou, Jiangsu Province Patentee before: SUZHOU SHENZHI MICROELECTRONICS Co.,Ltd. |
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