CN212572487U - Class D power amplifier and audio power amplification system - Google Patents
Class D power amplifier and audio power amplification system Download PDFInfo
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- CN212572487U CN212572487U CN202021527688.6U CN202021527688U CN212572487U CN 212572487 U CN212572487 U CN 212572487U CN 202021527688 U CN202021527688 U CN 202021527688U CN 212572487 U CN212572487 U CN 212572487U
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Abstract
The utility model provides a D class power amplifier and audio power amplification system need not the input stage clamp circuit that the change design is different to the gain, can simplify circuit structure. The class-D power amplifier comprises an input stage clamping circuit, a class-D modulation circuit, two variable input resistors RIN1, two fixed input resistors RIN2 and an output driving stage circuit; one differential input end of the D-type modulation circuit is connected with a variable input resistor RIN1 and a fixed input resistor RIN2 which are connected in series, the other differential input end is connected with the other variable input resistor RIN1 and the other fixed input resistor RIN2 which are connected in series, the input stage clamping circuit is positioned between the variable input resistor RIN1 and the fixed input resistor RIN2, the two variable input resistors RIN1 respectively output differential signals VINP and VINN to the input stage clamping circuit, and the input stage clamping circuit outputs two clamped differential signals VINP and VINN to the two input ends of the D-type modulation circuit through the two fixed input resistors RIN2 respectively.
Description
Technical Field
The utility model relates to a power amplifier technical field, concretely relates to D class power amplifier and audio power amplification system.
Background
The power amplifier usually introduces an input stage clamping circuit at the input stage to detect the magnitude of the input signal and clamp the input signal, so as to limit the output voltage to be kept within a certain range and avoid the load at the output end of the power amplifier, such as a loudspeaker, from being damaged due to the excessive input signal.
The inventor researches and discovers that for a D-type power amplifier which is connected with a differential signal and has adjustable gain, a plurality of different input stage clamping circuits are required to be designed to realize the same clamping output voltage of the D-type power amplifier according to different gains, and the circuit structure is redundant.
SUMMERY OF THE UTILITY MODEL
Based on this, the utility model provides a D class power amplifier and audio power amplification system need not the different input stage clamp circuit of change design to the gain, can simplify circuit structure.
In a first aspect, a class D power amplifier is provided, which includes an input stage clamping circuit, a class D modulation circuit, two variable input resistors RIN1, two fixed input resistors RIN2, and an output driver stage circuit; one differential input end of the D-type modulation circuit is connected with a variable input resistor RIN1 and a fixed input resistor RIN2 which are connected in series, the other differential input end is connected with the other variable input resistor RIN1 and the other fixed input resistor RIN2 which are connected in series, the input stage clamping circuit is positioned between the variable input resistor RIN1 and the fixed input resistor RIN2, the two variable input resistors RIN1 respectively output differential signals VINP and VINN to the input stage clamping circuit, the input stage clamping circuit outputs two clamped differential signals VINP and VINN which are respectively transmitted to the two input ends of the D-type modulation circuit through the two fixed input resistors RIN2, the D-type modulation circuit amplifies and modulates the signals, and outputs two pulse width modulation signals to the output driving stage circuit; the output driving circuit is used for responding to the two paths of pulse width modulation signals and outputting voltage to the loudspeaker.
In one embodiment, the class D modulation circuit comprises a first integrator AMP1, a second integrator AMP2, a first pulse width modulator and a second pulse width modulator;
the positive input end and the negative input end of the first integrator AMP1 are used as two input ends of the class D modulation circuit, wherein the negative input end is used for accessing the clamped signal VIPN, the positive input end is used for accessing the clamped signal VINN, the first output end of the first integrator AMP1 is connected with the positive input end of the second operational amplifier AMP2, the second output end of the first integrator AMP1 is connected with the negative input end of the second integrator AMP2, the first output end of the second integrator AMP2 is connected with the first input end of the first pulse width modulator, the second input end of the first pulse width modulator is used for accessing the sawtooth wave signal, the second output end of the second integrator AMP2 is connected with the first input end of the second pulse width modulator, the second input end of the second pulse width modulator is used for accessing the sawtooth wave signal, the output end of the first pulse width modulator is used as an output end of the class D modulation circuit and is connected with an input end of the output driving stage circuit, and the output end of the second pulse width modulator is used as the other output end of the D-type modulation circuit and is connected with the other input end of the output driving stage circuit.
In one embodiment, the input stage clamping circuit comprises a voltage division reference circuit, a differential comparator and a switch circuit, wherein the differential comparator comprises four input ends, the switch circuit comprises a first end, a second end and a control end, the first end and the second end of the switch circuit are respectively and correspondingly connected between a variable input resistor RIN2 and a fixed input resistor RIN2, and the control end of the switch circuit is connected with the output end of the differential comparator;
the voltage division reference circuit is used for outputting two different reference voltages;
the four input ends of the differential comparator are respectively connected with two output ends of the voltage division reference circuit and two variable input resistors RIN1 and respectively correspondingly used for accessing the two reference voltages and the differential signals VINP and VINN, and the differential comparator CMP1 is used for outputting a conduction control signal when the absolute value of the difference value obtained by subtracting the VINN from the differential signal VINP is greater than the difference value of the two reference voltages;
the first and second terminals of the switch circuit are respectively used for receiving the differential signals VINP and VINN, and are turned on in response to the turn-on control signal output by the differential comparator CMP1, so that the first and second terminals of the switch circuit are turned on to clamp the differential signals VINP and VINN.
In one embodiment, the differential comparator further comprises two output terminals, each connected to the control terminal of the switching circuit to provide the output voltages VP and VN;
the difference comparator is used for comparing the difference value of the difference signals VINP and VINN with the difference value of the two reference voltages, setting the output voltage VP to be high level when the difference value obtained by subtracting the VINN from the difference signal VINP is judged to be larger than the difference value of the reference voltages, and setting the output voltage VN to be high level when the difference value obtained by subtracting the VINP from the difference signal VINN is judged to be larger than the difference value of the reference voltages;
the switch circuit is used for conducting when the output voltage VP or VN is high level so as to clamp the differential signals VINP and VINN.
In one embodiment, the switch circuit includes a first NMOS transistor and a second NMOS transistor, a gate terminal of the first NMOS transistor is connected to one of the output terminals of the differential comparator to access the output voltage VP, a gate terminal of the second NMOS transistor is connected to the other output terminal of the differential comparator to access the output voltage VN, drain terminals of the first NMOS transistor and the second NMOS transistor are both used as a first terminal of the switch circuit to access the differential signal VINP, and a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor are both used as a second terminal of the switch circuit to access the differential signal VINN.
In one embodiment, the voltage division reference circuit includes a first voltage division resistor, a second voltage division resistor, and a third voltage division resistor, which are connected in series in sequence, wherein the first voltage division resistor is connected to a power supply voltage, the third voltage division resistor is connected to ground, and the first voltage division resistor and the third voltage division resistor have equal resistance values; the voltage at the connection node of the first voltage-dividing resistor and the second voltage-dividing resistor is used as one reference voltage, and the voltage at the connection node of the second voltage-dividing resistor and the third voltage-dividing resistor is used as the other reference voltage.
In one embodiment, the differential comparator comprises a first transpose circuit and a second transpose circuit;
the first transposition circuit comprises two input ends and an output end, the two input ends are respectively used for correspondingly accessing the two different reference voltages, and the transposition circuit is used for converting the reference voltage difference into the reference current;
the second transpose circuit is connected with the first transpose circuit, and includes two input ends and two output ends, the two output ends are respectively used for accessing a differential signal VINP and VINN, the two output ends are respectively used for outputting the output voltage VP or VN, the second transpose circuit is used for converting the differential signal VINP and VINN into a current signal IP and IN, and is used for setting the output voltage VP to a high level when the current signal IP is greater than a reference current, and setting the output voltage VN to a high level when the current signal IN is greater than the reference current.
In one embodiment, the differential comparator CMP1 further comprises a bias current input circuit, the bias current input circuit comprises an NMOS transistor MN1 and an NMOS transistor MN 2; the first switching circuit comprises an NMOS tube MN3, an NMOS tube MN4, an NMOS tube MN5, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8, a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5 and a PMOS tube MP 6; the second transpose circuit comprises an NMOS tube MN9, an NMOS tube MN10, an NMOS tube MN11, an NMOS tube MN12, an NMOS tube MN13, an NMOS tube MN14, an NMOS tube MN15, an NMOS tube MN16, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, a PMOS tube MP10, a PMOS tube MP11, a PMOS tube MP12, a PMOS tube MP13 and a PMOS tube MP 14;
in the bias current input circuit, the drain terminal of an NMOS (N-channel metal oxide semiconductor) tube MN1 is used for accessing a bias current IB, the gate terminal and the drain terminal are connected together, and the source terminal is connected with the drain terminal of an NMOS tube MN 2; the gate end and the drain end of the NMOS tube MN2 are connected together, and the source end is grounded; the gate end of the NMOS tube MN1 is connected with the gate end of the NMOS tube MN3, and the gate end of the NMOS tube MN2 is connected with the gate end of the NMOS tube MN 4;
in the first switching circuit, the source end of a PMOS tube MP1 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of a PMOS tube MP 2; the gate end and the drain end of the PMOS tube MP2 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 7; the source end of the NMOS tube MN7 is connected with the drain end of the NMOS tube MN3, and the gate end is connected with one of the reference voltages; the source end of the PMOS tube MP3 is used for accessing power supply voltage, the grid end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 4; the gate end and the drain end of the PMOS tube MP4 are connected together, the drain end is connected with the drain end of the NMOS tube MN8, the source end of the NMOS tube MN8 is connected with the drain end of the NMOS tube MN3, and the gate end is connected with another reference voltage; the source end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN4, and the source end of the NMOS tube MN4 is grounded; the source end of the PMOS tube MP5 is used for accessing power supply voltage, the gate end of the PMOS tube MP3 is connected with the gate end of the PMOS tube MP3, and the drain end of the PMOS tube MP6 is connected with the source end of the PMOS tube MP 6; the gate end of the PMOS tube MP6 is connected with the gate end of the PMOS tube MP4, the drain end of the PMOS tube MP6 is connected with the drain end of the NMOS tube MN5, the gate end and the drain end of the NMOS tube MN5 are connected together, the source end of the NMOS tube MN5 is connected with the drain end of the NMOS tube MN6, and the source end of the NMOS tube MN6 is grounded;
in the second transpose circuit, the source end of a PMOS transistor MP9 is used for accessing a supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of a PMOS transistor MP 10; the gate end and the drain end of the PMOS tube MP10 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 15; the source end of the NMOS tube MN15 is connected with the drain end of the NMOS tube MN11, and the gate end is connected with a differential signal VINN; the source end of the PMOS tube MP11 is used for accessing power supply voltage, the grid end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 12; the gate end and the drain end of the PMOS tube MP12 are connected together, the drain end is connected with the drain end of the NMOS tube MN16, the source end of the NMOS tube MN16 is connected with the drain end of the NMOS tube MN11, and the gate end is accessed to a differential signal VINP; the source end of the NMOS tube MN11 is connected with the drain end of the NMOS tube MN12, and the source end of the NMOS tube MN12 is grounded; the source end of a PMOS tube MP7 is used for accessing power supply voltage, the drain end of the PMOS tube MP7 is connected with the source end of a PMOS tube MP8, the drain end of a PMOS tube MP8 is connected with the drain end of an NMOS tube MN9, the drain end of the PMOS tube MP8 also provides a switch control voltage VN, the gate end of an NMOS tube MN9 is connected with the gate end of an NMOS tube MN5, the source end of the NMOS tube MN9 is connected with the drain end of the NMOS tube MN10, the source end of the NMOS tube MN10 is grounded, the gate end of the NMOS tube MN10 is connected with the gate end of an NMOS tube MN6, and the drain end of the NMOS tube MN9 is grounded through a capacitor C1; the source end of the PMOS tube MP13 is used for accessing power supply voltage, the drain end of the PMOS tube MP13 is connected with the source end of the PMOS tube MP14, the drain end of the PMOS tube MP14 is connected with the drain end of the NMOS tube MN13, the drain end of the PMOS tube MP14 also provides a switch control voltage VP, the gate end of the NMOS tube MN13 is connected with the gate end of the NMOS tube MN9, the source end of the NMOS tube MN13 is connected with the drain end of the NMOS tube MN14, the source end of the NMOS tube MN14 is grounded, the gate end of the NMOS tube MN14 is connected with the gate end of the NMOS tube MN10, and the drain end of the NMOS tube MN13 is grounded through a capacitor C2.
In a second aspect, an audio power amplifying system is provided, which includes a speaker and the class D power amplifier as described in any of the above embodiments, wherein an output terminal of an output driver stage circuit in the class D power amplifier is connected to an input terminal of the speaker as an output terminal of the class D power amplifier.
In one embodiment, the audio power amplifying system further comprises an external LC filter circuit, and the output terminal of the class D power amplifier is connected to the speaker through the external LC filter.
According to the class-D power amplifier and the audio power amplification system, the input variable resistor of the class-D power amplifier is divided into the variable resistor part and the fixed resistor part, and then the input stage clamping circuit is arranged between the variable resistor fixed resistors, so that the output clamping voltage of the power amplifier is independent of the change of the gain, different input stage clamping circuits do not need to be designed according to the change of the gain, and the circuit structure can be simplified.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a class-D power amplifier according to an embodiment of the present invention;
fig. 2 is a schematic waveform diagram of each node of the power amplifier according to an embodiment of the present invention;
fig. 3a and 3b are schematic structural diagrams of a class D power amplifier according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a voltage division reference circuit according to an embodiment of the present invention;
fig. 5 is a schematic waveform diagram of voltages at nodes according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a differential comparator according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an audio power amplifying system according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments, not all embodiments, of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention. The following embodiments and their technical features may be combined with each other without conflict.
As described in the background art, the inventors have found that, in a class-D power amplifier that is connected to a differential signal and has an adjustable gain, a plurality of different input stage clamp circuits need to be designed to achieve the same clamp output voltage of the class-D power amplifier according to different gains, and the circuit structure is redundant.
The embodiment of the utility model provides a D class power amplifier, this D class power amplifier's output clamp voltage does not have the change about the gain, consequently need not to design different input stage clamp circuit to the change of gain, can simplify circuit structure.
The embodiment of the present invention provides a class-D power amplifier, and in an embodiment, please refer to fig. 1, the power amplifier includes an input stage clamping circuit 100, a class-D modulation circuit 510, two variable input resistors RIN1, two fixed input resistors RIN2, and an output driver stage circuit 520; one differential input end of the class-D modulation circuit 510 is connected to a variable input resistor RIN1 and a fixed input resistor RIN2, the other differential input end is connected to another variable input resistor RIN1 and another fixed input resistor RIN2, the input stage clamping circuit 100 is located between the variable input resistor RIN1 and the fixed input resistor RIN2, the two variable input resistors RIN1 respectively output differential signals VINP and VINN to the two differential signal input ends of the input stage clamping circuit 100, and the two output ends of the input stage clamping circuit 100 output two clamped differential signals VINP and VINN which are respectively transmitted to the two input ends of the class-D modulation circuit 510 through the two fixed input resistors RIN 2. The class D modulation circuit 510 is configured to amplify and modulate a signal and output the signal to the output driver stage circuit 520. The output driver circuit 520 is configured to output a voltage to the speaker in response to the two pulse width modulated signals.
Specifically, the differential signals VINP and VINN may be voltage signals filtered by the differential signals INP and INN, as shown in fig. 1, the front ends of two variable input resistors RIN1 are respectively connected to a capacitor C2, and the differential signals INP and INN are respectively passed through C2 and a variable input resistor RIN1 to form the differential signals VINP and VINN.
In this embodiment, the class D power amplifier adds the input stage clamp circuit 100 between the variable input resistor RIN1 and the fixed input resistor RIN2, which can adjust the gain at the input end, and the input stage clamp circuit 100 detects the magnitudes of the input differential signals VINP and VINN, so that once the difference between the input differential signals VINP and VINN exceeds the difference between the reference voltages VRFH and VRFL, the differential signals VINP and VINN are clamped, and the output voltage VO supplied to the speaker by the class D power amplifier is also clamped at the voltage value Vclamp, thereby limiting the magnitude of the output voltage of the class D power amplifier and avoiding the load from being damaged due to the excessive input signal.
As shown in fig. 2, which is a schematic diagram of waveforms of the differential signals INP and INN, the clamped differential signals VINP and VINN, and the output voltage VO of the power amplifier, when the difference between the differential signals VINP and VINN is greater than the reference voltage difference Δ, the differential signals VINP and VINN are clamped at +0.5 Δ and-0.5 Δ, respectively, and the output voltage VO of the power amplifier is clamped at Vclamp.
The clamp voltage Vclamp satisfies the following relation:
where RF is a feedback resistor of the class D power amplifier, as shown in fig. 1, the input terminal of the class D modulation circuit 510 and the output terminal of the output driver stage circuit 520 are connected through the feedback resistor RF.
As can be seen from the above formula, in the present embodiment, the clamp voltage Vclamp is positively correlated with the fixed resistor RIN2, and is not correlated with the gain-adjustable resistor RIN1, so that the same clamp voltage can be provided to be compatible with different gains of the power amplifier by disposing the input stage clamp circuit between the gain-adjustable resistor and the fixed resistor, and it is not necessary to design different input stage clamp circuits for power amplifiers with varying gains, and the circuit structure can be simplified.
Specifically, as shown in fig. 3a, the class-D modulation circuit includes a first integrator AMP1, a second integrator AMP2, a first pulse width modulator comp1, and a second pulse width modulator comp 2;
the positive input end and the negative input end of the first integrator AMP1 are used as two input ends of the class D modulation circuit, wherein the negative input end is used for receiving the clamped signal VINP, the positive input end is used for receiving the clamped signal VINN, the first output end of the first integrator AMP1 is connected with the positive input end of the second integrator AMP2, the second output end of the first integrator AMP1 is connected with the negative input end of the second integrator AMP2, the first output end of the second integrator AMP2 is connected with the first input end of the first pulse width modulator comp1, the second input end of the first pulse width modulator comp1 is used for receiving the sawtooth wave signal, the second output end of the second integrator AMP2 is connected with the first input end of the second pulse width modulator comp2, the second input end of the second pulse width modulator comp2 is used for receiving the sawtooth wave signal, the output end of the first pulse width modulator comp1 is used as an output end of the class D modulation circuit and is connected with the input end 520 of the output driving circuit, an output terminal of the second pulse width modulator comp2 is connected as another output terminal of the class D modulation circuit 510 to another input terminal of the output driver stage circuit 520. Specifically, the first integrator AMP1 and the second integrator AMP2 are further connected to common-mode reference voltages VCM1 and VCM2, respectively.
Referring to fig. 3b, the input stage clamp circuit 100 includes a voltage division reference circuit 110, a differential comparator CMP1 and a switch circuit 120, the differential comparator CMP1 includes four input terminals, the switch circuit 120 includes a first terminal, a second terminal and a control terminal, the first terminal and the second terminal of the switch circuit 120 are respectively and correspondingly connected between a variable input resistor RIN1 and a fixed input resistor RIN2, and the control terminal of the switch circuit 120 is connected to the output terminal of the differential comparator CMP 1. The voltage division reference circuit 110 is used to output two different reference voltages VRFH and VRFL. The differential comparator CMP1 is configured to output a turn-on control signal when an absolute value of a difference between the two reference voltages VINP and VINN is greater than a difference between the two reference voltages, wherein four input terminals of the differential comparator CMP1 are respectively connected to two output terminals of the voltage-dividing reference circuit 110 and the two variable input resistors RIN1, and are respectively used for correspondingly accessing the two reference voltages VRFH and VRFL and the differential signals VINP and VINN. The first end and the second end of the switch circuit 120 are respectively used for accessing the differential signals VINP and VINN, and the switch circuit 120 is used for conducting when the absolute value of the difference value between the differential signals VINP and VINN is greater than the difference value between the two reference voltages, so that the first end and the second end of the switch circuit 120 are connected to clamp the differential signals VINP and VINN.
In this embodiment, one differential comparator CMP1 may be used to access the differential signals VINP and VINN and the two reference voltages VRFH and VRFL, and use the difference between the two reference voltages VRFH and VRFL as a detection threshold, and when the absolute value of the difference between the two differential signals is greater than the difference between the two reference voltages, the output voltage of the differential comparator CMP1 may turn on the switch circuit 120, so as to clamp the differential signals VINP and VINN, thereby limiting the output voltage of the power amplifier.
In one embodiment, referring to fig. 3b, the differential comparator CMP1 further includes two output terminals, both of which are connected to the control terminal of the switch circuit 120, wherein one of the output terminals provides the output voltage VP, and the other of the output terminals provides the output voltage VN, the differential comparator CMP1 is configured to compare the difference between the differential signals VINP and VINN and the two reference voltages, set the output voltage VP to a high level when it is determined that the difference between the differential signals VINP and VINN is greater than the difference between the reference voltages, and set the output voltage VN to a high level when it is determined that the difference between the differential signals VINN and VINN is greater than the difference between the reference voltages; the switch circuit 120 is configured to be turned on when the output voltage VP or VN is high, so as to clamp the differential signals VINP and VINN.
Specifically, referring to fig. 3b, the switch circuit 120 includes two control terminals, which are a first control terminal and a second control terminal, respectively, the switch circuit 120 includes a first NMOS transistor Mn1 and a second NMOS transistor Mn2, a gate terminal of the first NMOS transistor Mn1 is used as the first control terminal to connect to one output terminal of the differential comparator CMP1 to receive the output voltage VP, a gate terminal of the second NMOS transistor Mn2 is used as the second control terminal to connect to the other output terminal of the differential comparator CMP1 to receive the output voltage VN, drain terminals of the first NMOS transistor Mn1 and the second NMOS transistor Mn2 are both used as the first terminal of the switch circuit 120 to receive the differential signal VINP, and a source terminal of the first NMOS transistor Mn1 and a source terminal of the second NMOS transistor Mn2 are both used as the second terminal of the switch circuit 120 to receive the differential signal VINN.
Specifically, referring to fig. 3b, the voltage division reference circuit 110 includes a first voltage division resistor R1, a second voltage division resistor R2, and a third voltage division resistor R3, where the first voltage division resistor R1, the second voltage division resistor R2, and the third voltage division resistor R3 are sequentially connected in series, where the first voltage division resistor R1 is connected to a power supply voltage, and the third voltage division resistor R3 is grounded; the voltage at the connection node of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 is used as one of the reference voltages VRFHSaid second voltage dividerThe voltage at the junction of the resistor R2 and the third voltage dividing resistor R3 is used as another reference voltage VRFL. The first voltage dividing resistor R1 and the third voltage dividing resistor R3 may have equal resistances.
When the resistances of the divider resistors R1 and R3 are equal, a symmetrical reference voltage V can be providedRFHAnd VRFLThe clamping accuracy can be improved. Assuming that the power supply voltage is VDD, the relationship between the difference Δ of the reference voltages VRFH and VRFL and the voltage dividing resistors R1, R2, R3 is as follows:
it can be seen that when the resistances of the first voltage dividing resistor R1 and the third voltage dividing resistor R3 are equal, as shown in fig. 4, the reference voltages VRFH and VRFL are symmetrical with respect to the common mode voltage 0.5VDD of the input stage, i.e., the reference voltage VRFH is 0.5 Δ higher than 0.5VDD, the reference voltage VRFL is 0.5 Δ lower than 0.5VDD, and the reference voltage V isRFHAnd VRFLIs symmetrical, and can improve clamping precision.
Fig. 5 is a waveform diagram of the differential signals VINP and VINN, the differential signals INP and INN, and the voltages VP and VN in the circuit of fig. 3 b.
In one embodiment, referring to fig. 6, the differential comparator CMP1 includes a first transpose circuit 210 and a second transpose circuit 220; the first switching circuit 210 includes two input terminals and an output terminal, the two input terminals are respectively used for correspondingly connecting the two different reference voltages VRFHAnd VRFLThe first converting circuit 210 is configured to convert the reference voltage difference into a reference current IRFHL; the second transpose circuit 220 is connected to the first transpose circuit 210, the second transpose circuit 220 further includes two input terminals and two output terminals, the two output terminals are respectively connected to the differential signals VINP and VINN, the two output terminals are respectively used for outputting the output voltage VP or VN, the second transpose circuit 220 is configured to convert the differential signal VINP into the current signal IN, convert the differential signal VINP into the current signal IP, and output the output power when the current signal IP is greater than the reference current IRFHLThe voltage VP is set to high, and the output voltage VN is set to high when the current signal IN is greater than the reference current IRFHL.
Specifically, referring to fig. 6, the differential comparator CMP1 further includes a bias current input circuit 230 for inputting a bias current IB to the first transpose circuit 210 and the second transpose circuit 220, so as to improve the response speed of the differential comparator CMP 1. Specifically, the bias current circuit 230 includes an NMOS transistor MN1 and an NMOS transistor MN 2; the first transpose circuit 210 comprises an NMOS transistor MN3, an NMOS transistor MN4, an NMOS transistor MN5, an NMOS transistor MN6, an NMOS transistor MN7, an NMOS transistor MN8, a PMOS transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, a PMOS transistor MP4, a PMOS transistor MP5 and a PMOS transistor MP 6; the second transpose circuit 220 comprises an NMOS transistor MN9, an NMOS transistor MN10, an NMOS transistor MN11, an NMOS transistor MN12, an NMOS transistor MN13, an NMOS transistor MN14, an NMOS transistor MN15, an NMOS transistor MN16, a PMOS transistor MP7, a PMOS transistor MP8, a PMOS transistor MP9, a PMOS transistor MP10, a PMOS transistor MP11, a PMOS transistor MP12, a PMOS transistor MP13 and a PMOS transistor MP 14;
in the bias current input circuit 230, the drain terminal of an NMOS transistor MN1 is used for accessing a bias current IB, the gate terminal and the drain terminal are connected together, and the source terminal is connected to the drain terminal of an NMOS transistor MN 2; the gate end and the drain end of the NMOS tube MN2 are connected together, and the source end is grounded; the gate terminal of the NMOS transistor MN1 is connected to the gate terminal of the NMOS transistor MN3 in the first transpose circuit 210, the gate terminal of the NMOS transistor MN11 in the second transpose circuit 210 to provide a bias current to the NMOS transistor MN3 and the NMOS transistor MN11, the gate terminal of the NMOS transistor MN2 is connected to the gate terminal of the NMOS transistor MN4 in the first transpose circuit 210, and the gate terminal of the NMOS transistor MN12 in the second transpose circuit 220 to provide a bias current to the NMOS transistor MN4 and the NMOS transistor MN12, so as to improve the response speed of the NMOS transistor MN3, the NMOS transistor MN4, the NMOS transistor MN11, and the NMOS transistor MN12, and improve the response speed of the differential comparator CMP 1.
In the first inverter circuit 210, the source terminal of the PMOS transistor MP1 is used for accessing a supply voltage, the gate terminal and the drain terminal are connected together, and the drain terminal is connected with the source terminal of the PMOS transistor MP 2; the gate end and the drain end of the PMOS tube MP2 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 7; the source end of the NMOS tube MN7 is connected with the drain end of the NMOS tube MN3, and the gate end is accessed with a reference voltage VRFL(ii) a The source end of the PMOS tube MP3 is used for being connected with a power supply voltage, the grid end and the drainThe ends are connected together, and the drain end is connected with the source end of the PMOS tube MP 4; the gate end and the drain end of the PMOS tube MP4 are connected together, the drain end is connected with the drain end of the NMOS tube MN8, the source end of the NMOS tube MN8 is connected with the drain end of the NMOS tube MN3, and the gate end is accessed to a reference voltage VRFH(ii) a The source end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN4, and the source end of the NMOS tube MN4 is grounded; the source end of the PMOS tube MP5 is used for accessing power supply voltage, the gate end of the PMOS tube MP3 is connected with the gate end of the PMOS tube MP3, and the drain end of the PMOS tube MP6 is connected with the source end of the PMOS tube MP 6; the gate end of the PMOS tube MP6 is connected with the gate end of the PMOS tube MP4, the drain end of the PMOS tube MP6 is connected with the drain end of the NMOS tube MN5, the gate end and the drain end of the NMOS tube MN5 are connected together, the source end of the NMOS tube MN5 is connected with the drain end of the NMOS tube MN6, and the source end of the NMOS tube MN6 is grounded.
In the second transpose circuit 220, a source terminal of the PMOS transistor MP9 is used for accessing a supply voltage, a gate terminal and a drain terminal are connected together, and the drain terminal is connected with a source terminal of the PMOS transistor MP 10; the gate end and the drain end of the PMOS tube MP10 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 15; the source end of the NMOS tube MN15 is connected with the drain end of the NMOS tube MN11, and the gate end is connected with a differential signal VINN; the source end of the PMOS tube MP11 is used for accessing power supply voltage, the grid end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 12; the gate end and the drain end of the PMOS tube MP12 are connected together, the drain end is connected with the drain end of the NMOS tube MN16, the source end of the NMOS tube MN16 is connected with the drain end of the NMOS tube MN11, and the gate end is accessed to a differential signal VINP; the source end of the NMOS transistor MN11 is connected with the drain end of the NMOS transistor MN12, and the source end of the NMOS transistor MN12 is grounded. The source end of the PMOS tube MP7 is used for accessing power supply voltage, the drain end is connected with the source end of the PMOS tube MP8, the drain end of the PMOS tube MP8 is connected with the drain end of the NMOS tube MN9, the drain end of the PMOS tube MP8 also provides a switch control voltage VN, the gate end of the NMOS tube MN9 is connected with the gate end of the NMOS tube MN5, the source end of the NMOS tube MN9 is connected with the drain end of the NMOS tube MN10, the source end of the NMOS tube MN10 is grounded, the gate end of the NMOS tube MN10 is connected with the gate end of the NMOS tube MN6, and the drain end of the NMOS tube MN9 is grounded through a capacitor C1. The source end of the PMOS tube MP13 is used for accessing power supply voltage, the drain end of the PMOS tube MP13 is connected with the source end of the PMOS tube MP14, the drain end of the PMOS tube MP14 is connected with the drain end of the NMOS tube MN13, the drain end of the PMOS tube MP14 also provides a switch control voltage VP, the gate end of the NMOS tube MN13 is connected with the gate end of the NMOS tube MN9, the source end of the NMOS tube MN13 is connected with the drain end of the NMOS tube MN14, the source end of the NMOS tube MN14 is grounded, the gate end of the NMOS tube MN14 is connected with the gate end of the NMOS tube MN10, and the drain end of the NMOS tube MN13 is grounded through a capacitor C2.
In this embodiment, the differential signals VINP and VINN, reference voltage VRFHAnd VRFLFor input signals, the switch control voltages VP and VN are output signals. When the current IP is larger than the current IRFHL, the difference value of subtracting the VINN from the differential signal VINP is larger than the difference value of the reference voltages VRFH and VRFL, the voltage VP is set to be high level, otherwise, the voltage VP is set to be low level, when the current IN is larger than the current IRFHL, the difference value of subtracting the VINP from the differential signal VINN is larger than the difference value of the reference voltages VRFH and VRFL, and the voltage VN is set to be high level, otherwise, the voltage VN is set to be low level.
To sum up, the embodiment of the utility model provides an in to gain adjustable D class power amplifier, through the input variable resistance split with power amplifier become variable resistance part and fixed resistance part, then set up input stage clamping circuit between the variable resistance fixed resistance for power amplifier output clamping voltage is irrelevant with the change of gain, consequently need not to design different input stage clamping circuit to the change of gain, can simplify circuit structure. Just the embodiment of the utility model provides an in D class power amplifier, only need input stage clamp circuit all the way just can realize the clamper to differential signal, require lowly to the circuit matching nature.
The embodiment of the utility model provides a still provide an audio power amplification system, including speaker and the power amplifier as in above arbitrary embodiment, output drive level circuit's output is as among the power amplifier's output with the input of speaker is connected.
Referring to fig. 7, the audio power amplifying system further includes an external LC filter, and the output terminal of the power amplifier is connected to the speaker through the external LC filter.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (10)
1. A class D power amplifier is characterized by comprising an input stage clamping circuit, a class D modulation circuit, two variable input resistors RIN1, two fixed input resistors RIN2 and an output driving stage circuit;
one differential input end of the D-type modulation circuit is connected with a variable input resistor RIN1 and a fixed input resistor RIN2, the other differential input end of the D-type modulation circuit is connected with another variable input resistor RIN1 and another fixed input resistor RIN2, the input stage clamping circuit is positioned between the variable input resistor RIN1 and the fixed input resistor RIN2, the two variable input resistors RIN1 respectively output differential signals VINP and VINN to the input stage clamping circuit, the input stage clamping circuit outputs two clamped differential signals VINP and VINN which are respectively transmitted to the two input ends of the D-type modulation circuit through the two fixed input resistors RIN2, the D-type modulation circuit amplifies and modulates the signals and outputs two pulse width modulation signals to the output driving stage circuit; the output driving circuit is used for responding to the two paths of pulse width modulation signals and outputting voltage to the loudspeaker.
2. The class D power amplifier of claim 1, wherein the class D modulation circuit comprises a first integrator, a second integrator, a first pulse width modulator, and a second pulse width modulator;
the positive input end and the negative input end of the first integrator AMP1 are used as two input ends of the class D modulation circuit, wherein the negative input end is used for accessing a clamped signal VIPN, the positive input end is used for accessing a clamped signal VINN, the first output end of the first integrator AMP1 is connected with the positive input end of the second operational amplifier AMP2, the second output end of the first integrator AMP1 is connected with the negative input end of the second integrator AMP2, the first output end of the second integrator AMP2 is connected with the first input end of the first pulse width modulator, the second input end of the first pulse width modulator is used for accessing a sawtooth wave signal, the second output end of the second integrator AMP2 is connected with the first input end of the second pulse width modulator, the second input end of the second pulse width modulator is used for accessing a sawtooth wave signal, and the output end of the first pulse width modulator is used as an output end of the class D modulation circuit and is connected with an input end of the output driving circuit, and the output end of the second pulse width modulator is used as the other output end of the D-type modulation circuit and is connected with the other input end of the output driving stage circuit.
3. The class-D power amplifier of claim 1, wherein the input stage clamp circuit comprises a voltage division reference circuit, a differential comparator and a switch circuit, the differential comparator comprises four input terminals, the switch circuit comprises a first terminal, a second terminal and a control terminal, the first terminal and the second terminal of the switch circuit are respectively and correspondingly connected between a variable input resistor RIN1 and a fixed input resistor RIN2, and the control terminal of the switch circuit is connected to the output terminal of the differential comparator;
the voltage division reference circuit is used for outputting two different reference voltages;
the four input ends of the differential comparator are respectively connected with two output ends of the voltage division reference circuit and two variable input resistors RIN1 and respectively correspondingly used for accessing the two reference voltages and the differential signals VINP and VINN, and the differential comparator is used for outputting a conduction control signal when the absolute value of the difference value between the differential signal VINP and the VINN is larger than the difference value of the two reference voltages;
the first end and the second end of the switch circuit are respectively used for accessing differential signals VINP and VINN, and are conducted in response to the conduction control signal output by the differential comparator, so that the first end and the second end of the switch circuit are switched on, and the differential signals VINP and VINN are clamped.
4. A class D power amplifier according to claim 3, wherein the differential comparator further comprises two output terminals, each connected to a control terminal of the switching circuit to provide output voltages VP and VN;
the difference comparator is used for comparing the difference value of the difference signals VINP and VINN with the difference value of the two reference voltages, setting the output voltage VP to be high level when the difference value obtained by subtracting the VINN from the difference signal VINP is judged to be larger than the difference value of the reference voltages, and setting the output voltage VN to be high level when the difference value obtained by subtracting the VINP from the difference signal VINN is judged to be larger than the difference value of the reference voltages;
the switch circuit is used for conducting when the output voltage VP or VN is high level so as to clamp the differential signals VINP and VINN.
5. The class-D power amplifier of claim 4, wherein the switch circuit includes two control terminals, namely a first control terminal and a second control terminal, the switch circuit includes a first NMOS transistor and a second NMOS transistor, a gate terminal of the first NMOS transistor is connected to one of the output terminals of the differential comparator as the first control terminal to receive the output voltage VP, a gate terminal of the second NMOS transistor is connected to the other output terminal of the differential comparator as the second control terminal to receive the output voltage VN, drain terminals of the first and second NMOS transistors are both used as the first terminal of the switch circuit to receive the differential signal VINP, and a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor are both used as the second terminal of the switch circuit to receive the differential signal VINN.
6. The class-D power amplifier according to claim 3, wherein the voltage dividing reference circuit comprises a first voltage dividing resistor, a second voltage dividing resistor and a third voltage dividing resistor, and the first voltage dividing resistor, the second voltage dividing resistor and the third voltage dividing resistor are connected in series in sequence, wherein the first voltage dividing resistor is connected to a supply voltage, the third voltage dividing resistor is connected to ground, and the first voltage dividing resistor and the third voltage dividing resistor have equal resistance values; the voltage at the connection node of the first voltage-dividing resistor and the second voltage-dividing resistor is used as one reference voltage, and the voltage at the connection node of the second voltage-dividing resistor and the third voltage-dividing resistor is used as the other reference voltage.
7. The class D power amplifier of claim 3, wherein the differential comparator comprises a first transpose circuit and a second transpose circuit;
the first transposition circuit comprises two input ends and an output end, the two input ends are respectively used for correspondingly accessing the two different reference voltages, and the transposition circuit is used for converting the reference voltage difference into the reference current;
the second transpose circuit is connected with the first transpose circuit, and includes two input ends and two output ends, the two output ends are respectively used for accessing a differential signal VINP and VINN, the two output ends are respectively used for outputting the output voltage VP or VN, the second transpose circuit is used for converting the differential signal VINP and VINN into a current signal IP and IN, and is used for setting the output voltage VP to a high level when the current signal IP is greater than a reference current, and setting the output voltage VN to a high level when the current signal IN is greater than the reference current.
8. The class-D power amplifier of claim 7, wherein the differential comparator further comprises a bias current input circuit comprising NMOS transistor MN1 and NMOS transistor MN 2; the first switching circuit comprises an NMOS tube MN3, an NMOS tube MN4, an NMOS tube MN5, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8, a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5 and a PMOS tube MP 6; the second transpose circuit comprises an NMOS tube MN9, an NMOS tube MN10, an NMOS tube MN11, an NMOS tube MN12, an NMOS tube MN13, an NMOS tube MN14, an NMOS tube MN15, an NMOS tube MN16, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, a PMOS tube MP10, a PMOS tube MP11, a PMOS tube MP12, a PMOS tube MP13 and a PMOS tube MP 14;
in the bias current input circuit, the drain terminal of an NMOS (N-channel metal oxide semiconductor) tube MN1 is used for accessing a bias current IB, the gate terminal and the drain terminal are connected together, and the source terminal is connected with the drain terminal of an NMOS tube MN 2; the gate end and the drain end of the NMOS tube MN2 are connected together, and the source end is grounded; the gate end of the NMOS tube MN1 is connected with the gate end of the NMOS tube MN3 and the gate end of the NMOS tube MN11, and the gate end of the NMOS tube MN2 is connected with the gate end of the NMOS tube MN4 and the gate end of the NMOS tube MN 12;
in the first switching circuit, the source end of a PMOS tube MP1 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of a PMOS tube MP 2; the gate end and the drain end of the PMOS tube MP2 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 7; the source end of the NMOS tube MN7 is connected with the drain end of the NMOS tube MN3, and the gate end is connected with one of the reference voltages; the source end of the PMOS tube MP3 is used for accessing power supply voltage, the grid end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 4; the gate end and the drain end of the PMOS tube MP4 are connected together, the drain end is connected with the drain end of the NMOS tube MN8, the source end of the NMOS tube MN8 is connected with the drain end of the NMOS tube MN3, and the gate end is connected with another reference voltage; the source end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN4, and the source end of the NMOS tube MN4 is grounded; the source end of the PMOS tube MP5 is used for accessing power supply voltage, the gate end of the PMOS tube MP3 is connected with the gate end of the PMOS tube MP3, and the drain end of the PMOS tube MP6 is connected with the source end of the PMOS tube MP 6; the gate end of the PMOS tube MP6 is connected with the gate end of the PMOS tube MP4, the drain end of the PMOS tube MP6 is connected with the drain end of the NMOS tube MN5, the gate end and the drain end of the NMOS tube MN5 are connected together, the source end of the NMOS tube MN5 is connected with the drain end of the NMOS tube MN6, and the source end of the NMOS tube MN6 is grounded;
in the second transpose circuit, the source end of a PMOS transistor MP9 is used for accessing a supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of a PMOS transistor MP 10; the gate end and the drain end of the PMOS tube MP10 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 15; the source end of the NMOS tube MN15 is connected with the drain end of the NMOS tube MN11, and the gate end is connected with a differential signal VINN; the source end of the PMOS tube MP11 is used for accessing power supply voltage, the grid end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 12; the gate end and the drain end of the PMOS tube MP12 are connected together, the drain end is connected with the drain end of the NMOS tube MN16, the source end of the NMOS tube MN16 is connected with the drain end of the NMOS tube MN11, and the gate end is accessed to a differential signal VINP; the source end of the NMOS tube MN11 is connected with the drain end of the NMOS tube MN12, and the source end of the NMOS tube MN12 is grounded; the source end of a PMOS tube MP7 is used for accessing power supply voltage, the drain end of the PMOS tube MP7 is connected with the source end of a PMOS tube MP8, the drain end of a PMOS tube MP8 is connected with the drain end of an NMOS tube MN9, the drain end of the PMOS tube MP8 also provides a switch control voltage VN, the gate end of an NMOS tube MN9 is connected with the gate end of an NMOS tube MN5, the source end of the NMOS tube MN9 is connected with the drain end of the NMOS tube MN10, the source end of the NMOS tube MN10 is grounded, the gate end of the NMOS tube MN10 is connected with the gate end of an NMOS tube MN6, and the drain end of the NMOS tube MN9 is grounded through a capacitor C1; the source end of the PMOS tube MP13 is used for accessing power supply voltage, the drain end of the PMOS tube MP13 is connected with the source end of the PMOS tube MP14, the drain end of the PMOS tube MP14 is connected with the drain end of the NMOS tube MN13, the drain end of the PMOS tube MP14 also provides a switch control voltage VP, the gate end of the NMOS tube MN13 is connected with the gate end of the NMOS tube MN9, the source end of the NMOS tube MN13 is connected with the drain end of the NMOS tube MN14, the source end of the NMOS tube MN14 is grounded, the gate end of the NMOS tube MN14 is connected with the gate end of the NMOS tube MN10, and the drain end of the NMOS tube MN13 is grounded through a capacitor C2.
9. Audio power amplification system comprising a loudspeaker and a class D power amplifier according to any of claims 1-8, an output of the class D power amplifier being connected to an input of the loudspeaker.
10. The audio power amplification system of claim 9, further comprising an external LC filter circuit, wherein the output of the class D power amplifier is connected to a speaker through the external LC filter.
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| CN202021527688.6U CN212572487U (en) | 2020-07-28 | 2020-07-28 | Class D power amplifier and audio power amplification system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900940A (en) * | 2020-07-28 | 2020-11-06 | 上海艾为电子技术股份有限公司 | Input stage clamping circuit and clamping method thereof, and power amplifier |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900940A (en) * | 2020-07-28 | 2020-11-06 | 上海艾为电子技术股份有限公司 | Input stage clamping circuit and clamping method thereof, and power amplifier |
| CN111900940B (en) * | 2020-07-28 | 2024-04-19 | 上海艾为电子技术股份有限公司 | Input stage clamping circuit, clamping method thereof and power amplifier |
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