CN111900940B - Input stage clamping circuit, clamping method thereof and power amplifier - Google Patents

Input stage clamping circuit, clamping method thereof and power amplifier Download PDF

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Publication number
CN111900940B
CN111900940B CN202010742301.7A CN202010742301A CN111900940B CN 111900940 B CN111900940 B CN 111900940B CN 202010742301 A CN202010742301 A CN 202010742301A CN 111900940 B CN111900940 B CN 111900940B
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nmos tube
circuit
tube
voltage
drain
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CN111900940A (en
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胡孔生
杨志飞
张海军
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52—Circuit arrangements for protecting such amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52—Circuit arrangements for protecting such amplifiers
    • H03F1/523—Circuit arrangements for protecting such amplifiers for amplifiers using field-effect devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00—Circuits for transducers, loudspeakers or microphones
    • H04R3/007—Protection circuits for transducers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention discloses an input stage clamping circuit, a clamping method thereof, a power amplifier and an audio power amplifying system, wherein differential signals can be clamped only by one input stage clamping circuit, and the output voltage of the power amplifier can be limited, so that a loudspeaker is protected from being damaged due to overlarge output voltage of the power amplifier, and the requirement on the matching property of the circuit is reduced by the structural design of one input stage clamping circuit. The input stage clamping circuit comprises a differential comparator, wherein the differential comparator comprises four input ends; the four input ends of the differential comparator are respectively connected with differential signals VINP and VINN of the input stage of the power amplifier and two different reference voltages; if the absolute value of the difference value obtained by subtracting the VINN from the difference signal VINP is larger than the difference value of the two reference voltages, the switching circuit is conducted; and clamping the differential signals VINP and VINN by using the on switch circuit.

Description

Input stage clamping circuit, clamping method thereof and power amplifier
Technical Field
The invention relates to the technical field of power amplifiers, in particular to an input stage clamping circuit applied to a power amplifier and a clamping method thereof, a power amplifier and an audio power amplifying system.
Background
The power amplifier generally introduces an input stage clamping circuit at the input stage to detect the magnitude of an input signal and clamp the input signal, so as to limit the output voltage to be kept within a certain range, and avoid damage to a load at the output end of the power amplifier, such as a loudspeaker, caused by oversized input signal.
Currently, a single-ended input and single-ended output input stage clamping circuit is adopted to realize the clamping function. The inventor has found that for a power amplifier that is coupled to a differential signal, such as a class D power amplifier, two such input stage clamps are required, and that the matching requirements for the two input stage clamps are relatively high in order to ensure that the two clamp output signals maintain consistent changes.
Disclosure of Invention
Based on the above, the invention provides an input stage clamping circuit, a clamping method thereof, a power amplifier and an audio power amplifying system, which reduce the requirement on the matching property of the circuit.
In a first aspect, a clamping method of an input stage clamping circuit is provided, the input stage clamping circuit comprises a differential comparator and a switching circuit, the differential comparator comprises four input ends, and the switching circuit comprises a first end and a second end; the clamping method comprises the following steps:
The four input ends of the differential comparator are respectively connected with differential signals VINP and VINN of the input stage of the power amplifier and two different reference voltages, the difference value of the two reference voltages is used as a detection threshold value, and the first end and the second end of the switching circuit are also connected with the differential signals VINP and VINN;
If the absolute value of the difference value of the differential signals VINP and VINN is larger than the difference value of the two reference voltages, controlling the differential comparator to output a conduction control signal to conduct the switching circuit so as to switch on the first end and the second end of the switching circuit;
And clamping the differential signals VINP and VINN by using the on switch circuit.
In one embodiment, if the absolute value of the difference between the differential signals VINP and VINN is greater than the difference between the two reference voltages, the differential comparator is controlled to output a high level signal as the on control signal.
In one embodiment, the differential comparator further includes two output terminals, each connected to the control terminal of the switching circuit; and if the absolute value of the difference value of the differential signals VINP and VINN is larger than the difference value of the two reference voltages, controlling the two output ends of the differential comparator to output high-level voltage.
In one embodiment, the two reference voltages are symmetrical with respect to the input stage common mode voltage.
In a second aspect, an input stage clamping circuit is provided, including a voltage division reference circuit, a differential comparator and a switch circuit, wherein the differential comparator includes four input ends, the switch circuit includes a first end, a second end and a control end, the voltage division reference circuit is connected with two input ends of the differential comparator, and an output end of the differential comparator is connected with the control end of the switch circuit;
the voltage division reference circuit is used for outputting two different reference voltages;
The four input ends of the differential comparator are respectively used for correspondingly accessing the two reference voltages and differential signals VINP and VINN of the input stage of the power amplifier, and the differential comparator is used for outputting a conduction control signal when the absolute value of the difference value of the differential signals VINP and VINN is larger than the difference value of the two reference voltages;
The first end and the second end of the switch circuit are respectively used for being connected with differential signals VINP and VINN, and the switch circuit is used for responding to the conduction control signals output by the differential comparator to conduct, so that the first end and the second end of the switch circuit are connected to clamp the differential signals VINP and VINN.
In one embodiment, the differential comparator further comprises two output terminals, each connected to the switching circuit to provide output voltages VP and VN;
The differential comparator is used for comparing the difference value of the differential signals VINP and VINN with the difference value of the two reference voltages, setting the output voltage VP to a high level when the difference value of the differential signals VINP and VINN is determined to be larger than the difference value of the reference voltages, and setting the output voltage VN to a high level when the difference value of the differential signals VINN and VINP is determined to be larger than the difference value of the reference voltages; the switching circuit is turned on in response to the output voltage VP or VN being high.
In one embodiment, the switch circuit includes two control ends, namely a first control end and a second control end, the switch circuit includes a first NMOS tube and a second NMOS tube, the gate end of the first NMOS tube is used as the first control end to connect one of the output ends of the differential comparator to access the output voltage VP, the gate end of the second NMOS tube is used as the second control end to connect the other output end of the differential comparator to access the output voltage VN, the drain ends of the first NMOS tube and the second NMOS tube are used as the first end of the switch circuit to access the differential signal VINP, and the source ends of the first NMOS tube and the second NMOS tube are used as the second end of the switch circuit to access the differential signal VINN.
In one embodiment, the voltage division reference circuit comprises a first voltage division resistor, a second voltage division resistor and a third voltage division resistor, wherein the first voltage division resistor, the second voltage division resistor and the third voltage division resistor are sequentially connected in series, the first voltage division resistor is connected with a power supply voltage, the third voltage division resistor is grounded, and the resistance values of the first voltage division resistor and the third voltage division resistor are equal; the voltage at the connecting node of the first voltage dividing resistor and the second voltage dividing resistor is used as one of the reference voltages, and the voltage at the connecting node of the second voltage dividing resistor and the third voltage dividing resistor is used as the other reference voltage.
In one embodiment, the differential comparator includes a first transpose circuit and a second transpose circuit;
the first transfer circuit comprises two input ends, the two input ends are respectively used for correspondingly accessing the two different reference voltages, and the first transfer circuit is used for converting the reference voltage difference value into a reference current;
The second transpose circuit is connected with the first transpose circuit, the second transpose circuit further comprises two input ends and two output ends, the two input ends are respectively used for being connected with differential signals VINP and VINN, the two output ends are respectively used for outputting output voltage VP and output voltage VN, the second transpose circuit is used for converting the differential signals VINP and VINN into current signals IP and IN, and is used for setting the output voltage VP to be high level when the current signal IP is larger than a reference current, and setting the output voltage VN to be high level when the current signal IN is larger than the reference current.
The differential comparator further comprises a bias current input circuit, wherein the bias current circuit comprises an NMOS tube MN1 and an NMOS tube MN2; the first transfer circuit comprises an NMOS tube MN3, an NMOS tube MN4, an NMOS tube MN5, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8, a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5 and a PMOS tube MP6; the second transpose circuit comprises an NMOS tube MN9, an NMOS tube MN10, an NMOS tube MN11, an NMOS tube MN12, an NMOS tube MN13, an NMOS tube MN14, an NMOS tube MN15, an NMOS tube MN16, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, a PMOS tube MP10, a PMOS tube MP11, a PMOS tube MP12, a PMOS tube MP13 and a PMOS tube MP14;
In the bias current input circuit, a drain end of an NMOS tube MN1 is used for accessing bias current IB, a gate end and a drain end are connected together, and a source end is connected with a drain end of an NMOS tube MN 2; the gate end and the drain end of the NMOS tube MN2 are connected together, and the source end is grounded; the gate end of the NMOS tube MN1 is connected with the gate end of the NMOS tube MN3, and the gate end of the NMOS tube MN2 is connected with the gate end of the NMOS tube MN 4;
In the first transfer circuit, the source end of the PMOS tube MP1 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 2; the gate end and the drain end of the PMOS tube MP2 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 7; the source end of the NMOS tube MN7 is connected with the drain end of the NMOS tube MN3, and the gate end of the NMOS tube MN7 is connected with one of the reference voltages; the source end of the PMOS tube MP3 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 4; the gate end and the drain end of the PMOS tube MP4 are connected together, the drain end is connected with the drain end of the NMOS tube MN8, the source end of the NMOS tube MN8 is connected with the drain end of the NMOS tube MN3, and the gate end is connected with another reference voltage; the source end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN4, and the source end of the NMOS tube MN4 is grounded; the source end of the PMOS tube MP5 is used for accessing a power supply voltage, the gate end is connected with the gate end of the PMOS tube MP3, and the drain end is connected with the source end of the PMOS tube MP 6; the gate end of the PMOS tube MP6 is connected with the gate end of the PMOS tube MP4, the drain end is connected with the drain end of the NMOS tube MN5, the gate end and the drain end of the NMOS tube MN5 are connected together, the source end of the NMOS tube MN5 is connected with the drain end of the NMOS tube MN6, and the source end of the NMOS tube MN6 is grounded;
In the second transpose circuit, the source end of the PMOS tube MP9 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 10; the gate end and the drain end of the PMOS tube MP10 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 15; the source end of the NMOS tube MN15 is connected with the drain end of the NMOS tube MN11, and the gate end of the NMOS tube MN15 is connected with the differential input signal VINN; the source end of the PMOS tube MP11 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 12; the gate end and the drain end of the PMOS tube MP12 are connected together, the drain end is connected with the drain end of the NMOS tube MN16, the source end of the NMOS tube MN16 is connected with the drain end of the NMOS tube MN11, and the gate end is connected with a differential input signal VINP; the source end of the NMOS tube MN11 is connected with the drain end of the NMOS tube MN12, and the source end of the NMOS tube MN12 is grounded; the source end of the PMOS tube MP7 is used for accessing a power supply voltage, the drain end is connected with the source end of the PMOS tube MP8, the drain end of the PMOS tube MP8 is connected with the drain end of the NMOS tube MN9, the drain end of the PMOS tube MP8 also provides a switch control voltage VN, the gate end of the NMOS tube MN9 is connected with the gate end of the NMOS tube MN5, the source end of the NMOS tube MN9 is connected with the drain end of the NMOS tube MN10, the source end of the NMOS tube MN10 is grounded, the gate end of the NMOS tube MN10 is connected with the gate end of the NMOS tube MN6, and the drain end of the NMOS tube MN9 is grounded through a capacitor C1; the source end of the PMOS tube MP13 is used for accessing the power supply voltage, the drain end is connected with the source end of the PMOS tube MP14, the drain end of the PMOS tube MP14 is connected with the drain end of the NMOS tube MN13, the drain end of the PMOS tube MP14 also provides the switch control voltage VP, the gate end of the NMOS tube MN13 is connected with the gate end of the NMOS tube MN9, the source end of the NMOS tube MN13 is connected with the drain end of the NMOS tube MN14, the source end of the NMOS tube MN14 is grounded, the gate end of the NMOS tube MN14 is connected with the gate end of the NMOS tube MN10, and the drain end of the NMOS tube MN13 is grounded through a capacitor C2.
In a third aspect, a power amplifier is provided, including an input stage clamping circuit according to any one of the embodiments, wherein two input terminals of a differential comparator in the input stage clamping circuit are used as two differential signal input terminals of the input stage clamping circuit to access differential signals VINP and VINN, and a first terminal and a second terminal of a switch circuit in the input stage clamping circuit are used as two output terminals of the input stage clamping circuit to output the clamped differential signals VINP and VINN.
In one embodiment, the power amplifier further comprises a class D modulation circuit, two variable input resistors RIN1, two fixed input resistors RIN2, and an output driver stage circuit; one differential input end of the D-type modulating circuit is connected with a variable input resistor RIN1 and a fixed input resistor RIN2, the other differential input end is connected with the other variable input resistor RIN1 and the other fixed input resistor RIN2, the input stage clamping circuit is positioned between the variable input resistor RIN1 and the fixed input resistor RIN2, the two variable input resistors RIN1 respectively input differential signals VINP and VINN to the input stage clamping circuit, the input stage clamping circuit outputs two clamped differential signals VINP and VINN respectively through two input ends of the two fixed input resistors RIN2 to the D-type modulating circuit, and the D-type modulating circuit amplifies and modulates signals and outputs two pulse width modulating signals to the output driving stage circuit; the output driving circuit is used for responding to the two paths of pulse width modulation signals to output voltage to the loudspeaker.
In one embodiment, the class D modulation circuit includes a first integrator AMP1, a second integrator AMP2, a first pulse width modulator, and a second pulse width modulator;
The positive input end and the negative input end of the first integrator AMP1 are used as two input ends of the D-type modulation circuit, wherein the negative input end is used for being connected with a clamped signal VINN, the positive input end is used for being connected with a clamped signal VINN, the first output end of the first integrator AMP1 is connected with the positive input end of the second operational amplifier AMP2, the second output end of the first integrator AMP1 is connected with the negative input end of the second integrator AMP2, the first output end of the second integrator AMP2 is connected with the first input end of the first pulse width modulator, the second input end of the first pulse width modulator is used for being connected with a sawtooth wave signal, the second output end of the second integrator AMP2 is used for being connected with a sawtooth wave signal, the output end of the first integrator AMP2 is used as one output end of the D-type modulation circuit, the output end of the second integrator AMP2 is connected with one input end of the output driving stage circuit, and the output end of the second integrator AMP2 is used as the other output end of the D-type modulation circuit.
In a fourth aspect, an audio power amplification system is provided, including a speaker and a power amplifier as in any of the embodiments above, where an output terminal of the output driver stage circuit in the power amplifier is connected as an output terminal of the power amplifier to an input terminal of the speaker.
According to the input stage clamping circuit, the clamping method thereof, the power amplifier and the audio power amplifying system, the differential signals VINP and VINN and the two reference voltages VRFH and VRFL can be connected through the differential comparator, the difference value of the two reference voltages VRFH and VRFL is used as a detection threshold, and when the absolute value of the difference value of the two differential signals is larger than the difference value of the reference voltages, the output voltage of the differential comparator can conduct the switching circuit, so that the differential signals VINP and VINN are clamped, the output voltage of the power amplifier is limited, and the load of the power amplifier such as a loudspeaker cannot be damaged due to overlarge output voltage of the power amplifier. And for the power amplifier connected with the differential signal, the differential signal can be clamped by adopting the input stage clamping circuit in the embodiment, so that the requirement on the circuit matching property is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an input stage clamp circuit according to an embodiment of the invention;
FIG. 2 is a schematic diagram of an input stage clamp circuit according to another embodiment of the present invention;
FIG. 3 is a schematic diagram of a voltage division reference circuit according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a differential comparator according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a power amplifier according to an embodiment of the invention;
FIG. 6 is a schematic waveform diagram of the voltage at each node according to an embodiment of the invention;
FIG. 7 is a schematic diagram of waveforms of nodes of a power amplifier according to an embodiment of the present invention;
fig. 8a and 8b are schematic diagrams of a power amplifier according to an embodiment of the present invention;
Fig. 9 is a schematic diagram of a power amplifier according to another embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention. The various embodiments described below and their technical features can be combined with each other without conflict.
As described in the background art, a single-ended input/single-ended output input stage clamping circuit is currently used to implement the clamping function. The inventor has found that in a power amplifier connected to a differential signal, such as a class D power amplifier, two input stage clamping circuits of this type are required, and in order to ensure that the two input stage clamping circuits maintain consistent changes, the matching requirements for the two input stage clamping circuits are relatively high.
The embodiment of the invention provides an input stage clamping circuit and a clamping method thereof, and differential signals can be clamped by adopting the input stage clamping circuit, so that the requirement on the matching property of the circuit is reduced.
In one embodiment, as shown in fig. 1, the input stage clamping circuit includes a differential comparator CMP1 and a switching circuit 120, the differential comparator CMP1 includes four input terminals, and the switching circuit 120 includes a first terminal and a second terminal; the clamping method comprises the following steps: the four input ends of the differential comparator CMP1 are respectively connected to differential signals VINP and VINN of the input stage of the power amplifier and two different reference voltages, the difference between the two reference voltages is used as a detection threshold, and the first end and the second end of the switch circuit 120 are also connected to the differential signals VINP and VINN; if the absolute value of the difference between the differential signals VINP and VINN is greater than the difference between the two reference voltages, controlling the differential comparator CMP1 to output a turn-on control signal to turn on the switch circuit 120, so as to turn on the first end and the second end of the switch circuit 120; differential signals VINP and VINN are clamped with the switching circuit 120 turned on. The difference between the two reference voltages mentioned in this embodiment refers to the larger reference voltage minus the smaller reference voltage.
In the clamping method of the input stage clamping circuit in this embodiment, one differential comparator is utilized to access differential signals VINP and VINN and two reference voltages VRFH and VRFL, and the difference between the two reference voltages VRFH and VRFL is used as a detection threshold, and when the difference between the two differential signals is greater than the difference between the reference voltages, the switch circuit can be turned on, so as to clamp the differential signals VINP and VINN, thereby limiting the output voltage of the power amplifier, and protecting the load of the power amplifier such as a speaker from being damaged due to the overlarge output voltage of the power amplifier. When the input stage clamping circuit is applied to a power amplifier connected with differential signals, the differential signals can be clamped by the input stage clamping circuit in the embodiment, and the requirement on the matching property of the circuit is reduced.
In one embodiment, if the absolute value of the difference between the differential signals VINP and VINN is greater than the difference between the two reference voltages, the differential comparator CMP1 may be controlled to output a high level signal as the on control signal, and the switch circuit 120 is turned on in response to the high level signal.
Specifically, the differential comparator CMP1 further includes two output terminals, both of which are connected to the control terminal of the switching circuit 120; if the absolute value of the difference between the differential signals VINP and VINN is greater than the difference between the two reference voltages, the two output terminals of the differential comparator CMP1 are controlled to output high-level voltages, and the switch circuit 120 can be turned on by any one of the high-level output voltages.
In one embodiment, the reference voltages VRFH, VRFL may be symmetrical with respect to the input stage common mode voltage, which may improve clamping accuracy. For example, the input stage common mode voltage is 0.5VDD, and the reference voltages VRFH and VRFL are 0.5vdd+0.5 Δ and 0.5VDD-0.5 Δ, respectively, where the symbol Δ represents the difference of the reference voltages VRFH minus VRFL.
Fig. 1 is a schematic diagram of an input stage clamping circuit according to an embodiment of the invention, referring to fig. 1, the input stage clamping circuit includes a voltage division reference circuit 110, a differential comparator CMP1, and a switch circuit 120, the differential comparator CMP1 includes four input terminals, and the switch circuit 120 includes a first terminal, a second terminal, and a control terminal. The voltage division reference circuit 110 is connected to two input terminals of the differential comparator CMP1, and an output terminal of the differential comparator CMP1 is connected to a control terminal of the switching circuit 120.
The voltage division reference circuit 110 is configured to output two different reference voltages VRFH and VRFL. The four input ends of the differential comparator CMP1 are respectively corresponding to the differential signals VINP and VINN connected to the two reference voltages VRFH and VRFL and the power amplifier input stage, and the differential comparator CMP1 is configured to output a turn-on control signal when the absolute value of the difference between the differential signals VINP and VINN is greater than the difference between the two reference voltages. The first end and the second end of the switch circuit 120 are respectively used for accessing differential signals VINP and VINN, and the switch circuit 120 is used for responding to the conduction control signal output by the differential comparator CMP1 to conduct, so that the first end and the second end of the switch circuit 120 are connected to clamp the differential signals VINP and VINN. The difference between the two reference voltages mentioned in this embodiment refers to the larger reference voltage minus the smaller reference voltage.
In this embodiment, one differential comparator CMP1 is used to access differential signals VINP and VINN and two reference voltages VRFH and VRFL, and the difference between the two reference voltages VRFH and VRFL is used as a detection threshold, when the absolute value of the difference between the differential signals is greater than the difference between the reference voltages, the differential comparator CMP1 outputs a signal to turn on the switch circuit 120, and the turned on switch circuit 120 clamps the differential signals VINP and VINN, so as to limit the output voltage of the power amplifier, so that for the power amplifier accessing the differential signals, the input stage clamping circuit in this embodiment can clamp the differential signals, thereby reducing the requirement on circuit matching.
In one embodiment, referring to fig. 1, the differential comparator CMP1 further includes two output terminals, each of which is connected to the switch circuit 120, wherein one of the output terminals provides the output voltage VP, the other output terminal provides the output voltage VN, and the differential comparator CMP1 is configured to compare the difference between the differential signals VINP and VINN and the difference between the two reference voltages, and to set the output voltage VP to a high level when the difference between the differential signals VINP and VINN is determined to be greater than the difference between the reference voltages, and to set the output voltage VN to a high level when the difference between the differential signals VINN and VINP is determined to be greater than the difference between the reference voltages; the output voltage VP or VN at the high level may be used as the on control signal of the differential comparator CMP1, and the switch circuit 120 is turned on in response to the output voltage VP or VN at the high level.
Specifically, referring to fig. 2, the control end of the switch circuit 120 includes two control ends, namely a first control end and a second control end, the switch circuit 120 includes a first NMOS transistor Mn1 and a second NMOS transistor Mn2, the gate end of the first NMOS transistor Mn1 is used as the first control end to connect to one of the output ends of the differential comparator CMP1 to access the output voltage VP, the gate end of the second NMOS transistor Mn2 is used as the second control end to connect to the other output end of the differential comparator CMP1 to access the output voltage VN, the drain ends of the first NMOS transistor Mn1 and the second NMOS transistor Mn2 are used as the first end of the switch circuit 120 to access the differential signal VINP, and the source ends of the first NMOS transistor Mn1 and the second NMOS transistor Mn2 are used as the second end of the switch circuit 120 to access the differential signal VINN.
Referring to the voltage division reference circuit 110, specifically referring to fig. 2, the voltage division reference circuit 110 includes a first voltage division resistor R1, a second voltage division resistor R2, and a third voltage division resistor R3, where the first voltage division resistor R1, the second voltage division resistor R2, and the third voltage division resistor R3 are sequentially connected in series, and the first voltage division resistor R1 is connected to a supply voltage VDD, and the third voltage division resistor R3 is grounded; the voltage at the connection node of the first voltage dividing resistor R1 and the second voltage dividing resistor R2 is used as one of the reference voltages V RFH, and the voltage at the connection node of the second voltage dividing resistor R2 and the third voltage dividing resistor R3 is used as the other reference voltage V RFL. The resistance values of the first voltage dividing resistor R1 and the third voltage dividing resistor R3 may be equal.
When the resistance values of the voltage dividing resistors R1 and R3 are equal, symmetrical reference voltages V RFH and V RFL can be provided, and clamping accuracy can be improved. Assuming that the supply voltage is VDD, the relationship between the difference Δ of the reference voltages V RFH and V RFL and the voltage dividing resistors R1, R2, R3 is as follows:
As can be seen, when the resistances of the first voltage dividing resistor R1 and the third voltage dividing resistor R3 are equal, as shown in fig. 3, the reference voltages V RFH and V RFL are centered on the input stage common mode voltage of 0.5VDD, that is, the reference voltage V RFH is 0.5 Δ higher than 0.5VDD, the reference voltage V RFL is 0.5 Δ lower than 0.5VDD, and the reference voltages V RFH and V RFL are symmetrical, so that the clamping accuracy can be improved.
In one embodiment, referring to fig. 4, the differential comparator CMP1 includes a first transpose circuit 210 and a second transpose circuit 220; the first transfer circuit 210 includes two input terminals for respectively accessing the two different reference voltages V RFH and V RFL, and the first transfer circuit 210 is configured to convert the reference voltage difference into a reference current IRFHL; the second transpose circuit 220 is connected to the first transpose circuit 210, and the second transpose circuit 220 further includes two input terminals and two output terminals, the two input terminals are respectively connected to the differential signals VINP and VINN, the two output terminals are respectively configured to output the output voltage VP and the output voltage VN, the second transpose circuit 220 is configured to convert the differential signal VINP into a current signal IN, convert the differential signal VINP into a current signal IP, and when the current signal IP is greater than the reference current IRFHL, set the output voltage VP to a high level, and when the current signal IN is greater than the reference current IRFHL, set the output voltage VN to a high level.
Specifically, referring to fig. 4, the differential comparator CMP1 further includes a bias current input circuit 230 for receiving a bias current IB and providing the bias current IB to the first transpose circuit 210 and the second transpose circuit 220, so that the response speed of the differential comparator CMP1 can be improved. Specifically, the bias current circuit 230 includes an NMOS transistor MN1 and an NMOS transistor MN2; the first transfer circuit 210 includes an NMOS transistor MN3, an NMOS transistor MN4, an NMOS transistor MN5, an NMOS transistor MN6, an NMOS transistor MN7, an NMOS transistor MN8, a PMOS transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, a PMOS transistor MP4, a PMOS transistor MP5, and a PMOS transistor MP6; the second transpose circuit 220 includes an NMOS transistor MN9, an NMOS transistor MN10, an NMOS transistor MN11, an NMOS transistor MN12, an NMOS transistor MN13, an NMOS transistor MN14, an NMOS transistor MN15, an NMOS transistor MN16, a PMOS transistor MP7, a PMOS transistor MP8, a PMOS transistor MP9, a PMOS transistor MP10, a PMOS transistor MP11, a PMOS transistor MP12, a PMOS transistor MP13, and a PMOS transistor MP14;
In the bias current input circuit 230, the drain terminal of the NMOS transistor MN1 is used for accessing the bias current IB, the gate terminal and the drain terminal are connected together, and the source terminal is connected with the drain terminal of the NMOS transistor MN 2; the gate end and the drain end of the NMOS tube MN2 are connected together, and the source end is grounded; the gate end of the NMOS transistor MN1 is connected to the gate end of the NMOS transistor MN3 in the first transpose circuit 210 and the gate end of the NMOS transistor MN11 in the second transpose circuit 210, so as to provide bias current to the NMOS transistor MN3 and the NMOS transistor MN11, and the gate end of the NMOS transistor MN2 in the first transpose circuit 210 is connected to the gate end of the NMOS transistor MN4 of the gate end of the NMOS transistor MN12 in the second transpose circuit 220, so as to provide bias current to the NMOS transistor MN4 and the NMOS transistor MN12, thereby improving the response speed of the NMOS transistor MN3, the NMOS transistor MN4, the NMOS transistor MN11 and the NMOS transistor MN12, and improving the response speed of the differential comparator CMP 1.
In the first transfer circuit 210, the source end of the PMOS MP1 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of the PMOS MP 2; the gate end and the drain end of the PMOS tube MP2 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 7; the source end of the NMOS tube MN7 is connected with the drain end of the NMOS tube MN3, and the gate end of the NMOS tube is connected with the reference voltage V RFL; the source end of the PMOS tube MP3 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 4; the gate end and the drain end of the PMOS tube MP4 are connected together, the drain end is connected with the drain end of the NMOS tube MN8, the source end of the NMOS tube MN8 is connected with the drain end of the NMOS tube MN3, and the gate end is connected with the reference voltage V RFH; the source end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN4, and the source end of the NMOS tube MN4 is grounded; the source end of the PMOS tube MP5 is used for accessing a power supply voltage, the gate end is connected with the gate end of the PMOS tube MP3, and the drain end is connected with the source end of the PMOS tube MP 6; the gate end of the PMOS tube MP6 is connected with the gate end of the PMOS tube MP4, the drain end is connected with the drain end of the NMOS tube MN5, the gate end and the drain end of the NMOS tube MN5 are connected together, the source end of the NMOS tube MN5 is connected with the drain end of the NMOS tube MN6, and the source end of the NMOS tube MN6 is grounded.
In the second transpose circuit 220, the source end of the PMOS MP9 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of the PMOS MP 10; the gate end and the drain end of the PMOS tube MP10 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 15; the source end of the NMOS tube MN15 is connected with the drain end of the NMOS tube MN11, and the gate end of the NMOS tube MN is connected with the differential signal VINN; the source end of the PMOS tube MP11 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 12; the gate end and the drain end of the PMOS tube MP12 are connected together, the drain end is connected with the drain end of the NMOS tube MN16, the source end of the NMOS tube MN16 is connected with the drain end of the NMOS tube MN11, and the gate end is connected with a differential signal VINP; the source end of the NMOS tube MN11 is connected with the drain end of the NMOS tube MN12, and the source end of the NMOS tube MN12 is grounded; the source end of the PMOS tube MP7 is used for accessing a power supply voltage, the drain end is connected with the source end of the PMOS tube MP8, the drain end of the PMOS tube MP8 is connected with the drain end of the NMOS tube MN9, the drain end of the PMOS tube MP8 also provides a switch control voltage VN, the gate end of the NMOS tube MN9 is connected with the gate end of the NMOS tube MN5, the source end of the NMOS tube MN9 is connected with the drain end of the NMOS tube MN10, the source end of the NMOS tube MN10 is grounded, the gate end of the NMOS tube MN10 is connected with the gate end of the NMOS tube MN6, and the drain end of the NMOS tube MN9 is grounded through a capacitor C1; the source end of the PMOS tube MP13 is used for accessing the power supply voltage, the drain end is connected with the source end of the PMOS tube MP14, the drain end of the PMOS tube MP14 is connected with the drain end of the NMOS tube MN13, the drain end of the PMOS tube MP14 also provides the switch control voltage VP, the gate end of the NMOS tube MN13 is connected with the gate end of the NMOS tube MN9, the source end of the NMOS tube MN13 is connected with the drain end of the NMOS tube MN14, the source end of the NMOS tube MN14 is grounded, the gate end of the NMOS tube MN14 is connected with the gate end of the NMOS tube MN10, and the drain end of the NMOS tube MN13 is grounded through a capacitor C2.
In this particular circuit, differential signals VINP and VINN, reference voltages V RFH and V RFL, and bias current IB are input signals, and switch control voltages VP and VN are output signals. The differential signals VINP and VINN convert the voltage signal into current signals IN and IP through the differential comparator CMP1, and compare the current signals with the reference current IRFHL converted from the voltage difference between the reference voltages VRFH and VRFL, when the current IP is greater than the current IRFHL, the difference between the differential signal VINP and the VINN is greater than the voltage difference between the reference voltages VRFH and VRFL, the voltage VP is set to a high level, otherwise to a low level, when the current IN is greater than the current IRFHL, the difference between the differential signal VINN and the VINP is greater than the voltage difference between the reference voltages VRFH and VRFL, and the voltage VN is set to a high level, otherwise to a low level.
The embodiment of the invention also provides a power amplifier which comprises the input stage clamping circuit in any embodiment. Two input ends of the differential comparator in the input stage clamping circuit are used as two differential signal input ends of the input stage clamping circuit to be connected with differential signals VINP and VINN, and a first end and a second end of the switch circuit in the input stage clamping circuit are used as two output ends of the input stage clamping circuit to output the clamped differential signals VINP and VINN.
In one embodiment, the power amplifier may be a gain-adjustable class D power amplifier, referring to fig. 5, and further includes a class D modulation circuit 510, two variable input resistors RIN1, two fixed input resistors RIN2, and an output driver stage circuit 520; one differential input end of the class D modulation circuit 510 is connected to a variable input resistor RIN1 and a fixed input resistor RIN2 as a differential input end of the power amplifier input stage, the other differential input end is connected to the other variable input resistor RIN1 and the other fixed input resistor RIN2 as the other differential input end of the power amplifier input stage, the input stage clamping circuit 100 is located between the variable input resistor RIN1 and the fixed input resistor RIN2, the two variable input resistors RIN1 respectively input differential signals VINP and VINN to two differential signal input ends of the input stage clamping circuit 100, and the two output ends of the input stage clamping circuit 100 output two differential signals VINP and VINN clamped by the input stage clamping circuit 100 and respectively transmit the differential signals VINP and VINN to the two input ends of the class D modulation circuit 510 through the two fixed input resistors RIN 2. Fig. 8a and 8b are schematic diagrams showing specific connection structures of the input stage clamping circuit 100 and the class D modulation circuit 510. The class D modulation circuit 510 is configured to amplify and modulate a signal and output the signal to the output driver stage 520. The output driver 520 is configured to output a voltage to the speaker in response to the two pulse width modulated signals.
Specifically, the differential signals VINP and VINN may be voltage signals converted from the differential current signals INP and INN, as shown in fig. 5, the front ends of the two variable input resistors RIN1 are respectively connected to a capacitor C2, and the differential current signals INP and INN are respectively filtered by the C2 and the variable input resistor RIN1 to form the differential signals VINP and VINN. Fig. 6 is a schematic diagram showing waveforms of the differential signals INP and INN, the voltages VP and VN, and the differential signals VINP and VINN according to an embodiment of the invention.
In this embodiment, by adding the input stage clamping circuit 100 between the variable input resistor RIN1 and the fixed input resistor RIN2 with adjustable gain at the input terminal, the input stage clamping circuit 100 detects the magnitudes of the input differential signals VINP and VINN, and once the difference between the input differential signals VINP and VINN exceeds the difference between the reference voltages VRFH and VRFL, the differential signals VINP and VINN will be clamped, and the output voltage VO provided to the speaker by the class D power amplifier will also be clamped, thereby limiting the magnitude of the output voltage of the class D power amplifier, avoiding damage to the load due to excessive input signals, and protecting the speaker from damage due to excessive output voltage of the power amplifier.
As shown in fig. 7, waveforms of the differential signals INP and INN, the clamped differential signals VINP and VINN, and the output voltage VO of the power amplifier are shown, and when the difference between the differential signals VINP and VINN is greater than the reference voltage difference Δ, the differential signals VINP and VINN are clamped at +0.5Δ and-0.5Δ, respectively, and the output voltage VO of the power amplifier is clamped at Vclamp. The clamp voltage Vclamp satisfies the following relationship:
Where RF is the power amplifier feedback resistor, as shown in fig. 5, the input of the class D power modulation circuit 510 and the output of the output driver stage circuit 520 are connected RF by the feedback resistor.
As can be seen from the above, in the present embodiment, the clamp voltage Vclamp is positively correlated with the fixed resistor RIN2, and is independent of the gain-adjustable resistor RIN1, and it can be seen that by providing the input stage clamp circuit between the gain-adjustable resistor and the fixed resistor, the same clamp voltage can be provided to be compatible with different gains of the power amplifier, and it is unnecessary to design different input stage clamp circuits for the power amplifier with varying gains, thereby simplifying the circuit structure.
Specifically, please refer to fig. 8a and 8b, which are schematic diagrams illustrating a power amplifier according to an embodiment of the present invention. As shown in fig. 8b, the class D modulation circuit includes a first integrator AMP1, a second integrator AMP2, a first pulse width modulator comp1, and a second pulse width modulator comp2;
The positive input end and the negative input end of the first integrator AMP1 are used as two input ends of the class D modulation circuit, wherein the negative input end is used for being connected with a clamped signal VINP, the positive input end is used for being connected with a clamped signal VINN, the first output end of the first integrator AMP1 is connected with the positive input end of the second integrator AMP2, the second output end of the first integrator AMP1 is connected with the negative input end of the second integrator AMP2, the first output end of the second integrator AMP2 is connected with the first input end of the first pulse width modulator comp1, the second input end of the first pulse width modulator comp1 is used for being connected with a sawtooth wave signal, the second output end of the second integrator AMP2 is used for being connected with the first input end of the second pulse width modulator comp2, the output end of the first pulse width modulator comp1 is used as the negative input end of the second integrator AMP2, and the output end of the second integrator AMP2 is connected with the output end of the class D modulation circuit 520, and the second output end of the second integrator AMP2 is used as the output end of the other class D modulation circuit 510. Specifically, the first integrator AMP1 and the second integrator AMP2 are also connected to the common mode reference voltages VCM1 and VCM2, respectively.
In other embodiments, the power amplifier may be a class D power amplifier with a fixed gain, referring to fig. 9, which is different from the embodiment corresponding to fig. 5 in that there is no variable input resistor RIN1, and the differential current signals INP and INN are respectively passed through the capacitor C2 to directly form the differential signals VINP and VINN to be input to the differential input terminal of the input stage clamping circuit 100.
In summary, the embodiment of the invention can clamp the input signal by adding the input stage clamping circuit to the input stage of the power amplifier, thereby limiting the output voltage of the power amplifier within a certain range, avoiding the damage of the load at the output end of the power amplifier due to the overlarge input signal and realizing the clamping protection function. In addition, the clamping circuit of one input stage in the embodiment of the invention can clamp differential signals, and has low requirement on circuit matching. In addition, for a gain-adjustable power amplifier, such as a class D power amplifier, by splitting an input variable resistor of the power amplifier into a variable resistor portion and a fixed resistor portion and then disposing an input stage clamping circuit between the variable resistor and the fixed resistor, the power amplifier output clamping voltage can be made independent of the change in gain, and it is unnecessary to design different input stage clamping circuits for the power amplifier whose gain is changed, and the circuit structure can be simplified.
The embodiment of the invention also provides an audio power amplification system which comprises a loudspeaker and the power amplifier in any embodiment, wherein the output end of the output driving stage circuit in the power amplifier is used as the output end of the power amplifier to be connected with the input end of the loudspeaker.
Referring to fig. 5 and 8b, the audio power amplifier system further includes an external LC filter, and an output end of the power amplifier is connected to the speaker through the external LC filter.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (9)

1. A clamping method of an input stage clamping circuit, characterized in that the input stage clamping circuit comprises a differential comparator and a switching circuit, wherein the differential comparator comprises four input ends, and the switching circuit comprises a first end and a second end;
The differential comparator comprises a first transposition circuit and a second transposition circuit; the first transfer circuit comprises two input ends, the two input ends are respectively used for being correspondingly connected with two different reference voltages, and the first transfer circuit is used for converting the reference voltage difference value into a reference current; the second transpose circuit is connected with the first transpose circuit, and further comprises two input ends and two output ends, wherein the two input ends are respectively used for accessing differential signals VINP and VINN, the two output ends are respectively used for outputting voltage VP and voltage VN, the second transpose circuit is used for converting the differential signals VINP and VINN into current signals IP and IN, and is used for setting the output voltage VP to be high level when the current signal IP is greater than a reference current, and setting the output voltage VN to be high level when the current signal IN is greater than the reference current;
The clamping method comprises the following steps:
The four input ends of the differential comparator are respectively connected with differential signals VINP and VINN and two different reference voltages, the difference value of the two reference voltages is used as a detection threshold value, and the first end and the second end of the switching circuit are also connected with the differential signals VINP and VINN;
If the absolute value of the difference value of the differential signals VINP and VINN is larger than the difference value of the two reference voltages, controlling the differential comparator to output a conduction control signal to conduct the switching circuit so as to switch on the first end and the second end of the switching circuit;
And clamping the differential signals VINP and VINN by using the on switch circuit.
2. The method of claim 1, wherein if the absolute value of the difference between the differential signals VINP and VINN is greater than the difference between the two reference voltages, controlling the differential comparator to output a high signal as the on control signal.
3. The method of claim 2, wherein the differential comparator further comprises two output terminals, each connected to a control terminal of the switching circuit; and if the absolute value of the difference value of the differential signals VINP and VINN is larger than the difference value of the two reference voltages, controlling the two output ends of the differential comparator to output high-level voltage.
4. The method of claim 1, wherein the two reference voltages are symmetrical with respect to an input stage common mode voltage.
5. The input stage clamping circuit is characterized by comprising a voltage division reference circuit, a differential comparator and a switching circuit, wherein the differential comparator comprises four input ends, the switching circuit comprises a first end, a second end and a control end, the voltage division reference circuit is connected with two input ends of the differential comparator, and an output end of the differential comparator is connected with the control end of the switching circuit;
the voltage division reference circuit is used for outputting two different reference voltages;
The four input ends of the differential comparator are respectively used for correspondingly accessing the two reference voltages and the differential signals VINP and VINN, and the differential comparator is used for outputting a conduction control signal when the absolute value of the difference value of the differential signals VINP and VINN is larger than the difference value of the two reference voltages;
The first end and the second end of the switching circuit are respectively used for being connected with differential signals VINP and VINN, and the switching circuit is used for responding to the conduction control signals output by the differential comparator to conduct, so that the first end and the second end of the switching circuit are connected to clamp the differential signals VINP and VINN;
The differential comparator comprises a first transposition circuit and a second transposition circuit; the first transpose circuit comprises two input ends, the two input ends are respectively used for correspondingly accessing the two different reference voltages, and the transpose circuit is used for converting the reference voltage difference value into a reference current; the second transpose circuit is connected with the first transpose circuit, the second transpose circuit further comprises two input ends and two output ends, the two input ends are respectively used for being connected with differential signals VINP and VINN, the two output ends are respectively used for outputting voltage VP and voltage VN, the second transpose circuit is used for converting the differential signals VINP and VINN into current signals IP and IN, and is used for setting the output voltage VP to be high level when the current signal IP is larger than a reference current, and setting the output voltage VN to be high level when the current signal IN is larger than the reference current.
6. The input stage clamping circuit of claim 5, wherein the differential comparator further comprises two output terminals, each connected to a control terminal of the switching circuit to provide output voltages VP and VN;
The differential comparator is used for comparing the difference value of the differential signals VINP and VINN with the difference value of the two reference voltages, setting the output voltage VP to a high level when the difference value of the differential signals VINP and VINN is determined to be larger than the difference value of the reference voltages, and setting the output voltage VN to a high level when the difference value of the differential signals VINN and VINP is determined to be larger than the difference value of the reference voltages; the switching circuit is turned on in response to the output voltage VP or VN being high.
7. The input stage clamping circuit of claim 6, wherein the switching circuit comprises two control terminals, namely a first control terminal and a second control terminal, the switching circuit comprises a first NMOS transistor and a second NMOS transistor, the gate terminal of the first NMOS transistor is used as the first control terminal to be connected with one output terminal of the differential comparator to be connected with the output voltage VP, the gate terminal of the second NMOS transistor is used as the second control terminal to be connected with the other output terminal of the differential comparator to be connected with the output voltage VN, the drain terminals of the first NMOS transistor and the second NMOS transistor are used as the first terminal of the switching circuit to be connected with the differential signal VINP, and the source terminals of the first NMOS transistor and the second NMOS transistor are used as the second terminal of the switching circuit to be connected with the differential signal VINN.
8. The input stage clamping circuit of claim 5, wherein the voltage division reference circuit comprises a first voltage division resistor, a second voltage division resistor and a third voltage division resistor which are sequentially connected in series, wherein the first voltage division resistor is connected to a supply voltage, the third voltage division resistor is grounded, and the resistance values of the first voltage division resistor and the third voltage division resistor are equal; the voltage at the connecting node of the first voltage dividing resistor and the second voltage dividing resistor is used as one of the reference voltages, and the voltage at the connecting node of the second voltage dividing resistor and the third voltage dividing resistor is used as the other reference voltage.
9. The input stage clamp circuit of claim 5, wherein the differential comparator further comprises a bias current input circuit comprising an NMOS transistor MN1 and an NMOS transistor MN2; the first transfer circuit comprises an NMOS tube MN3, an NMOS tube MN4, an NMOS tube MN5, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8, a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5 and a PMOS tube MP6; the second transpose circuit comprises an NMOS tube MN9, an NMOS tube MN10, an NMOS tube MN11, an NMOS tube MN12, an NMOS tube MN13, an NMOS tube MN14, an NMOS tube MN15, an NMOS tube MN16, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, a PMOS tube MP10, a PMOS tube MP11, a PMOS tube MP12, a PMOS tube MP13 and a PMOS tube MP14;
In the bias current input circuit, a drain end of an NMOS tube MN1 is used for accessing bias current IB, a gate end and a drain end are connected together, and a source end is connected with a drain end of an NMOS tube MN 2; the gate end and the drain end of the NMOS tube MN2 are connected together, and the source end is grounded; the gate end of the NMOS tube MN1 is connected with the gate end of the NMOS tube MN3 and the gate end of the NMOS tube MN11, and the gate end of the NMOS tube MN2 is connected with the gate end of the NMOS tube MN4 and the gate end of the NMOS tube MN 12;
In the first transfer circuit, the source end of the PMOS tube MP1 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 2; the gate end and the drain end of the PMOS tube MP2 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 7; the source end of the NMOS tube MN7 is connected with the drain end of the NMOS tube MN3, and the gate end of the NMOS tube MN7 is connected with one of the reference voltages; the source end of the PMOS tube MP3 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 4; the gate end and the drain end of the PMOS tube MP4 are connected together, the drain end is connected with the drain end of the NMOS tube MN8, the source end of the NMOS tube MN8 is connected with the drain end of the NMOS tube MN3, and the gate end is connected with another reference voltage; the source end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN4, and the source end of the NMOS tube MN4 is grounded; the source end of the PMOS tube MP5 is used for accessing a power supply voltage, the gate end is connected with the gate end of the PMOS tube MP3, and the drain end is connected with the source end of the PMOS tube MP 6; the gate end of the PMOS tube MP6 is connected with the gate end of the PMOS tube MP4, the drain end is connected with the drain end of the NMOS tube MN5, the gate end and the drain end of the NMOS tube MN5 are connected together, the source end of the NMOS tube MN5 is connected with the drain end of the NMOS tube MN6, and the source end of the NMOS tube MN6 is grounded;
In the second transpose circuit, the source end of the PMOS tube MP9 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 10; the gate end and the drain end of the PMOS tube MP10 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 15; the source end of the NMOS tube MN15 is connected with the drain end of the NMOS tube MN11, and the gate end of the NMOS tube MN15 is connected with the differential input signal VINN; the source end of the PMOS tube MP11 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 12; the gate end and the drain end of the PMOS tube MP12 are connected together, the drain end is connected with the drain end of the NMOS tube MN16, the source end of the NMOS tube MN16 is connected with the drain end of the NMOS tube MN11, and the gate end is connected with a differential input signal VINP; the source end of the NMOS tube MN11 is connected with the drain end of the NMOS tube MN12, and the source end of the NMOS tube MN12 is grounded; the source end of the PMOS tube MP7 is used for accessing a power supply voltage, the drain end is connected with the source end of the PMOS tube MP8, the drain end of the PMOS tube MP8 is connected with the drain end of the NMOS tube MN9, the drain end of the PMOS tube MP8 also provides a switch control voltage VN, the gate end of the NMOS tube MN9 is connected with the gate end of the NMOS tube MN5, the source end of the NMOS tube MN9 is connected with the drain end of the NMOS tube MN10, the source end of the NMOS tube MN10 is grounded, the gate end of the NMOS tube MN10 is connected with the gate end of the NMOS tube MN6, and the drain end of the NMOS tube MN9 is grounded through a capacitor C1; the source end of the PMOS tube MP13 is used for accessing the power supply voltage, the drain end is connected with the source end of the PMOS tube MP14, the drain end of the PMOS tube MP14 is connected with the drain end of the NMOS tube MN13, the drain end of the PMOS tube MP14 also provides the switch control voltage VP, the gate end of the NMOS tube MN13 is connected with the gate end of the NMOS tube MN9, the source end of the NMOS tube MN13 is connected with the drain end of the NMOS tube MN14, the source end of the NMOS tube MN14 is grounded, the gate end of the NMOS tube MN14 is connected with the gate end of the NMOS tube MN10, and the drain end of the NMOS tube MN13 is grounded through a capacitor C2.
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