CN111900940A - Input stage clamping circuit and clamping method thereof, and power amplifier - Google Patents

Input stage clamping circuit and clamping method thereof, and power amplifier Download PDF

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Publication number
CN111900940A
CN111900940A CN202010742301.7A CN202010742301A CN111900940A CN 111900940 A CN111900940 A CN 111900940A CN 202010742301 A CN202010742301 A CN 202010742301A CN 111900940 A CN111900940 A CN 111900940A
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circuit
nmos tube
input
voltage
tube
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CN111900940B (en
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胡孔生
杨志飞
张海军
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52Circuit arrangements for protecting such amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52Circuit arrangements for protecting such amplifiers
    • H03F1/523Circuit arrangements for protecting such amplifiers for amplifiers using field-effect devices
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04RLOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00Circuits for transducers, loudspeakers or microphones
    • H04R3/007Protection circuits for transducers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Signal Processing (AREA)
  • Manipulation Of Pulses (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses an input stage clamping circuit and a clamping method thereof, a power amplifier and an audio power amplification system. The input stage clamping circuit comprises a differential comparator, and the differential comparator comprises four input ends; the four input ends of the differential comparator are respectively connected with differential signals VINP and VINN of the input stage of the power amplifier and two different reference voltages; if the absolute value of the difference value obtained by subtracting the VINN from the difference signal VINP is larger than the difference value of the two reference voltages, the switch circuit is switched on; and clamping the differential signals VINP and VINN by utilizing the conducted switch circuit.

Description

Input stage clamping circuit and clamping method thereof, and power amplifier
Technical Field
The invention relates to the technical field of power amplifiers, in particular to an input stage clamping circuit applied to a power amplifier and a clamping method thereof, the power amplifier and an audio power amplification system.
Background
The power amplifier usually introduces an input stage clamping circuit at the input stage to detect the magnitude of the input signal and clamp the input signal, so as to limit the output voltage to be kept within a certain range and avoid the load at the output end of the power amplifier, such as a loudspeaker, from being damaged due to the excessive input signal.
Currently, a single-ended input and single-ended output input stage clamping circuit is adopted to realize the clamping function. The inventor researches and discovers that two input stage clamping circuits are needed for a power amplifier for accessing a differential signal, such as a class-D power amplifier, and the matching requirement of the two input stage clamping circuits is higher in order to ensure that two clamping output signals keep consistent and change.
Disclosure of Invention
Based on this, the invention provides an input stage clamping circuit and a clamping method thereof, a power amplifier and an audio power amplifying system, which reduce the requirement on the matching of the circuit.
In a first aspect, a clamping method of an input stage clamping circuit is provided, the input stage clamping circuit comprises a differential comparator and a switching circuit, the differential comparator comprises four input ends, and the switching circuit comprises a first end and a second end; the clamping method comprises the following steps:
the four input ends of the differential comparator are respectively connected with differential signals VINP and VINN of the input stage of the power amplifier and two different reference voltages, the difference value of the two reference voltages is used as a detection threshold value, and the first end and the second end of the switch circuit are also connected with the differential signals VINP and VINN;
if the absolute value of the difference signals VINP and VINN is larger than the difference value of the two reference voltages, controlling the differential comparator to output a conduction control signal to conduct the switch circuit, so as to switch on the first end and the second end of the switch circuit;
and clamping the differential signals VINP and VINN by utilizing the conducted switch circuit.
In one embodiment, if the absolute value of the difference between the differential signals VINP and VINN is greater than the difference between the two reference voltages, the differential comparator is controlled to output a high-level signal as the turn-on control signal.
In one embodiment, the differential comparator further comprises two output terminals, each of which is connected to the control terminal of the switching circuit; and if the absolute value of the difference signals VINP and VINN is larger than the difference value of the two reference voltages, controlling the two output ends of the differential comparator to output high-level voltage.
In one embodiment, the two reference voltages are symmetrical with respect to the input stage common mode voltage.
In a second aspect, an input stage clamping circuit is provided, which includes a voltage division reference circuit, a differential comparator and a switch circuit, where the differential comparator includes four input terminals, the switch circuit includes a first terminal, a second terminal and a control terminal, the voltage division reference circuit is connected to two of the input terminals of the differential comparator, and the output terminal of the differential comparator is connected to the control terminal of the switch circuit;
the voltage division reference circuit is used for outputting two different reference voltages;
the four input ends of the differential comparator are respectively used for correspondingly accessing the two reference voltages and differential signals VINP and VINN of the input stage of the power amplifier, and the differential comparator is used for outputting a conduction control signal when the absolute value of the difference value of the differential signals VINP and VINN is greater than the difference value of the two reference voltages;
the first end and the second end of the switch circuit are respectively used for accessing differential signals VINP and VINN, and the switch circuit is used for responding to the conduction control signal output by the differential comparator to conduct, so that the first end and the second end of the switch circuit are switched on to clamp the differential signals VINP and VINN.
In one embodiment, the differential comparator further comprises two output terminals, each connected to the switching circuit to provide output voltages VP and VN;
the differential comparator is used for comparing the difference value of the differential signals VINP and VINN with the difference value of the two reference voltages, setting the output voltage VP to be at a high level when the difference value of the differential signals VINP and VINN is judged to be larger than the difference value of the reference voltages, and setting the output voltage VN to be at a high level when the difference value of the differential signals VINN and VINP is judged to be larger than the difference value of the reference voltages; the switch circuit is turned on in response to the output voltage VP or VN being high level.
In one embodiment, the switch circuit includes two control terminals, which are a first control terminal and a second control terminal, respectively, the switch circuit includes a first NMOS transistor and a second NMOS transistor, a gate terminal of the first NMOS transistor is used as the first control terminal to connect one of the output terminals of the differential comparator to access the output voltage VP, a gate terminal of the second NMOS transistor is used as the second control terminal to connect the other output terminal of the differential comparator to access the output voltage VN, drain terminals of the first NMOS transistor and the second NMOS transistor are both used as the first terminal of the switch circuit to access the differential signal VINP, and a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor are both used as the second terminal of the switch circuit to access the differential signal VINN.
In one embodiment, the voltage division reference circuit includes a first voltage division resistor, a second voltage division resistor, and a third voltage division resistor, which are connected in series in sequence, wherein the first voltage division resistor is connected to a power supply voltage, the third voltage division resistor is connected to ground, and the first voltage division resistor and the third voltage division resistor have equal resistance values; the voltage at the connection node of the first voltage-dividing resistor and the second voltage-dividing resistor is used as one reference voltage, and the voltage at the connection node of the second voltage-dividing resistor and the third voltage-dividing resistor is used as the other reference voltage.
In one embodiment, the differential comparator comprises a first transpose circuit and a second transpose circuit;
the first transposition circuit comprises two input ends and an output end, the two input ends are respectively used for correspondingly accessing the two different reference voltages, and the transposition circuit is used for converting the reference voltage difference into the reference current;
the second transpose circuit is connected with the first transpose circuit, and further comprises two input ends and two output ends, wherein the two output ends are respectively used for accessing a differential signal VINP and a differential signal VINN, the two output ends are respectively used for outputting the output voltage VP and the output voltage VN, the second transpose circuit is used for converting the differential signal VINP and the differential signal VINN into the current signals IP and IN, and is used for setting the output voltage VP to be at a high level when the current signal IP is greater than a reference current, and setting the output voltage VN to be at a high level when the current signal IN is greater than the reference current.
The differential comparator further comprises a bias current input circuit, and the bias current input circuit comprises an NMOS transistor MN1 and an NMOS transistor MN 2; the first switching circuit comprises an NMOS tube MN3, an NMOS tube MN4, an NMOS tube MN5, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8, a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5 and a PMOS tube MP 6; the second transpose circuit comprises an NMOS tube MN9, an NMOS tube MN10, an NMOS tube MN11, an NMOS tube MN12, an NMOS tube MN13, an NMOS tube MN14, an NMOS tube MN15, an NMOS tube MN16, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, a PMOS tube MP10, a PMOS tube MP11, a PMOS tube MP12, a PMOS tube MP13 and a PMOS tube MP 14;
in the bias current input circuit, the drain terminal of an NMOS (N-channel metal oxide semiconductor) tube MN1 is used for accessing a bias current IB, the gate terminal and the drain terminal are connected together, and the source terminal is connected with the drain terminal of an NMOS tube MN 2; the gate end and the drain end of the NMOS tube MN2 are connected together, and the source end is grounded; the gate end of the NMOS tube MN1 is connected with the gate end of the NMOS tube MN3, and the gate end of the NMOS tube MN2 is connected with the gate end of the NMOS tube MN 4;
in the first switching circuit, the source end of a PMOS tube MP1 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of a PMOS tube MP 2; the gate end and the drain end of the PMOS tube MP2 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 7; the source end of the NMOS tube MN7 is connected with the drain end of the NMOS tube MN3, and the gate end is connected with one of the reference voltages; the source end of the PMOS tube MP3 is used for accessing power supply voltage, the grid end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 4; the gate end and the drain end of the PMOS tube MP4 are connected together, the drain end is connected with the drain end of the NMOS tube MN8, the source end of the NMOS tube MN8 is connected with the drain end of the NMOS tube MN3, and the gate end is connected with another reference voltage; the source end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN4, and the source end of the NMOS tube MN4 is grounded; the source end of the PMOS tube MP5 is used for accessing power supply voltage, the gate end of the PMOS tube MP3 is connected with the gate end of the PMOS tube MP3, and the drain end of the PMOS tube MP6 is connected with the source end of the PMOS tube MP 6; the gate end of the PMOS tube MP6 is connected with the gate end of the PMOS tube MP4, the drain end of the PMOS tube MP6 is connected with the drain end of the NMOS tube MN5, the gate end and the drain end of the NMOS tube MN5 are connected together, the source end of the NMOS tube MN5 is connected with the drain end of the NMOS tube MN6, and the source end of the NMOS tube MN6 is grounded;
in the second transpose circuit, the source end of a PMOS transistor MP9 is used for accessing a supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of a PMOS transistor MP 10; the gate end and the drain end of the PMOS tube MP10 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 15; the source end of the NMOS tube MN15 is connected with the drain end of the NMOS tube MN11, and the gate end is accessed with a differential input signal VINN; the source end of the PMOS tube MP11 is used for accessing power supply voltage, the grid end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 12; the gate end and the drain end of the PMOS tube MP12 are connected together, the drain end is connected with the drain end of the NMOS tube MN16, the source end of the NMOS tube MN16 is connected with the drain end of the NMOS tube MN11, and the gate end is accessed to a differential input signal VINP; the source end of the NMOS tube MN11 is connected with the drain end of the NMOS tube MN12, and the source end of the NMOS tube MN12 is grounded; the source end of a PMOS tube MP7 is used for accessing power supply voltage, the drain end of the PMOS tube MP7 is connected with the source end of a PMOS tube MP8, the drain end of a PMOS tube MP8 is connected with the drain end of an NMOS tube MN9, the drain end of the PMOS tube MP8 also provides a switch control voltage VN, the gate end of an NMOS tube MN9 is connected with the gate end of an NMOS tube MN5, the source end of the NMOS tube MN9 is connected with the drain end of the NMOS tube MN10, the source end of the NMOS tube MN10 is grounded, the gate end of the NMOS tube MN10 is connected with the gate end of an NMOS tube MN6, and the drain end of the NMOS tube MN9 is grounded through a capacitor C1; the source end of the PMOS tube MP13 is used for accessing power supply voltage, the drain end of the PMOS tube MP13 is connected with the source end of the PMOS tube MP14, the drain end of the PMOS tube MP14 is connected with the drain end of the NMOS tube MN13, the drain end of the PMOS tube MP14 also provides a switch control voltage VP, the gate end of the NMOS tube MN13 is connected with the gate end of the NMOS tube MN9, the source end of the NMOS tube MN13 is connected with the drain end of the NMOS tube MN14, the source end of the NMOS tube MN14 is grounded, the gate end of the NMOS tube MN14 is connected with the gate end of the NMOS tube MN10, and the drain end of the NMOS tube MN13 is grounded through a capacitor C2.
In a third aspect, a power amplifier is provided, which includes the input stage clamping circuit as described in any of the above embodiments, two input terminals of a differential comparator in the input stage clamping circuit are used as two differential signal input terminals of the input stage clamping circuit to access differential signals VINP and VINN, and a first terminal and a second terminal of a switch circuit in the input stage clamping circuit are used as two output terminals of the input stage clamping circuit to output clamped differential signals VINP and VINN.
In one embodiment, the power amplifier further comprises a class D modulation circuit, two variable input resistors RIN1, two fixed input resistors RIN2, and an output driver stage circuit; one differential input end of the D-type modulation circuit is connected with a variable input resistor RIN1 and a fixed input resistor RIN2, the other differential input end is connected with another variable input resistor RIN1 and another fixed input resistor RIN2, an input stage clamping circuit is positioned between the variable input resistor RIN1 and the fixed input resistor RIN2, the two variable input resistors RIN1 respectively output differential signals VINP and VINN to the input stage clamping circuit, the input stage clamping circuit outputs two clamped differential signals VINP and VINN which are respectively transmitted to two input ends of the D-type modulation circuit through the two fixed input resistors RIN2, the D-type modulation circuit amplifies and modulates signals and transmits two pulse width modulation signals to the output driving stage circuit; the output driving circuit is used for responding to the two paths of pulse width modulation signals and outputting voltage to the loudspeaker.
In one embodiment, the class D modulation circuit comprises a first integrator AMP1, a second integrator AMP2, a first pulse width modulator and a second pulse width modulator;
the positive input end and the negative input end of the first integrator AMP1 are used as two input ends of the class D modulation circuit, wherein the negative input end is used for accessing a clamped signal VIPN, the positive input end is used for accessing a clamped signal VINN, the first output end of the first integrator AMP1 is connected with the positive input end of the second operational amplifier AMP2, the second output end of the first integrator AMP1 is connected with the negative input end of the second integrator AMP2, the first output end of the second integrator AMP2 is connected with the first input end of the first pulse width modulator, the second input end of the first pulse width modulator is used for accessing a sawtooth wave signal, the second output end of the second integrator AMP2 is connected with the first input end of the second pulse width modulator, the second input end of the second pulse width modulator is used for accessing a sawtooth wave signal, the output end of the first pulse width modulator is used as an output end of the class D modulation circuit and is connected with an input end of the output driver stage circuit, and the output end of the second pulse width modulator is used as the other output end of the D-type modulation circuit and is connected with the other input end of the output driving stage circuit.
In a fourth aspect, an audio power amplifying system is provided, which includes a speaker and the power amplifier as described in any of the above embodiments, wherein an output terminal of an output driver stage circuit in the power amplifier is connected to an input terminal of the speaker as an output terminal of the power amplifier.
According to the input stage clamping circuit and the clamping method thereof, the power amplifier and the audio power amplification system, the differential signals VINP and VINN and the two reference voltages VRFH and VRFL can be accessed through the differential comparator, the difference value of the two reference voltages VRFH and VRFL is used as a detection threshold value, when the absolute value of the difference value of the two differential signals is larger than the difference value of the reference voltages, the output voltage of the differential comparator can conduct the switch circuit, so that the differential signals VINP and VINN are clamped, the output voltage of the power amplifier is limited, and the load of the power amplifier such as a loudspeaker cannot be damaged due to the fact that the output voltage of the power amplifier is overlarge. For the power amplifier connected with the differential signal, the input stage clamping circuit in the embodiment can clamp the differential signal, and the requirement on circuit matching is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of an input stage clamp according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an input stage clamp according to another embodiment of the present invention;
FIG. 3 is a schematic diagram of a voltage-dividing reference circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a differential comparator according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a power amplifier according to an embodiment of the invention;
FIG. 6 is a waveform diagram of voltages at nodes according to an embodiment of the present invention;
FIG. 7 is a waveform diagram of nodes of a power amplifier according to an embodiment of the invention;
fig. 8a and 8b are schematic structural diagrams of a power amplifier according to an embodiment of the invention;
fig. 9 is a schematic structural diagram of a power amplifier according to another embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The following embodiments and their technical features may be combined with each other without conflict.
As described in the background, a single-ended input and single-ended output input stage clamp circuit is currently used to implement the clamping function. The inventor researches and discovers that two input stage clamping circuits are needed in a power amplifier for accessing differential signals, such as a class-D power amplifier, and the matching requirement of the two input stage clamping circuits is high in order to ensure that two clamping output signals keep consistent and change.
The embodiment of the invention provides an input stage clamping circuit and a clamping method thereof.
In one embodiment, as shown in fig. 1, the input stage clamp circuit comprises a differential comparator CMP1 and a switch circuit 120, the differential comparator CMP1 comprises four inputs, the switch circuit 120 comprises a first terminal and a second terminal; the clamping method comprises the following steps: the four input ends of the differential comparator CMP1 are respectively connected to the differential signals VINP and VINN of the input stage of the power amplifier and two different reference voltages, the difference value of the two reference voltages is used as a detection threshold, and the first end and the second end of the switch circuit 120 are also connected to the differential signals VINP and VINN; if the absolute value of the difference between the difference signals VINP and VINN is greater than the difference between the two reference voltages, controlling the differential comparator CMP1 to output a turn-on control signal to turn on the switch circuit 120, thereby turning on the first terminal and the second terminal of the switch circuit 120; the differential signals VINP and VINN are clamped by the switching circuit 120 that is turned on. The difference between the two reference voltages mentioned in this embodiment refers to the value of the larger reference voltage minus the smaller reference voltage.
In the clamping method of the input stage clamping circuit in this embodiment, one differential comparator is used to access the differential signals VINP and VINN and the two reference voltages VRFH and VRFL, and the difference between the two reference voltages VRFH and VRFL is used as a detection threshold, and when the difference between the two differential signals is greater than the difference between the two reference voltages, the switch circuit can be turned on, so as to clamp the differential signals VINP and VINN, thereby limiting the output voltage of the power amplifier, and protecting the load of the power amplifier, such as a speaker, from being damaged due to the excessive output voltage of the power amplifier. When the input-stage clamping circuit is applied to a power amplifier connected with a differential signal, the input-stage clamping circuit in the embodiment can clamp the differential signal, and the requirement on the matching performance of the circuit is lowered.
In one embodiment, if the absolute value of the difference between the differential signals VINP and VINN is greater than the difference between the two reference voltages, the differential comparator CMP1 may be controlled to output a high signal as the turn-on control signal, and the switch circuit 120 is turned on in response to the high signal.
Specifically, the differential comparator CMP1 further includes two output terminals, each connected to the control terminal of the switch circuit 120; if the absolute value of the difference between the difference signals VINP and VINN is greater than the difference between the two reference voltages, the two output terminals of the differential comparator CMP1 are controlled to output high-level voltages, and the switch circuit 120 can be turned on by any one of the high-level output voltages.
In one embodiment, the reference voltages VRFH and VRFL may be symmetrical with respect to the common mode voltage of the input stage, which may improve clamping accuracy. For example, the common mode voltage of the input stage is 0.5VDD, the reference voltages VRFH and VRFL are 0.5VDD +0.5 Δ and 0.5VDD-0.5 Δ, respectively, and the symbol Δ represents the difference between the reference voltage VRFH and VRFL.
Fig. 1 is a schematic structural diagram of an input stage clamp according to an embodiment of the present invention, referring to fig. 1, the input stage clamp includes a voltage division reference circuit 110, a differential comparator CMP1, and a switch circuit 120, the differential comparator CMP1 includes four input terminals, and the switch circuit 120 includes a first terminal, a second terminal, and a control terminal. The voltage-dividing reference circuit 110 is connected to two input terminals of the differential comparator CMP1, and an output terminal of the differential comparator CMP1 is connected to a control terminal of the switch circuit 120.
The voltage division reference circuit 110 is used to output two different reference voltages VRFH and VRFL. The four input terminals of the differential comparator CMP1 are respectively corresponding to the two reference voltages VRFH and VRFL and the differential signals VINP and VINN of the input stage of the power amplifier, and the differential comparator CMP1 is configured to output a turn-on control signal when the absolute value of the difference between the differential signals VINP and VINN is greater than the difference between the two reference voltages. The first terminal and the second terminal of the switch circuit 120 are respectively configured to receive the differential signals VINP and VINN, and the switch circuit 120 is configured to be turned on in response to the turn-on control signal output by the differential comparator CMP1, so as to turn on the first terminal and the second terminal of the switch circuit 120 to clamp the differential signals VINP and VINN. The difference between the two reference voltages mentioned in this embodiment refers to the value of the larger reference voltage minus the smaller reference voltage.
In this embodiment, one differential comparator CMP1 may be used to access the differential signals VINP and VINN and the two reference voltages VRFH and VRFL, and use the difference between the two reference voltages VRFH and VRFL as a detection threshold, when the absolute value of the difference between the two reference voltages VRFH and VRFL is greater than the difference between the two reference voltages, the differential comparator CMP1 outputs a signal to turn on the switch circuit 120, and the turned-on switch circuit 120 clamps the differential signals VINP and VINN, thereby limiting the output voltage of the power amplifier.
In one embodiment, referring to fig. 1, the differential comparator CMP1 further includes two output terminals, both of which are connected to the switch circuit 120, wherein one of the output terminals provides the output voltage VP, and the other of the output terminals provides the output voltage VN, the differential comparator CMP1 is configured to compare the difference between the differential signals VINP and VINN and the difference between the two reference voltages, set the output voltage VP to a high level when the difference between the differential signals VINP and VINN is determined to be greater than the difference between the reference voltages, and set the output voltage VN to a high level when the difference between the differential signals VINN and VINP is determined to be greater than the difference between the reference voltages; the output voltage VP or VN which is high level may be used as the turn-on control signal of the differential comparator CMP1, and the switch circuit 120 is turned on in response to the output voltage VP or VN which is high level.
Specifically, referring to fig. 2, the control terminal of the switch circuit 120 includes two control terminals, which are a first control terminal and a second control terminal, respectively, the switch circuit 120 includes a first NMOS transistor Mn1 and a second NMOS transistor Mn2, a gate terminal of the first NMOS transistor Mn1 is used as the first control terminal to connect to one of the output terminals of the differential comparator CMP1 to access the output voltage VP, a gate terminal of the second NMOS transistor Mn2 is used as the second control terminal to connect to the other output terminal of the differential comparator CMP1 to access the output voltage VN, drain terminals of the first NMOS transistor Mn1 and the second NMOS transistor Mn2 are used as the first terminal of the switch circuit 120 to access the differential signal VINP, and source terminals of the first NMOS transistor Mn1 and the second NMOS transistor Mn2 are used as the second terminal of the switch circuit 120 to access the differential signal VINN.
With respect to the voltage-dividing reference circuit 110, specifically, referring to fig. 2, the voltage-dividing reference circuit 110 includes a first voltage-dividing resistorThe power supply circuit comprises a power supply circuit and is characterized by comprising a resistor R1, a second voltage-dividing resistor R2 and a third voltage-dividing resistor R3, wherein the first voltage-dividing resistor R1, the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 are sequentially connected in series, the first voltage-dividing resistor R1 is connected to a power supply voltage VDD, and the third voltage-dividing resistor R3 is grounded; the voltage at the connection node of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 is used as one of the reference voltages VRFHThe voltage at the node where the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 are connected is used as another reference voltage VRFL. The first voltage dividing resistor R1 and the third voltage dividing resistor R3 may have equal resistances.
When the resistances of the divider resistors R1 and R3 are equal, a symmetrical reference voltage V can be providedRFHAnd VRFLThe clamping accuracy can be improved. Assuming the supply voltage is VDD, the reference voltage VRFHAnd VRFLThe relationship between the difference Δ of (a) and the voltage dividing resistances R1, R2, R3 is as follows:
Figure BDA0002605953660000111
it can be seen that when the resistances of the first voltage-dividing resistor R1 and the third voltage-dividing resistor R3 are equal, as shown in fig. 3, the reference voltage V isRFHAnd VRFLWith input-stage common-mode voltage 0.5VDD as central voltage, i.e. reference voltage VRFH0.5 delta higher than 0.5VDD, reference voltage VRFL0.5 delta lower than 0.5VDD, reference voltage VRFHAnd VRFLIs symmetrical, and can improve clamping precision.
In one embodiment, referring to fig. 4, the differential comparator CMP1 includes a first transpose circuit 210 and a second transpose circuit 220; the first switching circuit 210 includes two input terminals for respectively receiving the two different reference voltages VRFHAnd VRFLThe first converting circuit 210 is configured to convert the reference voltage difference into a reference current IRFHL; the second transpose circuit 220 is connected to the first transpose circuit 210, and the second transpose circuit 220 further includes two input terminals and two output terminals, the two output terminals are respectively connected to the differential signals VINP and VINN, and the two output terminals are respectively used for the differential signals VINP and VINNWhen the output voltage VP and the output voltage VN are output, the second transpose circuit 220 is configured to convert the differential signal VINP into a current signal IN, convert the differential signal VINP into a current signal IP, set the output voltage VP to a high level when the current signal IP is greater than the reference current IRFHL, and set the output voltage VN to a high level when the current signal IN is greater than the reference current IRFHL.
Specifically, referring to fig. 4, the differential comparator CMP1 further includes a bias current input circuit 230 for inputting a bias current IB to the first transpose circuit 210 and the second transpose circuit 220, so as to improve the response speed of the differential comparator CMP 1. Specifically, the bias current circuit 230 includes an NMOS transistor MN1 and an NMOS transistor MN 2; the first transpose circuit 210 comprises an NMOS transistor MN3, an NMOS transistor MN4, an NMOS transistor MN5, an NMOS transistor MN6, an NMOS transistor MN7, an NMOS transistor MN8, a PMOS transistor MP1, a PMOS transistor MP2, a PMOS transistor MP3, a PMOS transistor MP4, a PMOS transistor MP5 and a PMOS transistor MP 6; the second transpose circuit 220 comprises an NMOS transistor MN9, an NMOS transistor MN10, an NMOS transistor MN11, an NMOS transistor MN12, an NMOS transistor MN13, an NMOS transistor MN14, an NMOS transistor MN15, an NMOS transistor MN16, a PMOS transistor MP7, a PMOS transistor MP8, a PMOS transistor MP9, a PMOS transistor MP10, a PMOS transistor MP11, a PMOS transistor MP12, a PMOS transistor MP13 and a PMOS transistor MP 14;
in the bias current input circuit 230, the drain terminal of an NMOS transistor MN1 is used for accessing a bias current IB, the gate terminal and the drain terminal are connected together, and the source terminal is connected to the drain terminal of an NMOS transistor MN 2; the gate end and the drain end of the NMOS tube MN2 are connected together, and the source end is grounded; the gate of the NMOS transistor MN1 is connected to the gate of the NMOS transistor MN3 in the first transposing circuit 210 and the gate of the NMOS transistor MN11 in the second transposing circuit 210 to provide a bias current to the NMOS transistor MN3 and the NMOS transistor MN11, and the gate of the NMOS transistor MN2 in the first transposing circuit 210 is connected to the gate of the NMOS transistor MN4 in the NMOS transistor MN12 in the second transposing circuit 220 to provide a bias current to the NMOS transistor MN4 and the NMOS transistor MN12, so as to improve the response speed of the NMOS transistor MN3, the NMOS transistor MN4, the NMOS transistor MN11, and the NMOS transistor MN12, and improve the response speed of the differential comparator CMP 1.
In the first inverter circuit 210, the source terminal of the PMOS transistor MP1 is used for accessing a supply voltage, the gate terminal and the drain terminal are connected together, and the drain terminal is connected with the source terminal of the PMOS transistor MP 2;the gate end and the drain end of the PMOS tube MP2 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 7; the source end of the NMOS tube MN7 is connected with the drain end of the NMOS tube MN3, and the gate end is accessed with a reference voltage VRFL(ii) a The source end of the PMOS tube MP3 is used for accessing power supply voltage, the grid end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 4; the gate end and the drain end of the PMOS tube MP4 are connected together, the drain end is connected with the drain end of the NMOS tube MN8, the source end of the NMOS tube MN8 is connected with the drain end of the NMOS tube MN3, and the gate end is accessed to a reference voltage VRFH(ii) a The source end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN4, and the source end of the NMOS tube MN4 is grounded; the source end of the PMOS tube MP5 is used for accessing power supply voltage, the gate end of the PMOS tube MP3 is connected with the gate end of the PMOS tube MP3, and the drain end of the PMOS tube MP6 is connected with the source end of the PMOS tube MP 6; the gate end of the PMOS tube MP6 is connected with the gate end of the PMOS tube MP4, the drain end of the PMOS tube MP6 is connected with the drain end of the NMOS tube MN5, the gate end and the drain end of the NMOS tube MN5 are connected together, the source end of the NMOS tube MN5 is connected with the drain end of the NMOS tube MN6, and the source end of the NMOS tube MN6 is grounded.
In the second transpose circuit 220, a source terminal of the PMOS transistor MP9 is used for accessing a supply voltage, a gate terminal and a drain terminal are connected together, and the drain terminal is connected with a source terminal of the PMOS transistor MP 10; the gate end and the drain end of the PMOS tube MP10 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 15; the source end of the NMOS tube MN15 is connected with the drain end of the NMOS tube MN11, and the gate end is connected with a differential signal VINN; the source end of the PMOS tube MP11 is used for accessing power supply voltage, the grid end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 12; the gate end and the drain end of the PMOS tube MP12 are connected together, the drain end is connected with the drain end of the NMOS tube MN16, the source end of the NMOS tube MN16 is connected with the drain end of the NMOS tube MN11, and the gate end is accessed to a differential signal VINP; the source end of the NMOS tube MN11 is connected with the drain end of the NMOS tube MN12, and the source end of the NMOS tube MN12 is grounded; the source end of a PMOS tube MP7 is used for accessing power supply voltage, the drain end of the PMOS tube MP7 is connected with the source end of a PMOS tube MP8, the drain end of a PMOS tube MP8 is connected with the drain end of an NMOS tube MN9, the drain end of the PMOS tube MP8 also provides a switch control voltage VN, the gate end of an NMOS tube MN9 is connected with the gate end of an NMOS tube MN5, the source end of the NMOS tube MN9 is connected with the drain end of the NMOS tube MN10, the source end of the NMOS tube MN10 is grounded, the gate end of the NMOS tube MN10 is connected with the gate end of an NMOS tube MN6, and the drain end of the NMOS tube MN9 is grounded through a capacitor C1; the source end of the PMOS tube MP13 is used for accessing power supply voltage, the drain end of the PMOS tube MP13 is connected with the source end of the PMOS tube MP14, the drain end of the PMOS tube MP14 is connected with the drain end of the NMOS tube MN13, the drain end of the PMOS tube MP14 also provides a switch control voltage VP, the gate end of the NMOS tube MN13 is connected with the gate end of the NMOS tube MN9, the source end of the NMOS tube MN13 is connected with the drain end of the NMOS tube MN14, the source end of the NMOS tube MN14 is grounded, the gate end of the NMOS tube MN14 is connected with the gate end of the NMOS tube MN10, and the drain end of the NMOS tube MN13 is grounded through a capacitor C2.
In this specific circuit, the differential signals VINP and VINN, reference voltage VRFHAnd VRFLAnd bias current IB is the input signal and switch control voltages VP and VN are the output signals. The difference signals VINP and VINN are converted into current signals IN and IP by a difference comparator CMP1, and compared with a reference current IRFHL converted from the difference between the reference voltages VRFH and VRFL, when the current IP is greater than the current IRFHL, the difference between the difference signal VINP and VINN is greater than the difference between the reference voltages VRFH and VRFL, and the voltage VP is set to high level, otherwise, to low level, when the current IN is greater than the current IRFHL, the difference between the difference signal VINN and VINP is greater than the difference between the reference voltages VRFH and VRFL, and the voltage VN is set to high level, otherwise, to low level.
An embodiment of the present invention further provides a power amplifier, which includes the input stage clamping circuit as described in any of the above embodiments. Two input ends of a differential comparator in the input stage clamping circuit are used as two differential signal input ends of the input stage clamping circuit to be connected with differential signals VINP and VINN, and a first end and a second end of a switch circuit in the input stage clamping circuit are used as two output ends of the input stage clamping circuit to output clamped differential signals VINP and VINN.
In one embodiment, the power amplifier may be a class D power amplifier with adjustable gain, and referring to fig. 5, the power amplifier further includes a class D modulation circuit 510, two variable input resistors RIN1, two fixed input resistors RIN2, and an output driver stage circuit 520; one differential input end of the class-D modulation circuit 510 is connected to a variable input resistor RIN1 and a fixed input resistor RIN2 as a differential input end of the input stage of the power amplifier, the other differential input end is connected to another variable input resistor RIN1 and another fixed input resistor RIN2 as another differential input end of the input stage of the power amplifier, the input stage clamping circuit 100 is located between the variable input resistor RIN1 and the fixed input resistor RIN2, the two variable input resistors RIN1 respectively input differential signals VINP and VINN to the two differential signal input ends of the input stage clamping circuit 100, and the two output ends of the input stage clamping circuit 100 output two differential signals VINP and VINN clamped by the input stage clamping circuit 100 and are respectively transmitted to the two input ends of the class-D modulation circuit 510 through the two fixed input resistors RIN 2. As shown in fig. 8a and 8b, the specific connection structure of the input stage clamp circuit 100 and the class D modulation circuit 510 is shown. The class D modulation circuit 510 is configured to amplify and modulate a signal and output the signal to the output driver stage circuit 520. The output driver circuit 520 is configured to output a voltage to the speaker in response to the two pulse width modulated signals.
Specifically, the differential signals VINP and VINN may be voltage signals converted from differential current signals INP and INN, as shown in fig. 5, the front ends of two variable input resistors RIN1 are respectively connected to a capacitor C2, and the differential current signals INP and INN are respectively filtered by C2 and variable input resistor RIN1 to form differential signals VINP and VINN. Fig. 6 is a schematic diagram showing waveforms of the differential signals INP and INN, the voltages VP and VN, and the differential signals VINP and VINN according to an embodiment of the present invention.
In this embodiment, the class D power amplifier adds the input stage clamp circuit 100 between the variable input resistor RIN1 with adjustable gain at the input end and the fixed input resistor RIN2, and the input stage clamp circuit 100 detects the magnitudes of the input differential signals VINP and VINN, and once the difference between the input differential signals VINP and VINN exceeds the difference between the reference voltages VRFH and VRFL, the differential signals VINP and VINN are clamped, and the output voltage VO provided by the class D power amplifier to the speaker is also clamped, so as to limit the magnitude of the output voltage of the class D power amplifier, avoid the load from being damaged due to the excessive input signal, and protect the speaker from being damaged due to the excessive output voltage of the power amplifier.
As shown in fig. 7, which is a schematic diagram of waveforms of the differential signals INP and INN, the clamped differential signals VINP and VINN, and the output voltage VO of the power amplifier, when the difference between the differential signals VINP and VINN is greater than the reference voltage difference Δ, the differential signals VINP and VINN are clamped at +0.5 Δ and-0.5 Δ, respectively, and the output voltage VO of the power amplifier is clamped at Vclamp. The clamp voltage Vclamp satisfies the following relation:
Figure BDA0002605953660000161
where RF is the power amplifier feedback resistance, as shown in fig. 5, the input terminal of the class D power modulation circuit 510 and the output terminal of the output driver stage circuit 520 are connected through the feedback resistance RF.
As can be seen from the above formula, in the present embodiment, the clamp voltage Vclamp is positively correlated with the fixed resistor RIN2, and is not correlated with the gain-adjustable resistor RIN1, so that the same clamp voltage can be provided to be compatible with different gains of the power amplifier by disposing the input stage clamp circuit between the gain-adjustable resistor and the fixed resistor, and it is not necessary to design different input stage clamp circuits for power amplifiers with varying gains, and the circuit structure can be simplified.
Specifically, please refer to fig. 8a and 8b, which are schematic structural diagrams of a power amplifier according to an embodiment of the present invention. As shown in fig. 8b, the class D modulation circuit includes a first integrator AMP1, a second integrator AMP2, a first pulse width modulator comp1, and a second pulse width modulator comp 2;
the positive input end and the negative input end of the first integrator AMP1 are used as two input ends of the class D modulation circuit, wherein the negative input end is used for receiving the clamped signal VINP, the positive input end is used for receiving the clamped signal VINN, the first output end of the first integrator AMP1 is connected with the positive input end of the second integrator AMP2, the second output end of the first integrator AMP1 is connected with the negative input end of the second integrator AMP2, the first output end of the second integrator AMP2 is connected with the first input end of the first pulse width modulator comp1, the second input end of the first pulse width modulator comp1 is used for receiving the sawtooth wave signal, the second output end of the second integrator AMP2 is connected with the first input end of the second pulse width modulator comp2, the second input end of the second pulse width modulator comp2 is used for receiving the sawtooth wave signal, the output end of the first pulse width modulator comp1 is used as an output end of the class D modulation circuit and is connected with the first input end of the output driving circuit 520, an output terminal of the second pulse width modulator comp2 is connected as another output terminal of the class D modulation circuit 510 to another input terminal of the output driver stage circuit 520. Specifically, the first integrator AMP1 and the second integrator AMP2 are further connected to common-mode reference voltages VCM1 and VCM2, respectively.
In another embodiment, the power amplifier may be a D-class power amplifier with fixed gain, referring to fig. 9, which is different from the embodiment shown in fig. 5 in that there is no variable input resistor RIN1, and the differential current signals INP and INN are directly formed into differential signals VINP and VINN through capacitors C2, respectively, and then input to the differential input terminal of the input stage clamp circuit 100.
In summary, the embodiment of the present invention adds the input stage clamping circuit to the input stage of the power amplifier, so as to clamp the input signal, thereby limiting the output voltage of the power amplifier within a certain range, avoiding the load at the output terminal of the power amplifier from being damaged due to the excessive input signal, and realizing the clamping protection function. In addition, the input stage clamping circuit in the embodiment of the invention can clamp the differential signal, and has low requirement on circuit matching. In addition, for a gain-adjustable power amplifier, such as a class-D power amplifier, the input variable resistor of the power amplifier is split into a variable resistor part and a fixed resistor part, and then the input stage clamp circuit is arranged between the variable resistor and the fixed resistor, so that the output clamp voltage of the power amplifier is independent of the gain change, a different input stage clamp circuit does not need to be designed for the power amplifier with the gain change, and the circuit structure can be simplified.
The embodiment of the present invention further provides an audio power amplifying system, which includes a speaker and the power amplifier in any of the above embodiments, wherein an output terminal of an output driving stage circuit in the power amplifier is connected to an input terminal of the speaker as an output terminal of the power amplifier.
Referring to fig. 5 and 8b, the audio power amplifier system further includes an external LC filter, and the output terminal of the power amplifier is connected to the speaker through the external LC filter.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (14)

1. The clamping method of the input stage clamping circuit is characterized in that the input stage clamping circuit comprises a differential comparator and a switching circuit, wherein the differential comparator comprises four input ends, and the switching circuit comprises a first end and a second end; the clamping method comprises the following steps:
the four input ends of the differential comparator are respectively connected with differential signals VINP and VINN and two different reference voltages, the difference value of the two reference voltages is used as a detection threshold value, and the first end and the second end of the switch circuit are also connected with the differential signals VINP and VINN;
if the absolute value of the difference signals VINP and VINN is larger than the difference value of the two reference voltages, controlling the differential comparator to output a conduction control signal to conduct the switch circuit, so as to switch on the first end and the second end of the switch circuit;
and clamping the differential signals VINP and VINN by utilizing the conducted switch circuit.
2. The method of claim 1, wherein if an absolute value of a difference between the two reference voltages is greater than a difference between the two reference voltages, the differential comparator is controlled to output a high signal as the turn-on control signal.
3. The method of claim 2, wherein the differential comparator further comprises two output terminals, each connected to a control terminal of the switching circuit; and if the absolute value of the difference signals VINP and VINN is larger than the difference value of the two reference voltages, controlling the two output ends of the differential comparator to output high-level voltage.
4. The method of claim 1, wherein the two reference voltages are symmetric with respect to an input stage common mode voltage.
5. An input stage clamping circuit is characterized by comprising a voltage division reference circuit, a differential comparator and a switch circuit, wherein the differential comparator comprises four input ends, the switch circuit comprises a first end, a second end and a control end, the voltage division reference circuit is connected with two input ends of the differential comparator, and the output end of the differential comparator is connected with the control end of the switch circuit;
the voltage division reference circuit is used for outputting two different reference voltages;
the four input ends of the differential comparator are respectively used for correspondingly accessing the two reference voltages and the differential signals VINP and VINN, and the differential comparator is used for outputting a conduction control signal when the absolute value of the difference value of the differential signals VINP and VINN is greater than the difference value of the two reference voltages;
the first end and the second end of the switch circuit are respectively used for accessing differential signals VINP and VINN, and the switch circuit is used for responding to the conduction control signal output by the differential comparator to conduct, so that the first end and the second end of the switch circuit are switched on to clamp the differential signals VINP and VINN.
6. The input stage clamp circuit of claim 5, wherein the differential comparator further comprises two output terminals, each connected to a control terminal of the switching circuit to provide output voltages VP and VN;
the differential comparator is used for comparing the difference value of the differential signals VINP and VINN with the difference value of the two reference voltages, setting the output voltage VP to be at a high level when the difference value of the differential signals VINP and VINN is judged to be larger than the difference value of the reference voltages, and setting the output voltage VN to be at a high level when the difference value of the differential signals VINN and VINP is judged to be larger than the difference value of the reference voltages; the switch circuit is turned on in response to the output voltage VP or VN being high level.
7. The input stage clamp circuit of claim 6, wherein the switch circuit comprises two control terminals, namely a first control terminal and a second control terminal, the switch circuit comprises a first NMOS transistor and a second NMOS transistor, a gate terminal of the first NMOS transistor is used as the first control terminal to connect one of the output terminals of the differential comparator to access the output voltage VP, a gate terminal of the second NMOS transistor is used as the second control terminal to connect the other output terminal of the differential comparator to access the output voltage VN, drain terminals of the first NMOS transistor and the second NMOS transistor are both used as the first terminal of the switch circuit to access the differential signal VINP, and a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor are both used as the second terminal of the switch circuit to access the differential signal VINN.
8. The input stage clamping circuit according to claim 5, wherein the voltage dividing reference circuit comprises a first voltage dividing resistor, a second voltage dividing resistor and a third voltage dividing resistor, the first voltage dividing resistor, the second voltage dividing resistor and the third voltage dividing resistor are connected in series in sequence, wherein the first voltage dividing resistor is connected to a supply voltage, the third voltage dividing resistor is connected to ground, and the first voltage dividing resistor and the third voltage dividing resistor are equal in resistance; the voltage at the connection node of the first voltage-dividing resistor and the second voltage-dividing resistor is used as one reference voltage, and the voltage at the connection node of the second voltage-dividing resistor and the third voltage-dividing resistor is used as the other reference voltage.
9. The input stage clamp of claim 5, wherein the differential comparator comprises a first transpose circuit and a second transpose circuit;
the first transposition circuit comprises two input ends and an output end, the two input ends are respectively used for correspondingly accessing the two different reference voltages, and the transposition circuit is used for converting the reference voltage difference into the reference current;
the second transpose circuit is connected with the first transpose circuit, and further comprises two input ends and two output ends, wherein the two output ends are respectively used for accessing a differential signal VINP and a differential signal VINN, the two output ends are respectively used for outputting a voltage VP and a voltage VN, the second transpose circuit is used for converting the differential signal VINP and the differential signal VINN into current signals IP and IN, and is used for setting the output voltage VP to be at a high level when the current signal IP is greater than a reference current, and setting the output voltage VN to be at a high level when the current signal IN is greater than the reference current.
10. The input stage clamp of claim 9, wherein the differential comparator further comprises a bias current input circuit comprising NMOS transistor MN1 and NMOS transistor MN 2; the first switching circuit comprises an NMOS tube MN3, an NMOS tube MN4, an NMOS tube MN5, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8, a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5 and a PMOS tube MP 6; the second transpose circuit comprises an NMOS tube MN9, an NMOS tube MN10, an NMOS tube MN11, an NMOS tube MN12, an NMOS tube MN13, an NMOS tube MN14, an NMOS tube MN15, an NMOS tube MN16, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, a PMOS tube MP10, a PMOS tube MP11, a PMOS tube MP12, a PMOS tube MP13 and a PMOS tube MP 14;
in the bias current input circuit, the drain terminal of an NMOS (N-channel metal oxide semiconductor) tube MN1 is used for accessing a bias current IB, the gate terminal and the drain terminal are connected together, and the source terminal is connected with the drain terminal of an NMOS tube MN 2; the gate end and the drain end of the NMOS tube MN2 are connected together, and the source end is grounded; the gate end of the NMOS tube MN1 is connected with the gate end of the NMOS tube MN3 and the gate end of the NMOS tube MN11, and the gate end of the NMOS tube MN2 is connected with the gate end of the NMOS tube MN4 and the gate end of the NMOS tube MN 12;
in the first switching circuit, the source end of a PMOS tube MP1 is used for accessing a power supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of a PMOS tube MP 2; the gate end and the drain end of the PMOS tube MP2 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 7; the source end of the NMOS tube MN7 is connected with the drain end of the NMOS tube MN3, and the gate end is connected with one of the reference voltages; the source end of the PMOS tube MP3 is used for accessing power supply voltage, the grid end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 4; the gate end and the drain end of the PMOS tube MP4 are connected together, the drain end is connected with the drain end of the NMOS tube MN8, the source end of the NMOS tube MN8 is connected with the drain end of the NMOS tube MN3, and the gate end is connected with another reference voltage; the source end of the NMOS tube MN3 is connected with the drain end of the NMOS tube MN4, and the source end of the NMOS tube MN4 is grounded; the source end of the PMOS tube MP5 is used for accessing power supply voltage, the gate end of the PMOS tube MP3 is connected with the gate end of the PMOS tube MP3, and the drain end of the PMOS tube MP6 is connected with the source end of the PMOS tube MP 6; the gate end of the PMOS tube MP6 is connected with the gate end of the PMOS tube MP4, the drain end of the PMOS tube MP6 is connected with the drain end of the NMOS tube MN5, the gate end and the drain end of the NMOS tube MN5 are connected together, the source end of the NMOS tube MN5 is connected with the drain end of the NMOS tube MN6, and the source end of the NMOS tube MN6 is grounded;
in the second transpose circuit, the source end of a PMOS transistor MP9 is used for accessing a supply voltage, the gate end and the drain end are connected together, and the drain end is connected with the source end of a PMOS transistor MP 10; the gate end and the drain end of the PMOS tube MP10 are connected together, and the drain end is connected with the drain end of the NMOS tube MN 15; the source end of the NMOS tube MN15 is connected with the drain end of the NMOS tube MN11, and the gate end is accessed with a differential input signal VINN; the source end of the PMOS tube MP11 is used for accessing power supply voltage, the grid end and the drain end are connected together, and the drain end is connected with the source end of the PMOS tube MP 12; the gate end and the drain end of the PMOS tube MP12 are connected together, the drain end is connected with the drain end of the NMOS tube MN16, the source end of the NMOS tube MN16 is connected with the drain end of the NMOS tube MN11, and the gate end is accessed to a differential input signal VINP; the source end of the NMOS tube MN11 is connected with the drain end of the NMOS tube MN12, and the source end of the NMOS tube MN12 is grounded; the source end of a PMOS tube MP7 is used for accessing power supply voltage, the drain end of the PMOS tube MP7 is connected with the source end of a PMOS tube MP8, the drain end of a PMOS tube MP8 is connected with the drain end of an NMOS tube MN9, the drain end of the PMOS tube MP8 also provides a switch control voltage VN, the gate end of an NMOS tube MN9 is connected with the gate end of an NMOS tube MN5, the source end of the NMOS tube MN9 is connected with the drain end of the NMOS tube MN10, the source end of the NMOS tube MN10 is grounded, the gate end of the NMOS tube MN10 is connected with the gate end of an NMOS tube MN6, and the drain end of the NMOS tube MN9 is grounded through a capacitor C1; the source end of the PMOS tube MP13 is used for accessing power supply voltage, the drain end of the PMOS tube MP13 is connected with the source end of the PMOS tube MP14, the drain end of the PMOS tube MP14 is connected with the drain end of the NMOS tube MN13, the drain end of the PMOS tube MP14 also provides a switch control voltage VP, the gate end of the NMOS tube MN13 is connected with the gate end of the NMOS tube MN9, the source end of the NMOS tube MN13 is connected with the drain end of the NMOS tube MN14, the source end of the NMOS tube MN14 is grounded, the gate end of the NMOS tube MN14 is connected with the gate end of the NMOS tube MN10, and the drain end of the NMOS tube MN13 is grounded through a capacitor C2.
11. A power amplifier comprising an input stage clamp circuit according to any of claims 5-10, wherein two inputs of a differential comparator of the input stage clamp circuit are used as two differential signal inputs of the input stage clamp circuit to receive differential signals VINP and VINN, and wherein first and second ends of a switch circuit of the input stage clamp circuit are used as two outputs of the input stage clamp circuit to output clamped differential signals VINP and VINN.
12. The power amplifier of claim 11, further comprising a class D modulation circuit, two variable input resistors RIN1, two fixed input resistors RIN2, and an output driver stage circuit; one differential input end of the D-type modulation circuit is connected with a variable input resistor RIN1 and a fixed input resistor RIN2, the other differential input end is connected with another variable input resistor RIN1 and another fixed input resistor RIN2, an input stage clamping circuit is positioned between the variable input resistor RIN1 and the fixed input resistor RIN2, the two variable input resistors RIN1 respectively output differential signals VINP and VINN to the input stage clamping circuit, the input stage clamping circuit outputs two clamped differential signals VINP and VINN which are respectively transmitted to two input ends of the D-type modulation circuit through the two fixed input resistors RIN2, the D-type modulation circuit amplifies and modulates signals and transmits two pulse width modulation signals to the output driving stage circuit; the output driving circuit is used for responding to the two paths of pulse width modulation signals and outputting voltage to the loudspeaker.
13. The power amplifier of claim 12, wherein the class D modulation circuit comprises a first integrator AMP1, a second integrator AMP2, a first pulse width modulator, and a second pulse width modulator;
the positive input end and the negative input end of the first integrator AMP1 are used as two input ends of the class D modulation circuit, wherein the negative input end is used for accessing a clamped signal VIPN, the positive input end is used for accessing a clamped signal VINN, the first output end of the first integrator AMP1 is connected with the positive input end of the second operational amplifier AMP2, the second output end of the first integrator AMP1 is connected with the negative input end of the second integrator AMP2, the first output end of the second integrator AMP2 is connected with the first input end of the first pulse width modulator, the second input end of the first pulse width modulator is used for accessing a sawtooth wave signal, the second output end of the second integrator AMP2 is connected with the first input end of the second pulse width modulator, the second input end of the second pulse width modulator is used for accessing a sawtooth wave signal, the output end of the first pulse width modulator is used as an output end of the class D modulation circuit and is connected with an input end of the output driver stage circuit, and the output end of the second pulse width modulator is used as the other output end of the D-type modulation circuit and is connected with the other input end of the output driving stage circuit.
14. Audio power amplification system comprising a loudspeaker and a power amplifier according to any of claims 11-13, an output of the power amplifier being connected to an input of the loudspeaker.
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CN112737562A (en) * 2020-12-24 2021-04-30 西安翔腾微电子科技有限公司 High-speed voltage mode transmitter with impedance correction circuit
CN114281141A (en) * 2021-12-24 2022-04-05 思瑞浦微电子科技(上海)有限责任公司 Differential pair tube protection circuit
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CN112737562A (en) * 2020-12-24 2021-04-30 西安翔腾微电子科技有限公司 High-speed voltage mode transmitter with impedance correction circuit
US11457307B2 (en) 2021-02-23 2022-09-27 Macronix Iniernational Co., Ltd. Headphone driver and driving method thereof
TWI789712B (en) * 2021-02-23 2023-01-11 旺宏電子股份有限公司 Headphone driver and driving method thereof
CN114281141A (en) * 2021-12-24 2022-04-05 思瑞浦微电子科技(上海)有限责任公司 Differential pair tube protection circuit
CN114281141B (en) * 2021-12-24 2023-03-14 思瑞浦微电子科技(上海)有限责任公司 Differential pair tube protection circuit

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