CN212435678U - Active-passive noise shaping successive approximation ADC - Google Patents

Active-passive noise shaping successive approximation ADC Download PDF

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CN212435678U
CN212435678U CN202021448729.2U CN202021448729U CN212435678U CN 212435678 U CN212435678 U CN 212435678U CN 202021448729 U CN202021448729 U CN 202021448729U CN 212435678 U CN212435678 U CN 212435678U
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pmos transistor
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passive integrator
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徐卫林
翁浩然
周茜
韦雪明
段吉海
韦保林
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Guilin University of Electronic Technology
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Abstract

The utility model discloses an active-passive noise shaping successive approximation ADC, including DAC capacitor array DAC1 and DAC2, active-passive noise shaping module (including passive integrator PINT1 and positive feedback active-passive integrator APINT2), six input comparator COMP, successive approximation logic module SAR, clock generation module CKG, reference voltage generation module BGVG. The utility model discloses use the common source structure of simplest MOS transistor in active-passive noise shaping module, make low gain active amplifier and positive feedback combine together, only consume dozens of microwatts alright obtain good noise shaping characteristic, can promote the significant digit and exceed 5 bits on traditional successive approximation ADC basis. The utility model discloses a can be used to the analog-to-digital conversion scene of low-power consumption, high accuracy, fields such as biomedical signal acquisition, high accuracy instrument design have good application prospect.

Description

Active-passive noise shaping successive approximation ADC
Technical Field
The utility model relates to an integrated circuit design technical field, concretely relates to active-passive noise plastic successive approximation ADC.
Background
ADCs (analog to digital converters) serve as the only bridge between the analog and digital worlds and play an important role in the fields of communications, aviation, medical care, and the like. In view of the characteristics of biomedical signals and the requirement of portability, ADCs are required to have the characteristics of high precision and low power consumption. The successive approximation ADC is the optimal choice in the fields of low power consumption and medium precision by using an efficient algorithm and an ultra-low power consumption dynamic circuit. Oversampling ADCs enable ultra-high accuracy at moderate power consumption and speed using oversampling and noise shaping techniques. The noise-shaped successive approximation ADC combines the advantages of the two, namely the noise shaping is used for realizing high precision while the low power consumption of the successive approximation ADC is kept.
The traditional noise shaping module can be divided into an active type and a passive type, the passive noise shaping power consumption is low, but the defect is that the noise shaping capacity is limited, 1-2 effective digits can be improved only on the basis of a 10-digit successive approximation ADC, and the performance improving effect is poor. Active noise shaping can provide a more ideal noise shaping function, can improve the effective digit of more than 5 bits on the basis of a 10-bit successive approximation ADC, but the high gain of an active part causes higher power consumption, and the power consumption is often sub-milliwatt due to higher gain requirements, so that the active noise shaping is not suitable for portable application.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve is that the problem that current active noise shaping circuit consumption is high and current passive noise shaping circuit shaping ability is weak combines together active noise shaping and passive noise shaping technique, utilizes low-gain and positive feedback, provides an active-passive noise shaping successive approximation ADC.
In order to solve the above problems, the utility model discloses a realize through following technical scheme:
active-passive noiseThe shaping successive approximation ADC comprises a DAC (digital-to-analog converter) capacitor array DAC1, a DAC2, an active-passive noise shaping module, a six-input comparator COMP, a successive approximation logic module SAR, a clock generation module CKG and a reference voltage generation module BGVG; the active-passive noise shaping module comprises a passive integrator PINT1 and a positive feedback active-passive integrator APINT 2; the signal input in-phase end VINP is connected with a signal input end SGI1 of the DAC capacitor array DAC1, and the signal input out-of-phase end VINN is connected with a signal input end SGI2 of the DAC capacitor array DAC 2; an output end DO1 of the DAC1 is connected with a non-inverting input end RESP of the passive integrator PINT1 and a first non-inverting input end P1 of a six-input comparator COMP; an output end DO2 of the DAC2 is connected with an inverting input end RESN of the passive integrator PINT1 and a first inverting input end N1 of a six-input comparator COMP; the inverting output terminal PT1ON of the passive integrator PINT1 is connected with the inverting input terminal G2IN of the positive feedback active-passive integrator APINT2 and the second inverting input terminal N2 of the six-input comparator COMP; the same-direction output end PT1OP of the passive integrator PINT1 is connected with the non-phase input end G2IP of the positive feedback active-passive integrator APINT2 and the second non-phase input end P2 of the six-input comparator COMP; the non-inverting output terminal AT2OP of the positive feedback active-passive integrator APINT2 is connected to the third non-inverting input terminal P3 of the six-input comparator COMP; the inverting output terminal AT2ON of the positive feedback active-passive integrator APINT2 is connected to the third inverting input terminal N3 of the six-input comparator COMP; the output end of the six-input comparator COMP is connected with the input end of the successive approximation logic module SAR, the in-phase output end SARP of the successive approximation logic module SAR is connected back to the feedback input end FBI1 of the DAC (digital-to-analog converter) capacitor array DAC1, and the reverse-phase output end SARN of the successive approximation logic module SAR is connected back to the feedback input end FBI2 of the DAC capacitor array DAC 2; a digital output bus DOUT is led out from the successive approximation logic module SAR; the global clock signal CLK is connected to an input terminal CK of the clock generation module CKG; an output end KFS of the clock generation module CKG is commonly connected to a DAC1 and a sampling clock input end FS of the DAC 2; the output terminal KRES of the clock generation module CKG is connected to the residual error sampling clock input terminal phi of the passive integrator PINT1RES(ii) a The output terminals K1 of the clock generation module CKG are respectively connected to the first-order integration clock input terminals of the passive integrator PINT1Φ1And a first-order integration clock input phi of a positive feedback active-passive integrator APINT21(ii) a The output terminal K2 of the clock generation module CKG is connected to the second-order integration clock input terminal phi of the positive feedback active-passive integrator APINT22(ii) a An output end KCMP of the clock generation module CKG is connected to a clock input end COMPCLK of the six-input comparator COMP; an output end BGVCM of the reference voltage generation module BGVG is connected to a common-mode voltage input end VCM of the passive integrator PINT 1; an output terminal BGVB of the reference voltage generation block BGVG is connected to a bias voltage input terminal VB of the positive feedback active-passive integrator APINT 2.
In the scheme, the passive integrator PINT1 is composed of switches I1-I8 and capacitors C1-C4; one end of the switch I1 forms a non-inverting input end RESP of the passive integrator PINT1, and the other end of the switch I1 is connected with the upper plate of the capacitor C1 and one end of the switch I3; one end of the switch I2 forms an inverting input end RESP of the passive integrator PINT1, and the other end of the switch I2 is connected with the upper plate of the capacitor C2 and one end of the switch I4; one ends of the switches I5 and I7 are connected with the lower plate of the capacitor C1; one ends of the switches I6 and I8 are connected with the lower plate of the capacitor C2; the other end of the switch I7 is connected with the upper plate of the capacitor C3 to form an inverted output end PT1ON of the passive integrator PINT 1; the other end of the switch I8 is connected with the upper pole plate of the capacitor C4 to form a non-inverting output end PT1OP of the passive integrator PINT 1; the other ends of the switches I3, I4, I5 and I6 form a common-mode voltage input VCM of the passive integrator PINT 1; the control terminals of the switches I1, I2, I5 and I6 form the residual sampling clock Φ of the passive integrator PINT1RES(ii) a The control terminals of the switches I3, I4, I7 and I8 form the first-order integration clock input Φ of the passive integrator PINT11(ii) a The lower plates of the capacitors C3 and C4 are grounded GND.
In the scheme, the positive feedback active-passive integrator APINT2 consists of resistors R1-R2, PMOS transistors MP 1-MP 6, switches I9-I12, capacitors C5-C8 and a common mode feedback module CMFB; the input end of the common mode feedback module CMFB forms a bias voltage input end VB of the positive feedback active-passive integrator APINT 2; the gate of the PMOS transistor MP1 forms the non-inverting input terminal G2IP of the positive feedback active-passive integrator APINT2, the source of the PMOS transistor MP1 and the source of the PMOS transistor MP2 and the PMOS transistorThe drain electrode of the MP3 is connected, and the drain electrode of the PMOS transistor MP1 is connected with one end of the resistor R1 and the drain electrode of the PMOS transistor MP 5; the gate of the PMOS transistor MP2 forms the inverting input terminal G2IN of the positive feedback active-passive integrator APINT2, the source of the PMOS transistor MP2 is connected to the source of the PMOS transistor MP1 and the drain of the PMOS transistor MP3, and the drain of the PMOS transistor MP2 is connected to one end of the resistor R2 and the drain of the PMOS transistor MP 4; the source of the PMOS transistor MP3 is connected to the power supply VDD, the gate of the PMOS transistor MP3 is connected to the output terminal VCMFB of the common mode feedback module CMFB, and the drain of the PMOS transistor MP3 is connected to the sources of the PMOS transistors MP1 and MP 2; the grid of the PMOS transistor MP4, the upper plate of the capacitor C8 and one end of the switch I12 are connected to form the inverting output end AT2ON of the positive feedback active-passive integrator APINT2, the source of the PMOS transistor MP4 is linked with the source of the PMOS transistor MP5 and the drain of the PMOS transistor MP6, and the drain of the PMOS transistor MP4 is connected with one end of the resistor R2, the drain of the PMOS transistor MP2 and one end of the switch I9; the grid of the PMOS transistor MP5, the upper plate of the capacitor C7 and one end of the switch I11 are connected to form a non-inverting output end AT2OP of the positive feedback active-passive integrator APINT2, the source of the PMOS transistor MP5 is linked with the source of the PMOS transistor MP4 and the drain of the PMOS transistor MP6, and the drain of the PMOS transistor MP5 is connected with one end of the resistor R1, the drain of the PMOS transistor MP1 and one end of the switch I10; the source of the PMOS transistor MP6 is connected to the power supply VDD, the gate of the PMOS transistor MP6 is connected to the output terminal VCMFB of the common mode feedback module CMFB, and the drain of the PMOS transistor MP6 is connected to the sources of the PMOS transistors MP4 and MP 5; the control terminals of the switches I9 and I10 form the first-order integration clock input Φ of the positive-feedback active-passive integrator APINT21(ii) a The control terminals of the switches I11 and I12 form the second-order integration clock input phi of the positive-feedback active-passive integrator APINT22(ii) a The other end of the switch I9 is connected with the upper plate of the capacitor C5 and the other end of the switch I11; the other end of the switch I10 is connected with the upper plate of the capacitor C6 and the other end of the switch I12; the other ends of the resistors R1 and R2 and the lower plate of the capacitors C5-C8 are grounded GND.
Compared with the prior art, the utility model discloses use the common source structure of simplest MOS transistor in active-passive noise shaping module, make low-gain active amplifier and positive feedback combine together, only consume dozens of microwatts alright obtain good noise shaping characteristic, can promote the effective digit and exceed 5 bits on traditional successive approximation ADC basis. The utility model discloses a can be used to the analog-to-digital conversion scene of low-power consumption, high accuracy, fields such as biomedical signal acquisition, high accuracy instrument design have good application prospect.
Drawings
FIG. 1 is a diagram of the overall structure of an active-passive noise shaping successive approximation ADC;
FIG. 2 is an exemplary diagram of an active-passive noise shaping circuit;
FIG. 3 is a diagram of an active-passive noise shaping successive approximation ADC duty cycle;
FIG. 4 is a signal flow diagram of a noise-shaped successive approximation ADC;
FIG. 5 is a signal flow diagram of an active-passive noise shaping successive approximation ADC;
FIG. 6 is an amplitude-frequency characteristic curve of the noise transfer function of the active-passive noise shaping successive approximation ADC;
FIG. 7 is a graph of the output spectrum of a successive approximation ADC with the active-passive noise shaping module removed;
fig. 8 is a graph of the output spectrum of an active-passive noise-shaping successive approximation ADC.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the following specific examples.
An active-passive noise shaping successive approximation ADC is composed of a DAC1 and a DAC2, an active-passive noise shaping module (including a passive integrator PINT1 and a positive feedback active-passive integrator APINT2), a six-input comparator COMP, a successive approximation logic module SAR, a clock generation module CKG and a reference voltage generation module BGVG, as shown in FIG. 1.
The signal input in-phase end VINP is connected with the DAC1 signal input end SGI1, and the signal input out-phase end VINN is connected with the DAC2 signal input end SGI 2. An output end DO1 of the DAC1 is connected with a non-inverting input end RESP of the passive integrator PINT1, and is also connected with a first non-inverting input end P1 of a six-input comparator COMP; of DAC2The output terminal DO2 is connected to the inverting input terminal RESN of PINT1 and to the first inverting input terminal N1 of the six-input comparator COMP. The inverting output end PT1ON of the passive integrator PINT1 is connected with the inverting input end G2IN of the positive feedback active-passive integrator APINT2, and is also connected with a COMP second inverting input end N2; the PINT1 non-inverting output terminal PT1OP is connected to the non-inverting input terminal G2IP of APINT2, and to the second non-inverting input terminal P2 of COMP. The non-inverting output terminal AT2OP of APINT2 is connected to the third non-inverting input terminal P3 of COMP; the inverting output terminal AT2ON of APINT2 is connected to the third inverting input terminal N3 of COMP. The COMP output end is connected with a successive approximation logic module SAR, the SAR in-phase output end SARP is connected back to the feedback input end FBI1 of the DAC1, and the SAR reverse-phase output end SARN is connected back to the feedback input end FBI2 of the DAC2, so that a complete differential successive approximation structure is formed. The digital output bus DOUT is led out from the successive approximation logic module SAR. The global clock signal CLK is connected to the clock generation module CKG input end CK, the clock generation module CKG output KFS is connected to the DAC1 and the sampling clock input end FS of the DAC 2in common; the output KRES is connected to the residual sampling clock input phi of the passive integrator PINT1RES(ii) a The outputs K1 are respectively connected to the first-order integration clock input terminals phi of the PINT11And first order integration clock input Φ of APINT21(ii) a The output K2 is connected to the second-order integration clock input phi of APINT22(ii) a The output KCMP is connected to a clock input terminal COMPCLK of a six-input comparator COMP. An output end BGVCM of the reference voltage generation module BGVG is connected to a common-mode voltage input end VCM of the passive integrator PINT 1; the output terminal BGVB is connected to the APINT2 bias voltage input terminal VB.
The active-passive noise shaping module of the present invention, as shown in fig. 2, includes a passive integrator PINT1 and a positive feedback active-passive integrator APINT 2.
The passive integrator PINT1 of the active-passive noise shaping module consists of eight switches I1-I8 and four capacitors C1-C4. The control ends of the switches I1 and I2 are connected to a residual error sampling clock phiRESOne end of the I1 is connected with a residual error positive phase input end RESP, the other end of the I1 is connected with an upper polar plate of the capacitor C1, and one end of the switch I3; one end of the I2 is connected with the residual error inverting input end RESN, the other end is connected with the upper plate of the capacitor C2, and one end of the switch I4. I3, I4 the otherEnd connected to common mode level VCM, control end connected to first-order integral clock phi1. The control terminals of the switches I5 and I6 are connected to phiRESOne end of the common-mode voltage VCM is connected with the common-mode voltage VCM; the other end of the I5 is connected with a lower polar plate of the C1 and one end of a switch I7; the other end of the I6 is connected with the lower pole plate of the C2 and one end of the switch I8. The control ends of I7 and I8 are connected with a second-order integral clock phi2The other end of the I7 is connected with the upper plate of a capacitor C3 and the negative integrator PINT1 inverting output port PT1 ON; the other end of the I8 is connected with the upper plate of a capacitor C4 and a passive integrator PINT1 non-inverting output port PT1OP in common. The lower plates of the C3 and the C4 are connected to the ground GND. The inverting output port PT1ON of the passive integrator PINT1 is connected to the inverting input port G2IN of the positive feedback active-passive integrator APINT 2; the non-inverting output port PT1OP of the passive integrator PINT1 is connected to the non-inverting input port G2IP of the positive feedback active-passive integrator APINT 2.
The positive feedback active-passive integrator APINT2 of the active-passive noise shaping module consists of two resistors R1-R2, six PMOS transistors MP 1-MP 6, four switches I9-I12, four capacitors C5-C8 and a common mode feedback module CMFB. The bias voltage VB is input to the common mode feedback module CMFB, which generates a common mode feedback output VCMFB. The source of the active gain current source PMOS transistor MP3 is connected to the power supply VDD, the gate is connected to the output end VCMFB of the common mode feedback module, and the drain is connected to the sources of MP1 and MP 2. The grid electrode of the active gain non-inverting input PMOS transistor MP1 is connected to the non-inverting input end G2IP of APINT2, the source electrode is connected with the source electrode of MP2 and the drain electrode of the active gain current source PMOS transistor MP3, and the drain electrode is connected with one end of the load resistor R1 and the drain electrode of the positive feedback input tube MP 5; the grid electrode of the active gain inverting input PMOS transistor MP2 is connected to the inverting input end G2IN of the APINT2, the source electrode is connected with the source electrode of the MP1 and the drain electrode of the active gain current source PMOS transistor MP3, and the drain electrode is connected with one end of the load resistor R2 and the drain electrode of the positive feedback inverting input tube MP 4. The source of the positive feedback current source PMOS transistor MP6 is connected to the power supply VDD, the gate is connected to the output end VCMFB of the common mode feedback module, and the drain is connected to the sources of MP4 and MP 5. The gate of positive feedback inverting input PMOS transistor MP4 is connected to the upper plate of second stage integrating capacitor C8, the source is connected with the source of MP5, positiveThe drains of the feedback current source PMOS transistor MP6 are connected together, and the drain is connected with one end of a resistor R2, the drain of MP2 and one end of a switch I9; the grid electrode of the positive feedback non-inverting input PMOS transistor MP5 is connected to the upper pole plate of the second-stage integrating capacitor C7, the source electrode is connected with the source electrode of MP4 and the drain electrode of the positive feedback current source PMOS transistor MP6 in a common mode, and the drain electrode is connected with one end of a resistor R1, the drain electrode of MP1 and one end of a switch I10 in a common mode. One end of the load resistor R1 is connected with the drains of the MP1 and the MP5, and the other end is grounded GND; the load resistor R2 has one end connected to the drains of MP2 and MP4, and one end connected to GND. The control ends of the switches I9 and I10 are connected with phi together1The other end of the I9 is connected with the upper plate of the second-stage sampling capacitor C5 and one end of the I11, and the other end of the I10 is connected with the upper plate of the second-stage sampling capacitor C6 and one end of the I12. The lower plates of the C5 and the C6 are connected to the ground GND in common. The control ends of the switches I11 and I12 are connected with phi together2The other end of the I11 is connected with the upper polar plate of the second-stage integrating capacitor C7 and the grid of a positive feedback non-inverting input PMOS transistor MP5 together to serve as a non-inverting output end AT2OP of the APINT 2; the other end of the I12 is connected with the upper plate of the second-stage integrating capacitor C8 and the grid of the positive feedback inverting input PMOS transistor MP4 in common to serve as the inverting output AT2ON of the APINT 2. The lower polar plates of C7 and C8 are grounded.
The utility model discloses an active-passive noise plastic successive approximation ADC adopts the fully differential structure, can eliminate the even harmonic basically, and compare with single-ended structure, total signal to noise ratio can promote 3 dB. Differential input signals are respectively input into the input ends VINP and VINN, sampled by the DAC capacitor array, then respectively input into the in-phase end and the out-of-phase end of the comparator for comparison, the comparison result is input into the successive approximation logic module SAR, and the generated control signals are respectively fed back to the DAC1 and the DAC2 to realize the successive approximation algorithm.
The utility model discloses carry out noise shaping on ten successive approximation ADC's examples, consequently need eleven cycle to carry out successive approximation conversion. After the last bit of result is fed back to the DAC, the remainder in the DAC is the residual voltage of the conversion. And inputting the differential residual voltage into a first-stage passive integrator PINT1 to generate first-order noise shaping, and inputting the result of the first-order noise shaping into a second-stage positive feedback active-passive integrator APINT2 to generate second-order noise shaping. The results of the first order noise shaping and the second order noise shaping are then provided to a comparator to correct the next conversion.
The operation timing of the active-passive noise-shaping successive approximation ADC is shown in fig. 3. The ADC needs fifteen clock cycles to complete one conversion, and because the residual difference is differentially sampled to the capacitors C1 and C2 at the end of one conversion, the noise shaping module can work simultaneously when the successive approximation ADC samples signals, so that the design reduces the period required by the conversion. The first three periods are used for sampling input signals, the active-passive noise shaping module works simultaneously, and first-order and second-order residual difference integral voltages generated by the previous conversion are input into the comparator to correct the conversion result. The next eleven cycles complete the function of the successive approximation ADC. Compared with a common successive approximation ADC, the active-passive noise shaping module needs to sample and convert the residual difference voltage, and successive approximation logic is required to output results once more, so eleven cycles are required. And the active-passive noise shaping module in the last period samples the converted residual difference voltage.
The working principle of the noise-shaped successive approximation ADC is shown in fig. 4. Since the input signal is sampled, the input signal is represented as vin (z) in the z domain, the voltage generated by outputting the digital code and feeding back to the DAC is represented as dout (z), and the successive approximation conversion residual res (z) has:
RES(z)＝Vin(z)-Dout(z)
assuming the transfer function of the loop filter is h (z), the output yo (z) of the filter is:
YO(z)＝H(z)·RES(z)
let the quantization noise of SAR ADC be q (z), the comparator noise be ncomp (z), and then dout (z) can be obtained as:
Dout(z)＝Q(z)+NCOMP(z)+Vin(z)+YO(z)
when yo (z), res (z) are substituted into the above formula, the output of the whole system is:
Figure BDA0002594493440000061
the output of the system comprises signal vin (z) and noise (including comparator noise ncomp (z) and quantization noise q (z)). Let the coefficient before signal be the transfer function STF of signal and the coefficient before noise be the transfer function NTF of noise, then:
STF＝1
NTF＝1/[1+H(z)]
it can be seen that the signal is fully retained and when h (z) is sufficiently gained within the signal bandwidth, the noise within the signal bandwidth is greatly reduced. The NTF is similar to a high-pass filter for noise at the moment, the noise can be pushed from low frequency to high frequency, the noise in the signal bandwidth is reduced, and the effective digit is improved.
The signal flow diagram abstracted by the active-passive noise shaping module is shown in fig. 5. The NTF of the noise shaping module is calculated as:
Figure BDA0002594493440000062
then an active-passive noise shaping successive approximation ADC noise transfer function amplitude-frequency characteristic curve can be obtained as shown in fig. 6. It can be seen from the figure that within 5KHz of the signal bandwidth of the example, the noise is attenuated by more than-30 dB, and the dynamic performance of the output result of the ADC is greatly improved.
The utility model discloses a positive feedback active-passive integrator APINT2 among the active-passive noise shaping module uses the simplest MOS transistor common source level structure, utilizes the combination of lower gain (being less than 20dB) and positive feedback, only consumes 50 micro watts in the example and has just obtained good noise shaping characteristic. Conventional active noise shaping modules need to provide high gain (often greater than 80dB) to achieve good noise shaping characteristics, and thus the active part consumes a lot of power. Conventional active noise shaping modules tend to consume on the order of milliwatts. To sum up, the utility model discloses an active-passive noise shaping module compares can greatly reduced consumption compared with traditional active noise shaping module.
Fig. 7 is a diagram of the output spectrum of the successive approximation ADC without the active-passive noise shaping module, and fig. 8 is a diagram of the output spectrum of the successive approximation ADC with the active-passive noise shaping module removed. After comparison, it can be found that when the input signals are the same, active-passive noise shaping can improve the effective digit of nearly 7 bits on the basis of the traditional successive approximation ADC. The utility model discloses use the simple active amplifier and the positive feedback of lower gain, only consume 50 microwatts of power consumptions in the example, just can promote the significant digit and exceed 5.
It should be noted that the present invention is directed to the field of integrated circuit design, and not to system design based on existing commercial chip, so that the integrated circuit sub-module has no model, and the values of the resistor and the capacitor and the width-to-length ratio of the MOS transistor in the example of fig. 2 are labeled on the figure. Furthermore, although the above described embodiments of the present invention are illustrative, this is not a limitation of the present invention, and thus the present invention is not limited to the above described embodiments. Other embodiments, which can be made by those skilled in the art in light of the teachings of the present invention, are considered to be within the scope of the present invention without departing from the principles thereof.

Claims (3)

1. An active-passive noise shaping successive approximation ADC is characterized by comprising a DAC (digital-to-analog converter) capacitor array DAC1, a DAC2, an active-passive noise shaping module, a six-input comparator COMP, a successive approximation logic module SAR, a clock generation module CKG and a reference voltage generation module BGVG; the active-passive noise shaping module comprises a passive integrator PINT1 and a positive feedback active-passive integrator APINT 2;
the signal input in-phase end VINP is connected with a signal input end SGI1 of the DAC capacitor array DAC1, and the signal input out-of-phase end VINN is connected with a signal input end SGI2 of the DAC capacitor array DAC 2; an output end DO1 of the DAC1 is connected with a non-inverting input end RESP of the passive integrator PINT1 and a first non-inverting input end P1 of a six-input comparator COMP; an output end DO2 of the DAC2 is connected with an inverting input end RESN of the passive integrator PINT1 and a first inverting input end N1 of a six-input comparator COMP; the inverting output terminal PT1ON of the passive integrator PINT1 is connected with the inverting input terminal G2IN of the positive feedback active-passive integrator APINT2 and the second inverting input terminal N2 of the six-input comparator COMP; the same-direction output end PT1OP of the passive integrator PINT1 is connected with the non-phase input end G2IP of the positive feedback active-passive integrator APINT2 and the second non-phase input end P2 of the six-input comparator COMP; the non-inverting output terminal AT2OP of the positive feedback active-passive integrator APINT2 is connected to the third non-inverting input terminal P3 of the six-input comparator COMP; the inverting output terminal AT2ON of the positive feedback active-passive integrator APINT2 is connected to the third inverting input terminal N3 of the six-input comparator COMP; the output end of the six-input comparator COMP is connected with the input end of the successive approximation logic module SAR, the in-phase output end SARP of the successive approximation logic module SAR is connected back to the feedback input end FBI1 of the DAC (digital-to-analog converter) capacitor array DAC1, and the reverse-phase output end SARN of the successive approximation logic module SAR is connected back to the feedback input end FBI2 of the DAC capacitor array DAC 2; a digital output bus DOUT is led out from the successive approximation logic module SAR; the global clock signal CLK is connected to an input terminal CK of the clock generation module CKG;
an output end KFS of the clock generation module CKG is commonly connected to a DAC1 and a sampling clock input end FS of the DAC 2; the output terminal KRES of the clock generation module CKG is connected to the residual error sampling clock input terminal phi of the passive integrator PINT1RES(ii) a The output terminals K1 of the clock generation module CKG are respectively connected to the first-order integration clock input terminal phi of the passive integrator PINT11And a first-order integration clock input phi of a positive feedback active-passive integrator APINT21(ii) a The output terminal K2 of the clock generation module CKG is connected to the second-order integration clock input terminal phi of the positive feedback active-passive integrator APINT22(ii) a An output end KCMP of the clock generation module CKG is connected to a clock input end COMPCLK of the six-input comparator COMP; an output end BGVCM of the reference voltage generation module BGVG is connected to a common-mode voltage input end VCM of the passive integrator PINT 1; an output terminal BGVB of the reference voltage generation block BGVG is connected to a bias voltage input terminal VB of the positive feedback active-passive integrator APINT 2.
2. The active-passive noise-shaping successive approximation ADC of claim 1, wherein the passive integrator PINT1 is composed of switches I1-I8 and capacitors C1-C4;
one end of the switch I1 forms a non-inverting input end RESP of the passive integrator PINT1, and the other end of the switch I1 is connected with the upper plate of the capacitor C1 and one end of the switch I3;one end of the switch I2 forms an inverting input end RESP of the passive integrator PINT1, and the other end of the switch I2 is connected with the upper plate of the capacitor C2 and one end of the switch I4; one ends of the switches I5 and I7 are connected with the lower plate of the capacitor C1; one ends of the switches I6 and I8 are connected with the lower plate of the capacitor C2; the other end of the switch I7 is connected with the upper plate of the capacitor C3 to form an inverted output end PT1ON of the passive integrator PINT 1; the other end of the switch I8 is connected with the upper pole plate of the capacitor C4 to form a non-inverting output end PT1OP of the passive integrator PINT 1; the other ends of the switches I3, I4, I5 and I6 form a common-mode voltage input VCM of the passive integrator PINT 1; the control terminals of the switches I1, I2, I5 and I6 form the residual sampling clock Φ of the passive integrator PINT1RES(ii) a The control terminals of the switches I3, I4, I7 and I8 form the first-order integration clock input Φ of the passive integrator PINT11(ii) a The lower plates of the capacitors C3 and C4 are grounded GND.
3. The active-passive noise shaping successive approximation ADC of claim 1, wherein the positive feedback active-passive integrator APINT2 is composed of resistors R1-R2, PMOS transistors MP 1-MP 6, switches I9-I12, capacitors C5-C8 and a common mode feedback module CMFB;
the input end of the common mode feedback module CMFB forms a bias voltage input end VB of the positive feedback active-passive integrator APINT 2; the grid of the PMOS transistor MP1 forms a non-inverting input end G2IP of the positive feedback active-passive integrator APINT2, the source of the PMOS transistor MP1 is connected with the source of the PMOS transistor MP2 and the drain of the PMOS transistor MP3, and the drain of the PMOS transistor MP1 is connected with one end of a resistor R1 and the drain of the PMOS transistor MP 5; the gate of the PMOS transistor MP2 forms the inverting input terminal G2IN of the positive feedback active-passive integrator APINT2, the source of the PMOS transistor MP2 is connected to the source of the PMOS transistor MP1 and the drain of the PMOS transistor MP3, and the drain of the PMOS transistor MP2 is connected to one end of the resistor R2 and the drain of the PMOS transistor MP 4; the source of the PMOS transistor MP3 is connected to the power supply VDD, the gate of the PMOS transistor MP3 is connected to the output terminal VCMFB of the common mode feedback module CMFB, and the drain of the PMOS transistor MP3 is connected to the sources of the PMOS transistors MP1 and MP 2; the grid of the PMOS transistor MP4, the upper plate of the capacitor C8 and one end of the switch I12 are connected to form a positive electrodeThe inverting output end AT2ON of the feedback active-passive integrator APINT2, the source of the PMOS transistor MP4 is linked with the source of the PMOS transistor MP5 and the drain of the PMOS transistor MP6, and the drain of the PMOS transistor MP4 is connected with one end of a resistor R2, the drain of the PMOS transistor MP2 and one end of a switch I9; the grid of the PMOS transistor MP5, the upper plate of the capacitor C7 and one end of the switch I11 are connected to form a non-inverting output end AT2OP of the positive feedback active-passive integrator APINT2, the source of the PMOS transistor MP5 is linked with the source of the PMOS transistor MP4 and the drain of the PMOS transistor MP6, and the drain of the PMOS transistor MP5 is connected with one end of the resistor R1, the drain of the PMOS transistor MP1 and one end of the switch I10; the source of the PMOS transistor MP6 is connected to the power supply VDD, the gate of the PMOS transistor MP6 is connected to the output terminal VCMFB of the common mode feedback module CMFB, and the drain of the PMOS transistor MP6 is connected to the sources of the PMOS transistors MP4 and MP 5; the control terminals of the switches I9 and I10 form the first-order integration clock input Φ of the positive-feedback active-passive integrator APINT21(ii) a The control terminals of the switches I11 and I12 form the second-order integration clock input phi of the positive-feedback active-passive integrator APINT22(ii) a The other end of the switch I9 is connected with the upper plate of the capacitor C5 and the other end of the switch I11; the other end of the switch I10 is connected with the upper plate of the capacitor C6 and the other end of the switch I12; the other ends of the resistors R1 and R2 and the lower plate of the capacitors C5-C8 are grounded GND.
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