CN110190853B - First-order modulator based on static pre-amplifier integrator - Google Patents

Abstract

The invention discloses a first order modulator based on a static pre-amplifier integrator, which comprises: the digital-to-analog converter comprises a static pre-amplifier integrator, a four-input differential comparator, two DAC capacitor arrays and a binary counter with the modulus of N, wherein an input differential signal is connected with the input end of the static pre-amplifier integrator, and the output end of the static pre-amplifier integrator is connected with two reverse input ends of the differential comparator; two output ends of the differential comparator are respectively connected with the input end of the counter and the input ends of the two DAC capacitor arrays; the output ends of the two DAC capacitor arrays are respectively connected to two positive input ends of the differential comparator after being operated with the input differential signal; the output of the counter is used as the output of the whole modulator. The invention saves integral operation, saves power consumption brought by most integrators, and greatly accelerates the establishment speed of the comparator; misjudgment of the comparator caused by a metastable state is reduced to a certain degree, the effective digit of the whole modulator is improved, and the ADC performance of Nyquist bandwidth can be realized.

Description

First-order modulator based on static pre-amplifier integrator

Technical Field

The invention relates to a first-order modulator based on a static pre-amplifier integrator, and belongs to the technical field of integrated circuits.

Background

With the rapid development of semiconductor technology, high-speed and high-precision analog-to-digital converters have been widely used in the fields of digital communication, military radar, and the like. A successive approximation type analog-to-digital converter (SAR ADC) is taken as one of the mainstream ADC products at present, and can well meet the requirements of speed and power consumption after deep submicron. In a successive approximation analog-to-digital converter, due to the limitation of capacitance mismatch and KT/C noise, after the precision of the ADC is more than 12Bit, the requirement of very high precision is difficult to realize, and simultaneously, the speed of the ADC is limited by irrational factors. Since 2009, hybrid SAR architectures have gradually become the focus of research for high-speed, high-precision ADCs, such as hybrid pipeline-SAR, flash-SAR, and the like. In many hybrid architectures, when the accuracy is above 14 bits, the quantization noise, the comparator offset, the operational amplifier offset, the DAC capacitor array mismatch, the power supply ripple, and other various non-ideal factors greatly affect the accuracy, so the Effective Number (ENOB) is generally 2 to 3 bits lower than the accuracy.

In order to achieve better suppression of noise, noise-shaping SAR becomes the preferred structure, and a workflow diagram of a common local noise-shaping SAR ADC is shown in fig. 1. The SAR ADC first performs coarse quantization on an input signal to generate a high-order digital output code and simultaneously sends a margin Vres to a noise shaping loop. The sampled data X of this structure is converted into a digital signal Y by the ADC after passing through the processing block a (z). In order to close the loop, the converted digital signal must be converted into an analog signal by the DAC, and then fed back to the input terminal through a block B (z) to be differentiated from the residual Vres. In the first order linear model, considering that the output Y of the ADC module has a quantization error epsilon, the structure can be obtained to satisfy the following relation:

[V _res -Y·B(z)]A(z)+ε＝Y (1)

obtaining by solution:

the above shows that the margin Vres and the quantization noise epsilon pass through two different transfer functions, respectively:

Y＝V _res ·S(z)+ε·N(z) (3)

where S (z) is a signal transfer function and N (z) is a noise transfer function, S (z) is a low pass filter characteristic and N (z) is a high pass characteristic in order to implement a low pass data converter and maintain effective noise shaping. If B (z) =1, then a (z) must be in the form of an integrator to achieve the desired response.

However, such a hybrid SAR ADC based on noise-shaping has some disadvantages, and since the shaping of the margin is not only performed on a single margin but also performed on the last (k-1) or (k-2) margins at the same time each time, the bandwidth of the entire noise-shaping SAR ADC is determined by the noise-shaping loop bandwidth. Since noise shaping is typically achieved using oversampling and integrators with low pass filtering characteristics, the actual signal bandwidth nyquist bandwidth limits the overall ADC performance. Meanwhile, the voltage integrated by the integrator is a small amount every time, so that the requirements on offset, noise and speed of the comparator are particularly high, and the comparator is easily influenced by PVT change.

Disclosure of Invention

The invention aims to solve the technical problem that in order to realize the performance of Nyquist bandwidth while inhibiting noise, a first-order modulator based on a static pre-amplifier integrator is provided, and the application scene requirements of high speed and low power consumption are met.

The invention specifically adopts the following technical scheme to solve the technical problems:

a first order modulator based on a static pre-amplifier integrator, comprising: the digital-to-analog converter comprises a static pre-amplifier integrator, a four-input differential comparator, two DAC capacitor arrays and a binary counter with the modulus of N, wherein an input differential signal is connected with the input end of the static pre-amplifier integrator, and the output end of the static pre-amplifier integrator is connected with two reverse input ends of the differential comparator; two output ends of the differential comparator are respectively connected with the input end of the counter and the input ends of the two DAC capacitor arrays; the output ends of the two DAC capacitor arrays are respectively connected to two positive input ends of the differential comparator after being operated with the input differential signal; and the output end of the counter is used as the output end of the whole modulator.

Further, as a preferred technical solution of the present invention, the static pre-amplifier integrator is composed of a pre-amplifier stage and an output stage.

Further, as a preferred technical solution of the present invention, the pre-amplifying stage in the static pre-amplifier integrator includes: the clock control circuit comprises complementary input NMOS paired transistors consisting of NMOS transistors M1 and M2, PMOS paired transistors consisting of PMOS transistors M3 and M4, and a clock control transistor consisting of an NMOS transistor M5 and a PMOS transistor M6, wherein a clock control signal CLK is connected with a grid electrode of the NMOS transistor M5, a source electrode of the NMOS transistor M5 is grounded, and a drain electrode of the NMOS transistor M5 is respectively connected with source electrodes of the NMOS transistors M1 and M2; the grid electrode of the NMOS tube M1 is connected with an input signal Vip, and the drain electrode of the NMOS tube M1 is connected with the drain electrode of the PMOS tube M3; the grid electrode of the NMOS tube M2 is connected with an input signal Vin, and the drain electrode of the NMOS tube M2 is connected with the drain electrode of the PMOS tube M4; the grid electrode of the PMOS tube M3 is connected with an input signal Vip, and the source electrode of the PMOS tube M3 is connected with the drain electrode of the PMOS tube M6; the grid electrode of the PMOS tube M4 is connected with the input signal Vin, and the source electrode of the PMOS tube M4 is connected with the drain electrode of the PMOS tube M6; grid connection clock control signal of PMOS (P-channel metal oxide semiconductor) transistor M6

And its source is connected to the supply voltage VDD.

Further, as a preferable technical solution of the present invention, the static pre-amplification integralThe output stage in the device comprises: the amplifier comprises a common-gate input geminate transistor consisting of NMOS transistors M7 and M8, a reset transistor M9, an integral capacitor Cint, common-mode feedback capacitors C1 and C2, a clock control transistor consisting of PMOS transistors M10 and M11, and a current transistor consisting of PMOS transistors M12 and M13, wherein a clock control signal CLK is connected with the grids of the NMOS transistors M7 and M8, the sources of the NMOS transistors M7 and M8 are respectively connected to a pre-amplification stage, the drain of the NMOS transistor M7 is connected with the output end Vop of a static pre-amplification integrator, and the drain of the NMOS transistor M8 is connected with the output end Von of the static pre-amplification integrator; the grid electrode of the Reset tube M9 is connected with a Reset signal Reset, and the source electrode and the drain electrode of the Reset tube M9 are respectively connected with the output ends Von and Vop of the static preamplification integrator; two ends of the integrating capacitor Cint are respectively connected with the output ends Von and Vop of the static pre-amplification integrator; after short circuit, two ends of the common mode feedback capacitors C1 and C2 are respectively connected with the output ends Von and Vop of the static pre-amplifier integrator, and after short circuit, the common mode feedback capacitors are connected with the grids of the NMOS transistors M12 and M13; clock control signal

The grid electrodes of the PMOS tubes M10 and M11 are respectively connected, the drain electrode of the PMOS tube M10 is connected with the output end Vop of the static preamplification integrator, the source electrode of the PMOS tube M10 is connected with the drain electrode of the PMOS tube M12, the drain electrode of the PMOS tube M11 is connected with the output end Von of the static preamplification integrator, and the source electrode of the PMOS tube M13 is connected with the drain electrode of the PMOS tube M13; the source electrode of the PMOS tube and the source electrode of the PMOS tube M13 are connected with the power voltage VDD.

By adopting the technical scheme, the invention can produce the following technical effects:

the first-order modulator based on the pre-amplifier integrator only needs one integration operation for completing each conversion and 2 ^N Sub-voltage comparison operation, and thus needs 2 compared to conventional first order modulators ^N Sub-integration operation and 2 ^N The secondary voltage comparison operation saves 2 ^N 1 integration operation, saving most of the power consumption brought by the integrator; meanwhile, the static open-loop integrator amplifies the input voltage signal by 2 ^N The speed of establishing the comparator is greatly increased; meanwhile, the 'misjudgment' of the comparator caused by the metastable state is reduced to a certain degree, so that the effective bit of the whole modulator is improved; in addition, the same margin is input due to local oversamplingThe ADC performance of the nyquist bandwidth can be achieved by repeating the comparison quantization a number of times, so that when the modulator is used in a hybrid ADC, the bandwidth of its ADC is not limited, thereby enabling the ADC to achieve the normal nyquist signal bandwidth.

Drawings

FIG. 1 is an equivalent block diagram of a conventional first-order shading sigma-delta ADC.

Fig. 2 is a schematic diagram of a pre-integrator based first order modulator ISDM according to the present invention.

FIG. 3 is a circuit diagram of a static pre-amplifier integrator according to an embodiment of the present invention.

Fig. 4 is a system clock diagram of an ISDM modulator according to an embodiment of the present invention.

Fig. 5 is a simulation waveform diagram of input and output of the pre-amplifier integrator in the embodiment of the invention.

FIG. 6 is a waveform diagram simulated for an input signal according to an embodiment of the present invention.

FIG. 7 is a graph comparing the significance of an ISDM incorporating SAR ADC of the present invention with that of a conventional ADC as a function of comparator noise.

Detailed Description

The following describes embodiments of the present invention with reference to the drawings.

As shown in fig. 2, the present invention designs a first-order modulator ISDM based on static pre-amplifier integrator, which mainly includes: the digital-to-analog converter comprises a static pre-amplifier integrator Int, a four-input differential comparator, two DAC capacitor arrays DAC _ N and a binary counter with the modulus of N, wherein input differential signals Vip and Vin are connected with the input end of the static pre-amplifier integrator, and the output end of the static pre-amplifier integrator is connected with two reverse input ends of the differential comparator; two output ends of the differential comparator are respectively connected with the input end of the counter and the input ends of the two DAC capacitor arrays; the output ends of the two DAC capacitor arrays are respectively connected with input differential signals Vip and Vin to two positive input ends of a differential comparator after operation processing at a summing node; and the output end of the counter is used as the output end of the whole modulator.

Fig. 3 is a circuit diagram of a static preamplification integrator composed of a preamplification stage and an output stage according to an embodiment of the invention.

Specifically, the pre-amplification stage in the static pre-amplifier integrator comprises: the clock control circuit comprises complementary input NMOS (N-channel metal oxide semiconductor) geminate transistors consisting of NMOS (N-channel metal oxide semiconductor) tubes M1 and M2, PMOS geminate transistors consisting of PMOS (P-channel metal oxide semiconductor) tubes M3 and M4 and a clock control tube consisting of an NMOS tube M5 and a PMOS tube M6, wherein a clock control signal CLK (clock signal) is connected with a grid electrode of the NMOS tube M5, a source electrode of the NMOS tube M5 is grounded GND (ground) and a drain electrode of the NMOS tube M5 is respectively connected with source electrodes of the NMOS tubes M1 and M2; the grid electrode of the NMOS tube M1 is connected with an input signal Vip, and the drain electrode of the NMOS tube M1 is connected with the drain electrode of the PMOS tube M3; the grid electrode of the NMOS tube M2 is connected with an input signal Vin, and the drain electrode of the NMOS tube M2 is connected with the drain electrode of the PMOS tube M4; the grid electrode of the PMOS tube M3 is connected with an input signal Vip, and the source electrode of the PMOS tube M3 is connected with the drain electrode of the PMOS tube M6; the grid electrode of the PMOS tube M4 is connected with the input signal Vin, and the source electrode of the PMOS tube M4 is connected with the drain electrode of the PMOS tube M6; grid connection clock control signal of PMOS (P-channel metal oxide semiconductor) transistor M6

And its source is connected to the supply voltage VDD.

Specifically, the output stage in the static pre-amplifier integrator comprises: a common-gate input geminate transistor consisting of NMOS transistors M7 and M8, a reset transistor M9, an integral capacitor Cint, common-mode feedback capacitors C1 and C2, a clock control transistor consisting of PMOS transistors M10 and M11, and a current transistor consisting of PMOS transistors M12 and M13, wherein a clock control signal CLK is connected with the grids of the NMOS transistors M7 and M8, the source electrode of the NMOS transistor M7 is connected with the drain electrode of the NMOS transistor M1 in the preamplifier stage, the source electrode of the NMOS transistor M8 is connected with the drain electrode of the NMOS transistor M2 in the preamplifier stage, the drain electrode of the NMOS transistor M7 is connected with the output end Vop of the static preamplifier integrator, and the drain electrode of the NMOS transistor M8 is connected with the output end Von of the static preamplifier integrator; the grid electrode of the Reset tube M9 is connected with a Reset signal Reset, and the source electrode and the drain electrode of the Reset tube M9 are respectively connected with the output ends Von and Vop of the static preamplification integrator; two ends of the integrating capacitor Cint are respectively connected with the output ends Von and Vop of the static pre-amplifier integrator; short-circuit is carried out between the common mode feedback capacitors C1 and C2 to obtain short-circuit points, two ends of the common mode feedback capacitors C1 and C2 after short-circuit are respectively connected with output ends Von and Vop of the static preamplification integrator, and the short-circuit points are also connected with grids of PMOS tubes M12 and M13; clock control signal

The grid electrodes of the PMOS tubes M10 and M11 are respectively connected, the drain electrode of the PMOS tube M10 is connected with the output end Vop of the static preamplification integrator, the source electrode of the PMOS tube M10 is connected with the drain electrode of the PMOS tube M12, the drain electrode of the PMOS tube M11 is connected with the output end Von of the static preamplification integrator, and the source electrode of the PMOS tube M13 is connected with the drain electrode of the PMOS tube M13; the source electrode of the PMOS tube M12 and the source electrode of the PMOS tube M13 are connected with the power voltage VDD.

The differential comparator is composed of four input ports Vxp, vxn, vyp and Vyn, wherein Vxp is obtained by summing an input signal Vip and an output signal of a DAC capacitor array DAC _ P; vxn is obtained by summing an input signal Vin and an output signal of another DAC capacitor array DAC _ N; and Vyp and Vyn are respectively connected with output ports Vop and Von of the static pre-amplifier integrator. The comparator is provided with two output ports Dout + and Dout-, wherein the Dout + is connected with one input end of the binary counter and one DAC _ P input end of the DAC capacitor array; dout-is connected to one input of the binary counter and to the input of the other DAC capacitor array DAC _ N. The two input terminals of the binary Counter are respectively connected to the output terminals Dout + and Dout-, and the output terminal of the binary Counter is an NBit binary code stream signal.

Based on the circuit structure of the static pre-amplifier integrator and based on the clock diagram shown in fig. 4, the working process specifically includes:

(1) When the clock control signal CLK =1, the clock control signal

NMOS tubes M5, M6, M10 and M11 are conducted simultaneously, input signals Vip and Vin are amplified through complementary input pair tubes M1, M2, M3 and M4 respectively, the amplified signals charge an integrating capacitor Cint of an output node through NMOS tubes M7 and M8, C1 and C2 serve as work mode feedback capacitors, short-circuit points of the capacitors gradually rise along with the charging of the output node, and when the voltage of the points rises to be equal to VDD- | V _thp When |, the NMOS transistors M12, M13 are turned off, where | V _thp And | represents the threshold voltage of the PMOS tube, the integration time is over, and the charging time is the CLK high level duration Tint.

(2) When the clock control signal CLK =0, the clock control signal

The NMOS transistors M5, M6, M10 and M11 are simultaneously cut off, and the voltage difference of the output nodes is kept on the integrating capacitor Cint.

(3) When the Reset signal Reset =1, the output node is Reset to output a common mode voltage, a voltage difference between two ends of the integrating capacitor Cint becomes 0, and the integrator completes a complete working process.

The working principle of the ISDM modulator in the embodiment of the present invention is based on the clock diagram shown in fig. 4, and specifically includes the following processes:

(1) When Reset signal Reset =1, the entire modulator is Reset. When the clock control signal CLK is high, the clock control signal

When the level is low, the integrator performs integral amplification on the input signal, and the integration time and the gain of the integrator are determined by the high level duration of the CLK.

(2) When the clock control signal CLK is low, the clock control signal

At high level, the circuit enters a loop comparison state, and at each comparison clock CMP =1, the comparator compares the magnitude relation between the difference value of the input signal Vip-Vin and the integral signal Vyp-Vyn:

if Vip-Vin < Vyp-Vyn is satisfied, dout + =1, dout- =0, and the counter is increased by 1;

if Vip-Vin > Vyp-Vyn is satisfied, then Dout + =0, dout- =1, while the counter is decremented by 1.

The DAC generates a voltage signal related to Dout +, dout-which is fed back to the input summing node and subtracted from the input signal, the positive and negative of the generated voltage being dependent on Dout +, dout-being equal to 1 or 0. The integrator output voltage remains at the integrating capacitor Cint at this stage until Cint is reset again after the end of the last compare period. Finally, the amplitude of the voltage signal of the upper electrode plate of the DAC capacitor array of the ADC can be obtained according to the counting result of the counter, namely the input end of the comparator is as follows:

wherein, dout + and Dout-are the output result of each comparison by the comparator, N represents the comparison times, and N =2 ⁿ N is ADC precision, V _ref (i) For each reference voltage generated by the DAC, V is the first order delta modulation _ref Is a constant value.

The pre-amplifier integrator of the present invention was simulated, and the input and output waveforms are shown in fig. 5. As can be seen from fig. 5, the integrator can pre-amplify the input differential signal with a gain of 8.1 times. The invention carries out behavioral level simulation aiming at a 3-Bit first-order incremental modulator, the gain of a required integrator is about 8 times, for an input differential small signal, the changes of integrated signals Vyp and Vyn and signals Vxp and Vxn at the input end of a comparator along with the comparison times are shown in fig. 6, and the output digital code of the comparator under the condition shown in fig. 6 is as follows: 11111111.

for the performance test of the hybrid ISDM-SAR ADC, selecting 9Bit SAR +2bit ISDM (11 Bit precision) and the SAR ADC with 11Bit to carry out a comparison test, adding the same comparator input noise to the two comparators simultaneously in the test, and measuring the effective digit of the ADC, as shown in FIG. 7. As can be seen from fig. 7, the hybrid ISDM-SAR ADC has a better noise suppression effect, and therefore, the present invention has a certain use value.

In summary, the present invention only needs one integration operation and 2 for each conversion ^N The sub-voltage comparison operation, thus saving 2 compared to a conventional first order modulator ^N 1 integration operation, saving most of the power consumption brought by the integrator; meanwhile, the static open-loop integrator amplifies the input voltage signal by 2 ^N The speed of establishing the comparator is greatly increased; meanwhile, misjudgment of the comparator caused by metastable state is reduced to a certain degree, so that the effective bit of the whole modulator is improved; in addition, local oversampling is adopted, and multiple repeated comparison and quantization are carried out on the same margin, so that the method can realize the effect of quantizationADC performance at nyquist bandwidth.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims (4)

1. A first order modulator based on a static pre-amp integrator, comprising: the digital-to-analog converter comprises a static open-loop pre-amplifier integrator, a four-input differential comparator, two DAC capacitor arrays and a binary counter with the modulus of N, wherein an input differential signal is connected with the input end of the static pre-amplifier integrator, and the output end of the static pre-amplifier integrator is connected with two reverse input ends of the differential comparator; two output ends of the differential comparator are respectively connected with the input end of the counter and the input ends of the two DAC capacitor arrays; the output ends of the two DAC capacitor arrays are respectively connected to two positive input ends of the differential comparator after being subjected to operation processing with the input differential signals; and the output end of the counter is used as the output end of the whole modulator.

2. A first order modulator based on a static open-loop pre-amplifier integrator as claimed in claim 1, characterized in that the static open-loop pre-amplifier integrator consists of a pre-amplifier stage and an output stage.

3. The static pre-amplifier integrator-based first order modulator of claim 2, wherein the pre-amplifier stage in the static open-loop pre-amplifier integrator comprises: the clock control circuit comprises complementary input NMOS paired transistors consisting of NMOS transistors M1 and M2, PMOS paired transistors consisting of PMOS transistors M3 and M4, and a clock control transistor consisting of an NMOS transistor M5 and a PMOS transistor M6, wherein a clock control signal CLK is connected with a grid electrode of the NMOS transistor M5, a source electrode of the NMOS transistor M5 is grounded, and a drain electrode of the NMOS transistor M5 is respectively connected with source electrodes of the NMOS transistors M1 and M2; the grid electrode of the NMOS tube M1 is connected with an input signal Vip, and the drain electrode of the NMOS tube M1 is connected with the drain electrode of the PMOS tube M3; the grid electrode of the NMOS tube M2 is connected with an input signal Vin, and the drain electrode of the NMOS tube M2 is connected with the drain electrode of the PMOS tube M4; the grid of the PMOS tube M3 is connected with an input signal Vip, and the source electrode of the PMOS tube M3 is connected with PMOSA drain of tube M6; the grid electrode of the PMOS tube M4 is connected with the input signal Vin, and the source electrode of the PMOS tube M4 is connected with the drain electrode of the PMOS tube M6; grid electrode connection clock control signal of PMOS (P-channel metal oxide semiconductor) transistor M6

And its source is connected to the supply voltage VDD.

4. The static pre-amplifier integrator-based first order modulator of claim 1, wherein the output stage of the static open-loop pre-amplifier integrator comprises: the amplifier comprises a common-gate input geminate transistor consisting of NMOS transistors M7 and M8, a reset transistor M9, an integral capacitor Cint, common-mode feedback capacitors C1 and C2, a clock control transistor consisting of a PMOS transistor M10 and a PMOS transistor M11, and a current transistor consisting of a PMOS transistor M12 and a PMOS transistor M13, wherein a clock control signal CLK is connected with the grids of the NMOS transistors M7 and M8, the sources of the NMOS transistors M7 and M8 are respectively connected to a pre-amplification stage, the drain of the NMOS transistor M7 is connected with the output end Vop of a static pre-amplification integrator, and the drain of the NMOS transistor M8 is connected with the output end Von of the static pre-amplification integrator; the grid electrode of the Reset tube M9 is connected with a Reset signal Reset, and the source electrode and the drain electrode of the Reset tube M9 are respectively connected with the output ends Von and Vop of the static preamplification integrator; two ends of the integrating capacitor Cint are respectively connected with the output ends Von and Vop of the static pre-amplifier integrator; after short circuit, two ends of the common mode feedback capacitors C1 and C2 are respectively connected with the output ends Von and Vop of the static pre-amplifier integrator, and after short circuit, the common mode feedback capacitors are connected with the grid electrodes of the PMOS tubes M12 and M13; clock control signal

The grid electrodes of the PMOS tubes M10 and M11 are respectively connected, the drain electrode of the PMOS tube M10 is connected with the output end Vop of the static preamplification integrator, the source electrode of the PMOS tube M10 is connected with the drain electrode of the PMOS tube M12, the drain electrode of the PMOS tube M11 is connected with the output end Von of the static preamplification integrator, and the source electrode of the PMOS tube M13 is connected with the drain electrode of the PMOS tube M13; the source electrode of the PMOS tube M12 and the source electrode of the PMOS tube M13 are connected with the power voltage VDD.

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