CN110311683B - Sigma-Delta modulator based on VCO quantizer - Google Patents

Sigma-Delta modulator based on VCO quantizer Download PDF

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CN110311683B
CN110311683B CN201910429272.6A CN201910429272A CN110311683B CN 110311683 B CN110311683 B CN 110311683B CN 201910429272 A CN201910429272 A CN 201910429272A CN 110311683 B CN110311683 B CN 110311683B
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vco
transistor
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CN110311683A (en
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朱樟明
朱冬琳
刘马良
刘术彬
刘帘曦
杨银堂
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Xidian University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/344—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution

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Abstract

The invention discloses a Sigma-Delta modulator based on a VCO (voltage controlled oscillator) quantizer, which comprises a VCO quantization module (1), a feedback module (2), an input capacitor C and an input resistor R; wherein the VCO quantization module (1) is connected with an input end V through the input capacitor CINFor receiving and quantizing an input signal and outputting a digital signal; the input end of the feedback module (2) is connected with the output end of the VCO quantization module (1), and the output end of the feedback module (2) is connected with the input end of the VCO quantization module (1) and is used for feeding back the output code of the VCO quantization module (1) to the input end; one end of the input resistor R is connected between the input capacitor C and the VCO quantization module (1), and the other end of the input resistor R is connected with VCMA level. The Sigma-Delta modulator based on the VCO quantizer combines the VCO and the Sigma-Delta ADC, utilizes the VCO as the quantizer, realizes low power supply voltage work, adopts the Sigma-Delta modulator structure, simplifies the system structure, reduces the power consumption and the area, and ensures the good performance of the circuit.

Description

Sigma-Delta modulator based on VCO quantizer
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a Sigma-Delta modulator based on a VCO quantizer.
Background
An Analog-to-Digital Converter (ADC) is a device that converts a continuously changing Analog signal into a discrete Digital signal, and plays a very important role in signal processing. Conventional ADCs perform digital quantization by comparing an analog input voltage with a reference voltage in the voltage domain, and the ability to resolve the input voltage determines the performance of the ADC circuit. With the progress of semiconductor process, the power supply voltage of the chip is continuously reduced, which brings many problems for the design of the traditional structure analog circuit, such as the reduction of the swing of input and output voltage, the deterioration of linearity, the reduction of the voltage value corresponding to one conversion step when the digits are the same, and the like; meanwhile, due to the comparison accuracy of the comparator, it is very difficult to directly complete the quantization of the analog input voltage, which undoubtedly increases the difficulty of ADC design. In addition, the sensing device powered by the battery also puts higher requirements on the power consumption of the chip circuit inside the ADC in order to realize long-term stable operation.
The modulator belongs to an important part in an ADC circuit, and the structure selection and the circuit parameter design of the modulator greatly influence each performance index of the whole ADC. Therefore, designing a modulator which operates at a low power supply voltage, has low power consumption, a small area and high performance is of great significance for improving the overall performance of the ADC.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a Sigma-Delta modulator based on a VCO quantizer. The technical problem to be solved by the invention is realized by the following technical scheme:
a Sigma-Delta modulator based on a VCO quantizer comprises a VCO quantization module, a feedback module, an input capacitor C and an input resistor R; wherein the content of the first and second substances,
the VCO quantization module is connected with an input end V through the input capacitor CINFor receiving and quantizing an input signal and outputting a digital signal;
the input end of the feedback module is connected with the output end of the VCO quantization module, and the output end of the feedback module is connected with the input end of the VCO quantization module and is used for feeding back the output code of the VCO quantization module to the input end;
one end of the input resistor R is connected between the input capacitor C and the VCO quantization module, and the other end of the input resistor R is connected with VCMA level.
In one embodiment of the invention, the VCO quantization module comprises a fully differential VCO cell, a comparator array, a digital accumulation unit; wherein the content of the first and second substances,
the fully differential VCO unit respectively passes through N-end capacitance C of the input capacitance CINAnd a P-terminal capacitor CIPConnecting differential input signalsVINNAnd VINPA differential input signal receiving circuit for receiving the differential input signal and outputting a first signal;
the comparator array is connected with the fully differential VCO unit and used for receiving and processing a first signal and outputting a second signal;
the digital accumulation unit is used for receiving and processing the second signal and outputting a digital signal.
In one embodiment of the invention, the fully differential VCO unit comprises an n-stage ring oscillator and m external control circuits for control signals, wherein n is a positive integer and n ≧ 1, and m is an even number and m ≧ 4.
In one embodiment of the present invention, the external control circuit includes a transistor MV1, symmetrically arranged input transistors MN1, MP1, symmetrically arranged N-terminal control circuit and P-terminal control circuit, wherein,
the P-end control circuit and the N-end control circuit respectively comprise i pull-up links and j pull-down links, wherein i and j are positive integers, and i + j is m.
In one embodiment of the invention, the comparator array comprises 2n-1 dynamic comparators each comprising a dynamic amplifier and a latch, wherein,
the dynamic amplifier comprises transistors M1-M9, wherein a source and a gate of the transistor M1 are respectively connected with a VDD terminal and a CLK signal, a drain of the transistor M1 is connected with sources of the transistors M2 and M3, gates of the transistors M2 and M3 are respectively used as input interfaces for receiving the first signal, sources of the transistors M4 and M5 are connected with each other, a gate of the transistor M6 and a gate of the transistor M9 are both connected with the CLK signal, a drain of the transistor M2, a drain of the transistor M4, a source of the transistor M6, a gate of the transistor M5, a drain of the transistor M7 and a gate of the transistor M8 are connected with each other and connected with the latch through a node A; the drain of the transistor M3, the drain of M5, the drain of M6, the gate of M4, the gate of M7 and the drain of M8 are connected with each other and the latch through a node B, the source of the transistor M7, the source of M8 and the drain of M9 are connected with each other, and the source of the transistor M9 is grounded;
the latch comprises transistors M10-M17, wherein the sources of the transistors M10-M13 are all connected with a VDD terminal, the gate of the transistor M10 and the gate of the transistor M16 are all connected with the node A, the gate of the transistor M13 and the gate of the transistor M17 are all connected with the node B, the drain of the transistor M10, the drain of the transistor M11, the gate of the transistor M14, the gate of the transistor M12 and the gate of the transistor M15 are mutually connected with a node OA, the drain of the transistor M12, the drain of the transistor M13, the drain of the transistor M15, the gate of the transistor M11 and the gate of the transistor M14 are mutually connected with a node OB, and the second signal is output through a node Q.
In an embodiment of the present invention, the feedback module includes a conversion unit, a dynamic matching unit, a sample-and-hold unit, and a feedback capacitance digital-to-analog conversion unit; wherein the content of the first and second substances,
the conversion unit is connected with the digital accumulation unit and is used for receiving and processing the digital signal and outputting a thermometer code signal;
one end of the dynamic matching unit is connected with the conversion unit, and the other end of the dynamic matching unit is connected with the feedback capacitor digital-to-analog conversion unit through a sampling and holding unit and is used for receiving the thermometer code signal and outputting a control signal to control the feedback capacitor digital-to-analog conversion unit to randomly select a feedback sub-unit;
the slave sampling and holding unit is used for carrying out time delay on the control signal and outputting a delay signal;
the feedback capacitance digital-to-analog conversion unit is connected with the fully-differential VCO unit and used for receiving the delay signal and regulating and controlling the input signal of the fully-differential VCO unit.
In one embodiment of the present invention, the feedback capacitance digital-to-analog conversion unit comprises 2nA stage C-DAC subunit, wherein each bit of the C-DAC subunit comprises a capacitor CNAnd a capacitor CPSaid capacitor CNThe upper electrode plate of the capacitor is connected with the N-end capacitor C of the input capacitor CINAnd said capacitor C between said fully differential VCO cellPThe upper electrode plate of the capacitor is connected with a P-end capacitor C of the input capacitor CIPAnd said capacitor C between said fully differential VCO cellNLower plate of and said capacitor CPLower pole plateThe reference voltage V is connected via a conversion circuitrefpAnd VrefnAnd (4) an end.
The invention has the beneficial effects that:
1. the invention adopts a continuous time Sigma-Delta modulator structure, and compared with ADCs with other structures, the invention omits a filter structure with complicated front end because the Sigma-Delta modulator structure has anti-aliasing filtering characteristic, thereby having simpler structure and saving partial power consumption and area.
2. The VCO is used as a quantizer, input voltage signals can be quantized in a time domain, the problem caused by the fact that the quantization amplitude of the traditional quantizer is reduced due to the reduction of the power supply voltage is solved, and the low power supply voltage application scene can be met; meanwhile, the VCO has the characteristic of first-order integration, so that first-order noise shaping can be performed on quantization noise, and the introduction of a continuous time integrator is avoided, thereby avoiding circuit modules with high power consumption, such as an operational amplifier and the like, being introduced into a front-end circuit, and reducing the power consumption and the area.
3. In the internal structure of the VCO, an odd number of inverters are cascaded to form a delay unit, so that the delay unit has a steeper phase waveform, errors of a subsequent comparator in phase signal acquisition and comparison processes are further reduced, and the precision is effectively improved; meanwhile, a control circuit is added at the input end of the VCO, so that the influence of Process, power supply Voltage and environment Temperature (PVT) change on the oscillation frequency of the VCO can be effectively adjusted.
4. Compared with the traditional resistance DAC, the invention adopts the capacitance DAC feedback module, thereby not only improving the linearity of the DAC module, but also reducing the overall power consumption.
5. The invention adopts the digital circuit to realize the matching of the register, the adder, the dynamic unit and the like, has high system digitization degree, and has better adaptability to the change of the semiconductor manufacturing process while reducing the circuit area.
6. The system of the invention adopts a structure without an operational amplifier, thereby simplifying the system structure and reducing the overall power consumption.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a Sigma-Delta modulator based on a VCO quantizer according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a Sigma-Delta modulator based on a VCO quantizer according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a feedback system provided by an embodiment of the present invention;
fig. 4 is a schematic diagram of a basic structure of a ring VCO according to an embodiment of the present invention;
figure 5 is a schematic diagram of an external control circuit for a ring VCO according to an embodiment of the present invention;
fig. 6 is a structural diagram of an external control circuit of a ring VCO with 4 control signals according to an embodiment of the present invention;
fig. 7 is a block diagram of an external control circuit of a ring VCO with 6 control signals according to an embodiment of the present invention;
FIGS. 8 a-8 b are schematic diagrams of dynamic comparators provided in embodiments of the present invention;
FIG. 9 is a timing diagram of a dynamic comparator according to an embodiment of the present invention;
FIGS. 10 a-10 b are schematic diagrams of conventional dynamic comparators provided by embodiments of the present invention;
FIG. 11 is a diagram of a quantization scheme provided by an embodiment of the present invention;
fig. 12 is a graph of the frequency characteristic of an input high pass filter provided by an embodiment of the present invention;
fig. 13 is a DEM schematic diagram provided by an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a Sigma-Delta modulator based on a VCO quantizer according to an embodiment of the present invention;
the invention provides a Sigma-Delta modulator based on a VCO (voltage-controlled oscillator) quantizer, which comprises a VCO quantizing module 1, a feedback module 2, an input capacitor C and an input resistor R, wherein the VCO quantizing module 1 is connected with the feedback module C; wherein the content of the first and second substances,
the VCO quantization module 1 is connected with an input end V through the input capacitor CINFor receiving and quantizing an input signal and outputting a digital signal;
the input end of the feedback module 2 is connected with the output end of the VCO quantization module 1, and the output end of the feedback module 2 is connected with the input end of the VCO quantization module 1, and is configured to feed back the output code of the VCO quantization module 1 to the input end;
one end of the input resistor R is connected between the input capacitor C and the VCO quantization module 1, and the other end of the input resistor R is connected with VCMA level.
External input voltage VINThe input capacitor is coupled to the input end of the VCO quantization module 1, digital binary codes are output after quantization, meanwhile, the binary codes are converted into corresponding thermometer codes through the feedback module 2, corresponding analog voltage values are obtained and fed back to the input end of the VCO quantization module 1, the analog voltage values are input into the VCO quantization module 1 after being differed with external input voltage, the level of the input end is kept in a small range, and the stability of a system is maintained.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another Sigma-Delta modulator based on a VCO quantizer according to an embodiment of the present invention;
in this embodiment, the VCO quantization module 1 includes a fully differential VCO unit (VCO ADC), a Comparator Array (Comparator Array), a digital summation unit (Delta Sigma Accumulator); wherein the content of the first and second substances,
the fully differential VCO unit (VCO ADC) respectively passes through the N-end capacitor CIN and the P-end capacitor C of the input capacitor CIPConnecting differential input signals VINNAnd VINPA differential input signal receiving circuit for receiving the differential input signal and outputting a first signal;
the Comparator Array (Comparator Array) is connected with the fully differential VCO unit (VCO ADC) and used for receiving and processing a first signal and outputting a second signal;
the digital accumulation unit (Delta Sigma Accumulator) is used for receiving and processing the second signal and outputting a digital signal.
The Voltage Controlled Oscillator (VCO) used in the invention refers to an oscillating circuit whose output frequency is controlled by input voltage, and an oscillator whose oscillating frequency and input control voltage have a functional relation. The advantage of the VCO-type ADC is mainly that it can perform quantization of the signal in the time domain, which is suitable for operation at low supply voltages since the quantization in the time domain is insensitive to variations in the supply voltage. The VCO is used as a quantizer, input voltage signals can be quantized in a time domain, the problem caused by the fact that the quantization amplitude of the traditional quantizer is reduced due to the reduction of the power supply voltage is solved, and the low power supply voltage application scene can be met;
the general VCO structure types are: LC-type VCOs, RC-type VCOs, crystal-type VCOs, and ring-type VCOs. In this embodiment, a VCO-based Sigma-Delta modulator employs a ring VCO. Compared with other types of VCO, the annular VCO has the advantages of simple structure, easy integration and contribution to area reduction and power consumption reduction.
The basic principle of a ring VCO is the oscillation generated by the feedback system. Referring to fig. 3, fig. 3 is a schematic structural diagram of a feedback system according to an embodiment of the present invention; in the feedback system shown in fig. 3, there are:
Figure BDA0002068453980000081
wherein, VinFor input, VoutFor output, H(s) is a feedback function.
Oscillation occurs when the system phase shift is large enough that the feedback of the entire system changes from negative to positive. Because of positive feedback, the phase of the input signal is opposite to that of the feedback signal, and the input signal and the feedback signal generate larger difference through signal subtraction, so that the circuit signal can be continuously regenerated, and the output signal of the system is continuously enlarged. If let's H (jw)0) 180 °, its output amplitude expression is as follows:
Vout＝Vin+|H(jw0)|·Vin+|H(jw0)|2·Vin+|H(jw0)|3·Vin+...
when | H (jw)0)|>1 hour, VoutWill diverge.
Thus, the conditions under which a negative feedback system generates oscillations are:
|H(jw0)|＞1
∠H(jw0)＝180°
in this embodiment, the fully differential VCO unit includes an n-stage ring oscillator and an external control circuit having m control signals, where n is a positive integer and n ≧ 1, and m is an even number and m ≧ 4.
Referring to fig. 4, fig. 4 is a schematic diagram of a basic structure of a ring VCO according to an embodiment of the present invention;
in the present embodiment, the n-stage ring VCO is composed of 2n-1 stage reverse delay unit cascaded end to end, each stage having a voltage control terminal VCin. The invention adopts odd number of phase inverters to form a delay unit, thus leading the delay unit to have steeper phase waveform, further reducing the error of the subsequent comparator in the process of phase signal acquisition and comparison, and effectively improving the precision.
According to the Barkhausen criterion, the gain of each stage of cells is greater than 2, and 2nThe total phase shift of the system after 1 stage cascade is 180 °. The inverting delay unit may be formed by an inverter with a single stage gain greater than 2 and a single stage phase shift of 180 °, so the total dc phase shift of the oscillator is 180 °. At the same time, the signal amplitude is increasing. At this time, the circuit enters a large-signal nonlinear working state, and the circuit linear small-signal analysis method is not applicable any more. This is the oscillation principle of the ring VCO. The frequency of the output oscillation signal is controlled by the input signal, and the delay time of each stage of the inverting delay unit is assumed to be TdelayThe signal passes through 2n-1 stage delay followed by time n x T to the final stage outputdelaySo that the output of the last stage is kept at n x TdelayWill change after that time. Meanwhile, the output signal half period of the ring oscillator is n T because of the inverted statedelayThus having an output frequency of：
Figure BDA0002068453980000091
In order to effectively adjust the influence of Process, power supply Voltage and environment Temperature (PVT) change on the oscillation frequency of the VCO, the invention is provided with an external control circuit at the input end of the VCO, and for the ring VCO with a fixed structure, the delay of an inverting unit can be controlled by changing the magnitude of the input Voltage so as to change the oscillation frequency of the VCO.
Referring to fig. 5, fig. 5 is a schematic diagram of an external control circuit of a ring VCO according to an embodiment of the present invention; in the figure, VCON and VCOP represent the N and P inputs, respectively, of the ring VCO. The use of differential signal input can suppress common mode noise and even harmonics, improving the linearity of the ring oscillator.
In this embodiment, the external control circuit includes a transistor MV1, symmetrically arranged input transistors MN1, MP1, symmetrically arranged N-terminal control circuit and P-terminal control circuit, wherein,
the P-end control circuit and the N-end control circuit respectively comprise i pull-up links and j pull-down links, wherein i and j are positive integers, i + j is m, and m is the number of control signals.
When the oscillation frequency of the ring oscillator is changed due to the process angle deviation and/or the temperature change, the current flowing into the ring oscillator can be adjusted through an external control circuit. Specifically, the upper zipper is used for increasing the current flowing into the ring oscillator and increasing the oscillation frequency of the ring oscillator to a normal working range; the pull-down link is used for reducing the current flowing into the ring oscillator and reducing the oscillation frequency of the ring oscillator to a normal working range;
because of the double-end input signal used by the invention, when an external control circuit is designed, a P-end control circuit and an N-end control circuit are symmetrically arranged and comprise a pull-up link and a pull-down link, therefore, the invention at least needs 4 paths of control signals to regulate the input of the VCO.
The operating principle of the VCO external control circuit of the present invention will be described in detail below by taking an example of 4 control signals, i.e., 4 control signals.
Referring to fig. 6, fig. 6 is a structural diagram of an external control circuit of a ring VCO with 4 control signals according to an embodiment of the present invention; in the figure, MV1 is a tail current tube, MN1 and MP1 are input tubes and are input ports of a VCO, MN2-MN3 and MP2-MP3 are transistors of a pull-up link, MN5 and MP5 are transistors of a pull-down link, and the rest of the transistors are peripheral control circuits for adjusting oscillation frequency of a ring oscillator. The control signals CTR1-CTR4 function to compensate for the effects of process corner and temperature variations on the ring oscillator oscillation frequency in the VCO.
Initially, the four control signals are all "1" (high level) in the initial stage, and the PMOS transistors MP5, MN5, MP3, and MN3 are all in the off state, and no pull-up or pull-down current flows.
When the oscillation frequency of the ring oscillator is increased due to the process angle deviation and/or temperature variation, the signals CTR1 and CTR2 are set to be 0 (low level), so that the MP5 and MN5 in the pull-down link are conducted, a part of current flowing to the ring oscillator is pumped to GND, and the current flowing into the ring oscillator is reduced, and the oscillation frequency of the ring oscillator is reduced to a normal working range.
When the oscillation frequency of the ring oscillator is reduced due to the process angle deviation and/or temperature variation, the signals CTR3 and CTR4 are set to be 0 (low level), so that the MP3 and MN3 in the pull-up link are conducted, the current flowing into the ring oscillator is increased, and the oscillation frequency of the ring oscillator is increased to a normal working range.
In the pull-up paths MN2-MN3 and MP2-MP3, the types and the width-to-length ratios of the MOS tubes MN2 and MP2 are the same as those of the input tubes MN1 and MP1, so that the voltage frequency gain K with more constant VCO is realizedVCO. When the pull-up control signal is added, a pull-up link with the same structure as that of MN2-MN3(MP2-MP3) is required to be added; when the pull-down control signal is added, only one pair of MOS tubes is needed to be added to serve as a pull-down link.
The invention can select different control inputs under different process angles, thereby enabling the oscillation frequency to be changed within a designed range. Referring to fig. 7, fig. 7 is a structural diagram of an external control circuit of a ring VCO with 6 control signals according to an embodiment of the present invention; in this embodiment, 2 pull-down signals are added, and MOS transistors MP6 and MN6 are added beside the lower pull chain circuit MP5 and MN5 transistors, and the working principle thereof is similar to that of the 4-path control signals, and will not be described herein again.
Ideally, the larger the number of the pull-up control and the pull-down control, the larger the adjustment range of the oscillation frequency of the ring oscillator, and the higher the adjustment precision, but this will increase the circuit complexity, and the increase of the control ports will also increase the number of control signal pins outside the chip. In use, therefore, the oscillation frequency adjustment range and the adjustment precision are required to be compromised, and the number of pins and the hardware expense are required to be considered, so that the number of control signals suitable for the corresponding application scene is selected.
In the present embodiment, the external input voltage VINNAnd VINPVia a coupling capacitor CINAnd CIPThe voltage is input to the VCO input end, and is converted into a corresponding square wave signal after passing through the VCO, namely a first signal, and the square wave signal is output to the comparator array, wherein the frequency of the square wave signal is controlled by the input voltage.
In the present embodiment, the Comparator Array (Comparator Array) includes 2n-1 dynamic comparators, each of said dynamic comparators comprising a dynamic amplifier and a latch.
Referring to fig. 8a to 8b, fig. 8a to 8b are schematic structural diagrams of a dynamic comparator according to an embodiment of the present invention; fig. 8a is a schematic structural diagram of a dynamic amplifier according to an embodiment of the present invention; the dynamic amplifier comprises transistors M1-M9, wherein a source and a gate of the transistor M1 are respectively connected with a VDD terminal and a CLK signal, a drain of the transistor M1 is connected with sources of the transistors M2 and M3, gates of the transistors M2 and M3 are respectively used as input interfaces for receiving the first signal, sources of the transistors M4 and M5 are connected with each other, a gate of the transistor M6 and a gate of the transistor M9 are both connected with the CLK signal, a drain of the transistor M2, a drain of the transistor M4, a source of the transistor M6, a gate of the transistor M5, a drain of the transistor M7 and a gate of the transistor M8 are connected with each other and connected with the latch through a point; the drain of the transistor M3, the drain of the transistor M5, the drain of the transistor M6, the gate of the transistor M4, the gate of the transistor M7 and the drain of the transistor M8 are connected with each other and connected with the latch through a point B, the source of the transistor M7, the source of the transistor M8 and the drain of the transistor M9 are connected with each other, and the source of the transistor M9 is grounded;
FIG. 8b is a schematic diagram of a latch structure according to an embodiment of the present invention; the latch comprises transistors M10-M17, wherein the sources of the transistors M10-M13 are all connected with a VDD terminal, the gate of the transistor M10 and the gate of the transistor M16 are all connected with the node A, the gate of the transistor M13 and the gate of the transistor M17 are all connected with the node B, the drain of the transistor M10, the drain of the transistor M11, the gate of the transistor M14, the gate of the transistor M12 and the gate of the transistor M15 are mutually connected with a node OA, the drain of the transistor M12, the drain of the transistor M13, the drain of the transistor M15, the gate of the transistor M11 and the gate of the transistor M14 are mutually connected with a node OB, and the second signal is output through a node Q.
In this embodiment, the operation state of the dynamic comparator is divided into two stages of reset and regeneration, first, the reset stage, when CLK is low, M1 and M6 in the preamplifier are turned on, pulling A, B two nodes to high, and the nodes OA and OB have no charge and discharge paths, so the output Q remains unchanged. Then, entering a regeneration phase, when the CLK changes to a high level, M7, M8 and M9 in the preamplifier are turned on, and the discharging speed of the two nodes A, B are different because the amplitudes of the input signals at the differential ends are different. When input V of dynamic comparatorin>VipWhen the voltage of the OA node is higher than the threshold value of M15, the OB node generates a discharge path to the ground, so that the voltage of the OB node is reduced, and meanwhile due to the existence of positive feedback, the reduction of the voltage of the OB node accelerates the rapid rise of the voltage of the OA node to VDD. Thereby enabling the voltage at the Q node to build up quickly.
Referring to fig. 9, fig. 9 is a timing diagram of a dynamic comparator according to an embodiment of the invention; one end of the input end of the comparator is connected with a fixed reference level, the other end of the input end of the comparator is connected with a phase node of the output end of the VCO, and the comparator shapes the level of the output node of the VCO through comparison to obtain a high level and a low level which can be directly used by a rear-end digital module, namely a second signal and outputs the second signal to the digital accumulation unit. Compared with a structure that the output of the VCO is directly input into the register, the use of the comparator can shape the output signal of the VCO and enhance the driving capability of the signal, so that errors generated when the digital module processes the signal are reduced, and the overall precision of the circuit is improved.
Referring to fig. 10a to 10b, fig. 10a to 10b are schematic structural diagrams of a conventional dynamic comparator according to an embodiment of the present invention; fig. 10a is a schematic diagram of an amplifier structure of a conventional dynamic comparator according to an embodiment of the present invention; FIG. 10b is a diagram illustrating a latch structure of a conventional dynamic comparator according to an embodiment of the present invention; in the traditional two-stage dynamic comparator, the output result is obtained by comparing in the regeneration stage, and the output stage result of the comparator in the reset stage is reset. In the dynamic comparator adopted by the design, only the voltages of the A, B two nodes in the dynamic amplifier are reset in the reset stage; the output signals OA, OB will store the previous comparison result until the next comparison is stored in a new comparison result. The comparator can therefore simultaneously function as a holding circuit, holding the signal for half a clock cycle to allow time for the digital circuit to process the signal.
In this embodiment, a quantization module is composed of a fully differential VCO unit, a comparator array, and a digital accumulation unit, and a quantization process is completed. Referring to fig. 11, fig. 11 is a diagram illustrating a quantization diagram according to an embodiment of the present invention; in this embodiment, n is 5, where the VCO with 31-phases is a 5-stage ring VCO, and the VCO is formed by cascading 31 stages of inverse delay units end to end, and correspondingly, the number of the comparators and the registers and the number of the xor gates are 31, where the 31-bit comparator is in the dynamic comparison array, and the 31-bit registers and the 31 xor gates are both disposed in the digital accumulation unit.
When a signal is input, the frequency of the VCO changes along with the amplitude of the input signal, the phase of the VCO is sampled and shaped by the comparator and then is directly subjected to XOR operation with the phase result of the last moment stored in the register, and the variation of the current quantization relative to the previous quantization can be obtained. And the thermometer code obtained by the XOR is processed by an adder in the digital module to obtain an output binary code. The larger the input signal amplitude is, the faster the VCO oscillation frequency is, the more delay units in the VCO that have phase changes from the previous time, the more "1" s are output through the xor operation, and therefore, the larger the value of the binary code of the output obtained. Therefore, the VCO realizes a function of converting the analog input voltage into a corresponding binary code, completing quantization.
In this embodiment, except for the fully differential VCO module and the comparator array, the remaining VCO quantization module is implemented by a digital circuit, so that compared with a conventional VCO quantizer implemented by using two sets of analog register array structures, the VCO quantizer reduces circuit power consumption, reduces circuit area, and has great advantages.
In this embodiment, the feedback module 2 includes a conversion unit (BIN to THERM), a dynamic matching unit (DEM), a sample-and-hold unit (SAH), and a feedback capacitance digital-to-analog conversion unit (C-DAC); wherein the content of the first and second substances,
the conversion unit (BIN to THERM) is connected with the digital accumulation unit (Delta Sigma Accumulator) and is used for receiving and processing the digital signal and outputting a thermometer code signal;
one end of the dynamic matching unit (DEM) is connected with the conversion unit (BIN to THERM), and the other end of the dynamic matching unit (DEM) is connected with the feedback capacitance digital-to-analog conversion unit (delta-sigma C-DAC) through a sampling and holding unit (SAH), and is used for receiving the thermometer code signal and outputting a control signal to control the feedback capacitance digital-to-analog conversion unit (delta-sigma C-DAC) to randomly select a feedback sub-unit;
the slave sample and hold unit (SAH) is configured to time-delay the control signal and output a delayed signal;
the feedback capacitance digital-to-analog conversion unit (delta-sigma C-DAC) is connected with the fully differential VCO unit (VCO ADC) and is used for receiving the delay signal and regulating and controlling the input signal of the fully differential VCO unit (VCO ADC).
The feedback capacitance digital-to-analog conversion unit (delta-sigma C-DAC) comprises 2nEach C-DAC subunit comprises a capacitor CN and a capacitor CP, wherein the upper plate of the capacitor CN is connected with the N-end capacitor CI of the input capacitor CN and the fully differential VCO unit (VCO ADC), the upper plate of the capacitor CP is connected with the P-end capacitor C of the input capacitor CIPAnd between the fully differential VCO unit (VCO ADC), the lower plate of the capacitor CN and the lower plate of the capacitor CP are connected with reference voltage Vrefp and Vrefn ends through a transfer circuit (CTR switches).
In this embodiment, the conversion unit mainly converts the binary code output by the digital accumulation unit into a corresponding thermometer code and outputs the thermometer code to the dynamic matching unit.
In the present embodiment, since a 5-bit ring VCO quantizer is adopted in the system, a 5-bit C-DAC structure, i.e. 32C-DAC subunits, is adopted in the feedback design, as shown in fig. 2.
In fig. 1, an input end, an input capacitor C and an input resistor R form a first-order high-pass filter, where the input resistor R is a pseudo resistor and can be implemented by a MOS transistor using a diode connection method. Referring to fig. 12, fig. 12 is a frequency characteristic curve of an input-end high-pass filter according to an embodiment of the invention; the transfer function expression is as follows:
Figure BDA0002068453980000151
it can be seen that at dc, the transfer function amplitude is 0, so the dc signal is filtered by the filter, and therefore the high pass filter at the signal input end can filter the dc signal and noise in the input signal. Thereby improving the overall accuracy of the circuit. The output of the former-stage VCO quantizer is converted into a binary code through a digital accumulation circuit, the binary code is converted into a thermometer code through a conversion unit, after a time delay is carried out through a sampling and holding unit SAH, each level selection switch in a C-DAC array is controlled respectively, and the upper plate voltage of a capacitor array is changed into a difference value between the input voltage and the analog voltage corresponding to the output code of the VCO quantizer through charge redistribution. The SAH unit is adopted to delay the C-DAC control signal so as to ensure the stability of a feedback loop. This negative feedback process keeps the VCO input level within a small range. In the process, the mismatch between capacitors is smaller than that of resistors, so that compared with the traditional resistor type DAC, the non-linearity problem in the DAC can be reduced by adopting a capacitor type DAC structure, and the overall precision of the circuit is further improved.
In this embodiment, non-linear errors introduced by DAC feedback unit mismatch are suppressed by dynamic matching unit (DEM) matching techniques. Referring to fig. 13, fig. 13 is a schematic diagram of a DEM according to an embodiment of the present invention. The principle of the DEM is that feedback units are randomly selected for Dynamic allocation, so that the probability of each feedback unit being utilized tends to be equal and is similar to white noise, thus breaking through the original static error mode, and in the frequency domain, harmonics caused by nonlinear errors are diffused into the whole signal bandwidth, thereby improving the Spurious-Free Dynamic Range (SFDR) of the system. The invention adopts the digital circuit to realize the matching of the register, the adder, the dynamic unit and the like, has high system digitization degree, and has better adaptability to the change of the semiconductor manufacturing process while reducing the circuit area.
The Sigma-Delta modulator based on the VCO quantizer provided by the invention mainly works according to the following principle: external input voltage VINNAnd VINPVia a coupling capacitor CINAnd CIPThe voltage-controlled oscillator is input into an input end of a fully differential VCO unit, is converted into a corresponding square wave signal after passing through a VCO, and is input into one input end of a comparator array, and the other end of the comparator array is input into a fixed reference level. The comparator array compares the square wave signal output by the VCO unit with a fixed level to obtain a comparison result of 0 or 1, and the comparison result is transmitted to the post-stage digital accumulation unit. The digital accumulation unit stores the output result of the comparator in the previous period, and obtains a group of 0 or 1 values by carrying out XOR operation on the output value of the previous period and the output value of the current period, and the digital binary output code value of the modulator is obtained by adding. And then, converting the binary code value into a corresponding thermometer code through a conversion unit (BIN to THERM), disordering the sequence through a dynamic matching unit DEM algorithm, controlling a feedback capacitor DAC to obtain a corresponding analog voltage value, subtracting the analog voltage value from an external input voltage, inputting the analog voltage value into the input end of the VCO, and repeating the process.
The Sigma-Delta modulator based on the VCO quantizer combines the VCO and the Sigma-Delta ADC, utilizes the VCO as the quantizer, realizes low power supply voltage work, adopts the Sigma-Delta modulator structure, simplifies the system structure, reduces the power consumption and the area, and ensures the good performance of the circuit.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (3)

1. A Sigma-Delta modulator based on a VCO quantizer is characterized by comprising a VCO quantization module (1), a feedback module (2), an input capacitor C and an input resistor R; wherein the content of the first and second substances,
the VCO quantization module (1) is connected with an input end V through the input capacitor CINFor receiving and quantizing an input signal and outputting a digital signal; the VCO quantization module (1) comprises a fully differential VCO unit, a comparator array and a digital accumulation unit;
the fully differential VCO unit respectively passes through N-end capacitors C of the input capacitor CINAnd a P-terminal capacitor CIPConnecting differential input signals VINNAnd VINPA differential input signal receiving circuit for receiving the differential input signal and outputting a first signal;
the comparator array is connected with the fully differential VCO unit and used for receiving and processing a first signal and outputting a second signal; wherein the comparator array comprises 2n-1 dynamic comparators each comprising a dynamic amplifier and a latch;
the dynamic amplifier comprises transistors M1-M9, wherein a source and a gate of the transistor M1 are respectively connected with a VDD terminal and a CLK signal, a drain of the transistor M1 is connected with sources of the transistors M2 and M3, gates of the transistors M2 and M3 are respectively used as input interfaces for receiving the first signal, sources of the transistors M4 and M5 are connected with each other, a gate of the transistor M6 and a gate of the transistor M9 are both connected with the CLK signal, a drain of the transistor M2, a drain of the transistor M4, a source of the transistor M6, a gate of the transistor M5, a drain of the transistor M7 and a gate of the transistor M8 are connected with each other and connected with the latch through a node A; the drain of the transistor M3, the drain of M5, the drain of M6, the gate of M4, the gate of M7 and the drain of M8 are connected with each other and the latch through a node B, the source of the transistor M7, the source of M8 and the drain of M9 are connected with each other, and the source of the transistor M9 is grounded;
the latch comprises transistors M10-M17, wherein the sources of the transistors M10-M13 are all connected with a VDD terminal, the gate of the transistor M10 and the gate of the transistor M16 are all connected with the node A, the gate of the transistor M13 and the gate of the transistor M17 are all connected with the node B, the drain of the transistor M10, the drain of the transistor M11, the drain of the transistor M14, the gate of the transistor M12 and the gate of the transistor M15 are mutually connected with a node OA, the drain of the transistor M12, the drain of the transistor M13, the drain of the transistor M15, the gate of the transistor M11 and the gate of the transistor M14 are mutually connected with a node OB, and the second signal is output from a node Q through an inverter;
the digital accumulation unit is used for receiving and processing the second signal and outputting a digital signal;
the fully differential VCO unit comprises an n-stage ring oscillator and an external control circuit of m control signals, wherein n is a positive integer and is more than or equal to 1, and m is an even number and is more than or equal to 4; the n-stage ring oscillator comprises 2n1 stage of end-to-end cascaded reverse delay units, each stage being provided with a voltage control terminal VCin；
The external control circuit comprises a transistor MV1, symmetrically arranged input tubes MN1 and MP1, a symmetrically arranged N-terminal control circuit and a symmetrically arranged P-terminal control circuit, wherein,
the P-end control circuit and the N-end control circuit respectively comprise i pull-up links and j pull-down links, wherein i and j are positive integers, and i + j is m;
the input end of the feedback module (2) is connected with the output end of the VCO quantization module (1), and the output end of the feedback module (2) is connected with the input end of the VCO quantization module (1) and is used for feeding back the output code of the VCO quantization module (1) to the input end;
one end of the input resistor R is connected between the input capacitor C and the VCO quantization module (1), and the other end of the input resistor R is connected with VCMA level.
2. The modulator according to claim 1, characterized in that the feedback module (2) comprises a conversion unit, a dynamic matching unit, a sample-and-hold unit and a feedback capacitance digital-to-analog conversion unit; wherein the content of the first and second substances,
the conversion unit is connected with the digital accumulation unit and is used for receiving and processing the digital signal and outputting a thermometer code signal;
one end of the dynamic matching unit is connected with the conversion unit, and the other end of the dynamic matching unit is connected with the feedback capacitor digital-to-analog conversion unit through a sampling and holding unit and is used for receiving the thermometer code signal and outputting a control signal to control the feedback capacitor digital-to-analog conversion unit to randomly select a feedback sub-unit;
the sampling and holding unit is used for carrying out time delay on the control signal and outputting a delay signal;
the feedback capacitance digital-to-analog conversion unit is connected with the fully-differential VCO unit and used for receiving the delay signal and regulating and controlling the input signal of the fully-differential VCO unit.
3. The modulator according to claim 2, wherein the feedback capacitance digital-to-analog conversion unit comprises 2nA stage C-DAC subunit, wherein each bit of the C-DAC subunit comprises a capacitor CNAnd a capacitor CPSaid capacitor CNThe upper electrode plate of the capacitor is connected with the N-end capacitor C of the input capacitor CINAnd said capacitor C between said fully differential VCO cellPThe upper electrode plate of the capacitor is connected with a P-end capacitor C of the input capacitor CIPAnd said capacitor C between said fully differential VCO cellNLower plate of and said capacitor CPThe lower polar plate is connected with a reference voltage V through a conversion circuitrefpAnd VrefnAnd (4) an end.
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